diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml deleted file mode 100644 index 3b3666be..00000000 --- a/.github/workflows/build.yml +++ /dev/null @@ -1,161 +0,0 @@ -# Copyright 2026 Arm Limited and/or its affiliates. -# SPDX-License-Identifier: Apache-2.0 -# -# CI for the three-step flow (cbuild setup, create_ai_layer.py, cbuild) -# followed by an FVP run, with each of the three toolchains. -name: Build and Run - -on: - workflow_dispatch: - push: - branches: [main] - pull_request: - branches: [main] - -env: - SOLUTION: cmsis-executorch - TARGET: SSE-320-U85 - -jobs: - # Full build plus an FVP run, once per toolchain. Linux only: the FVP needs - # an Arm user-based license, so matrixing this across hosts is not cheap. - build-and-run: - name: Build and run on Corstone-320 (${{ matrix.toolchain }}) - runs-on: ubuntu-latest - - strategy: - fail-fast: false - matrix: - toolchain: [AC6, GCC, CLANG] - - steps: - - name: Checkout repo - uses: actions/checkout@v7 - - - name: Install tools - uses: ARM-software/cmsis-actions/vcpkg@v1 - - - name: Activate Arm tool license - uses: ARM-software/cmsis-actions/armlm@v1 - - # The FVP loads the runner's libpython3.11, whose standard library is - # not where that build's prefix says; the model then dies at start-up - # with "Fatal Python error: init_fs_encoding". PYTHONHOME (set on the - # FVP step only) points it at a complete Python 3.11. - - name: Set up Python 3.11 for the FVP - uses: actions/setup-python@v5 - with: - python-version: '3.11' - - - name: Cache packs - uses: actions/cache@v6 - with: - key: cmsis-packs-${{ hashFiles('*.csolution.yml') }} - path: /home/runner/.cache/arm/packs - - # torch + executorch is a multi-gigabyte install and otherwise dominates - # the job. Keyed on the requirements files so a pin change rebuilds it. - - name: Cache model-export venv - uses: actions/cache@v6 - with: - key: venv-${{ runner.os }}-${{ hashFiles('requirements*.txt', 'setup_venv.py') }} - path: .venv - - - name: Create model-export venv - run: ./setup_venv.sh - - - name: Generate the MLOps information - run: cbuild setup ${SOLUTION}.csolution.yml --active ${TARGET} --packs - - - name: Create the AI layer - run: python3 create_ai_layer.py ${SOLUTION}.cbuild-mlops.yml - - - name: Build - run: cbuild ${SOLUTION}.csolution.yml --active ${TARGET} --toolchain ${{ matrix.toolchain }} - - - name: Run on the FVP - env: - PYTHONHOME: ${{ env.pythonLocation }} - run: | - IMAGE=$(find out -name "${SOLUTION}.axf" -o -name "${SOLUTION}.elf" | head -1) - echo "Running ${IMAGE}" - # stdio is retargeted to semihosting, so the output arrives on the - # FVP's own stdout. - FVP_Corstone_SSE-320 \ - -f board/Corstone-320/fvp_config.txt \ - -a "${IMAGE}" \ - --simlimit 60 --stat \ - | tee fvp_stdout.log - - echo "Checking simulation output" - grep -q "Test_result: PASS" fvp_stdout.log - - - name: Upload artifacts - if: always() - uses: actions/upload-artifact@v4 - with: - name: corstone-320-${{ matrix.toolchain }} - path: | - fvp_stdout.log - out/**/*.axf - out/**/*.elf - ai_layer/ - - # The export flow must work on all three host OSes -- that is the point of a - # venv-based (rather than Docker-based) model build. No FVP and no Arm - # license needed, so this is cheap to matrix. Without this job, Windows - # support regresses on the first refactor and nobody notices. - venv-cross-platform: - name: Export environment check, import only (${{ matrix.os }}) - runs-on: ${{ matrix.os }} - - strategy: - fail-fast: false - matrix: - os: [ubuntu-latest, macos-latest, windows-latest] - - steps: - - name: Checkout repo - uses: actions/checkout@v7 - - - name: Set up Python - uses: actions/setup-python@v5 - with: - python-version: '3.12' - - - name: Create model-export venv (POSIX) - if: runner.os != 'Windows' - run: ./setup_venv.sh - - - name: Create model-export venv (Windows) - if: runner.os == 'Windows' - run: .\setup_venv.bat - - - name: Check the export entry point - shell: bash - run: | - if [ "$RUNNER_OS" = "Windows" ]; then - PY=.venv/Scripts/python.exe - else - PY=.venv/bin/python - fi - "${PY}" -c "import executorch.backends.arm.quantizer.quantization_annotator; print('arm quantizer OK')" - # No cbuild-mlops.yml without cbuild; importing the script checks - # that it parses under this interpreter. - "${PY}" -c "import create_ai_layer; print('create_ai_layer.py OK')" - - - name: Report resolved versions - shell: bash - run: | - if [ "$RUNNER_OS" = "Windows" ]; then - PY=.venv/Scripts/python.exe - else - PY=.venv/bin/python - fi - "${PY}" -m pip list | grep -iE "torch|executorch|vela|tosa|flatbuffers" - # flatbuffers must stay at 24.3.25 (the Arm backend's pin): tosa-tools - # wants 25.2.10 and is installed --no-deps precisely to stop that. See - # requirements-arm-tosa.txt. - # No grep -q: with pipefail, grep closing the pipe early fails the step. - "${PY}" -m pip show flatbuffers | grep "Version: 24.3.25" \ - || { echo "::error::flatbuffers pin regressed"; exit 1; } diff --git a/.github/workflows/test-cmsis-executorch-u55.yml b/.github/workflows/test-cmsis-executorch-u55.yml new file mode 100644 index 00000000..531dee53 --- /dev/null +++ b/.github/workflows/test-cmsis-executorch-u55.yml @@ -0,0 +1,95 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# Generated with AI and adapted from the create-csolution-github-action skill. + +name: Build and test Ethos-U55-128 + +on: + workflow_dispatch: + pull_request: + branches: [main] + push: + branches: [main] + +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +jobs: + build-and-test: + name: Corstone-300 / Ethos-U55-128 (${{ matrix.toolchain }}) + runs-on: ubuntu-latest + + strategy: + fail-fast: false + matrix: + toolchain: [AC6, GCC, CLANG] + + steps: + - uses: actions/checkout@v7 + + - name: Activate vcpkg environment + uses: ARM-software/cmsis-actions/vcpkg@v1 + with: + config: vcpkg-configuration.json + cache: cmsis-executorch + + # The default Arm license setup is for evaluation only. + - name: Activate Arm tool license + uses: ARM-software/cmsis-actions/armlm@v1 + + - name: Set up Python 3.11 + uses: actions/setup-python@v5 + with: + python-version: "3.11" + + - name: Cache CMSIS packs + uses: actions/cache@v6 + with: + key: cmsis-packs-u55-${{ hashFiles('*.csolution.yml', 'board/Corstone-300/*.clayer.yml') }} + path: /home/runner/.cache/arm/packs + + - name: Cache model-export environment + uses: actions/cache@v6 + with: + key: model-export-${{ runner.os }}-${{ hashFiles('requirements*.txt', 'setup_venv.py') }} + path: .venv + + - name: Create model-export environment + run: ./setup_venv.sh + + - name: Generate U55 MLOps information + run: cbuild setup cmsis-executorch-u55.csolution.yml --active SSE-300-U55 --packs + + - name: Create U55 AI layer + run: .venv/bin/python create_ai_layer.py cmsis-executorch-u55.cbuild-mlops.yml + + - name: Build SSE-300-U55 + run: cbuild cmsis-executorch-u55.csolution.yml --active SSE-300-U55 --packs --toolchain ${{ matrix.toolchain }} + + - name: Run SSE-300-U55 on FVP simulation + env: + PYTHONHOME: ${{ env.pythonLocation }} + run: | + set -o pipefail + FVP_Corstone_SSE-300_Ethos-U55 \ + -f board/Corstone-300/fvp_config_u55.txt \ + -a out/*/SSE-300-U55/*/*.hex \ + --simlimit 120 2>&1 | tee fvp.log + + - name: Check application result + run: 'grep -Fq "Test_result: PASS" fvp.log' + + - name: Upload build artifacts + if: always() + uses: actions/upload-artifact@v7 + with: + name: cmsis-executorch-SSE-300-U55-${{ matrix.toolchain }} + path: | + out + ai_layer + fvp.log + if-no-files-found: warn diff --git a/.github/workflows/test-cmsis-executorch.yml b/.github/workflows/test-cmsis-executorch.yml new file mode 100644 index 00000000..624d7841 --- /dev/null +++ b/.github/workflows/test-cmsis-executorch.yml @@ -0,0 +1,96 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# Generated with AI and adapted from the create-csolution-github-action skill. + +name: Build and test Ethos-U85-256 + +on: + workflow_dispatch: + pull_request: + branches: [main] + push: + branches: [main] + +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +jobs: + build-and-test: + name: Corstone-320 / Ethos-U85-256 (${{ matrix.toolchain }}) + runs-on: ubuntu-latest + + strategy: + fail-fast: false + matrix: + toolchain: [AC6, GCC, CLANG] + + steps: + - uses: actions/checkout@v7 + + - name: Activate vcpkg environment + uses: ARM-software/cmsis-actions/vcpkg@v1 + with: + config: vcpkg-configuration.json + cache: cmsis-executorch + + # The default Arm license setup is for evaluation only. + - name: Activate Arm tool license + uses: ARM-software/cmsis-actions/armlm@v1 + + - name: Set up Python 3.11 + uses: actions/setup-python@v5 + with: + python-version: "3.11" + + - name: Cache CMSIS packs + uses: actions/cache@v6 + with: + key: cmsis-packs-u85-${{ hashFiles('*.csolution.yml', 'board/Corstone-320/*.clayer.yml') }} + path: /home/runner/.cache/arm/packs + + - name: Cache model-export environment + uses: actions/cache@v6 + with: + key: model-export-${{ runner.os }}-${{ hashFiles('requirements*.txt', 'setup_venv.py') }} + path: .venv + + - name: Create model-export environment + run: ./setup_venv.sh + + - name: Generate U85 MLOps information + run: cbuild setup cmsis-executorch.csolution.yml --active SSE-320-U85 --packs + + - name: Create U85 AI layer + run: .venv/bin/python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml + + - name: Build SSE-320-U85 + run: cbuild cmsis-executorch.csolution.yml --active SSE-320-U85 --packs --toolchain ${{ matrix.toolchain }} + + - name: Run SSE-320-U85 on FVP simulation + env: + PYTHONHOME: ${{ env.pythonLocation }} + run: | + set -o pipefail + FVP_Corstone_SSE-320 \ + -f board/Corstone-320/fvp_config.txt \ + -a out/*/SSE-320-U85/*/*.hex \ + --simlimit 120 2>&1 | tee fvp.log + + - name: Check application result + run: 'grep -Fq "Test_result: PASS" fvp.log' + + - name: Upload build artifacts + if: always() + uses: actions/upload-artifact@v7 + with: + name: cmsis-executorch-SSE-320-U85-${{ matrix.toolchain }} + path: | + out + ai_layer + fvp.log + if-no-files-found: warn + diff --git a/.github/workflows/test-python-environment.yml b/.github/workflows/test-python-environment.yml new file mode 100644 index 00000000..f7500f94 --- /dev/null +++ b/.github/workflows/test-python-environment.yml @@ -0,0 +1,67 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 + +name: Test Python environment + +on: + workflow_dispatch: + pull_request: + branches: [main] + push: + branches: [main] + +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.ref }} + cancel-in-progress: true + +jobs: + venv-cross-platform: + name: Python environment (${{ matrix.os }}) + runs-on: ${{ matrix.os }} + + strategy: + fail-fast: false + matrix: + os: [ubuntu-latest, macos-latest, windows-latest] + + steps: + - uses: actions/checkout@v7 + + - name: Set up Python 3.12 + uses: actions/setup-python@v5 + with: + python-version: "3.12" + + - name: Create model-export environment + if: runner.os != 'Windows' + run: ./setup_venv.sh + + - name: Create model-export environment + if: runner.os == 'Windows' + run: .\setup_venv.bat + + - name: Check model-export environment + shell: bash + run: | + if [ "$RUNNER_OS" = "Windows" ]; then + PY=.venv/Scripts/python.exe + else + PY=.venv/bin/python + fi + "${PY}" -c "import executorch.backends.arm.quantizer.quantization_annotator; print('arm quantizer OK')" + "${PY}" -c "import create_ai_layer; print('create_ai_layer.py OK')" + + - name: Check resolved package versions + shell: bash + run: | + if [ "$RUNNER_OS" = "Windows" ]; then + PY=.venv/Scripts/python.exe + else + PY=.venv/bin/python + fi + "${PY}" -m pip list | grep -iE "torch|executorch|vela|tosa|flatbuffers" + "${PY}" -m pip show flatbuffers | grep "Version: 24.3.25" \ + || { echo "::error::flatbuffers pin regressed"; exit 1; } diff --git a/.gitignore b/.gitignore index b978bff9..6fc2d8be 100644 --- a/.gitignore +++ b/.gitignore @@ -2,6 +2,7 @@ .venv/ __pycache__/ *.pyc +*.bak # The exported ExecuTorch program. create_ai_layer.py writes it next to the # generated AI layer; the C array in ai_layer/model_pte.c is what gets built. diff --git a/.vscode.d/tasks.json b/.vscode.d/tasks.json index f53c3464..10f44f70 100644 --- a/.vscode.d/tasks.json +++ b/.vscode.d/tasks.json @@ -2,7 +2,8 @@ "version": "2.0.0", "tasks": [ { - "label": "Setup Python virtual environment", + "label": "Create Python environment (pip)", + "detail": "Create .venv with the installed Python and pip, then install the model-export dependencies", "type": "shell", "command": "./setup_venv.sh", "windows": { @@ -14,8 +15,8 @@ "problemMatcher": [] }, { - "label": "Setup Python virtual environment (uv)", - "detail": "Same as above, but with uv (must be on PATH): uv creates .venv for the Python version you enter and can download that interpreter", + "label": "Create Python environment (uv)", + "detail": "Create .venv with uv, optionally downloading the selected Python version; requires uv on PATH", "type": "shell", "command": "./setup_venv.sh", "windows": { @@ -29,10 +30,13 @@ }, { "label": "Create AI layer", - "detail": "Export model/model.py for the NPU in cmsis-executorch.cbuild-mlops.yml and write ai_layer/ (run a CMSIS build or 'cbuild setup' first)", + "detail": "Export model/model.py for the active solution's NPU and write ai_layer (run 'cbuild setup' first)", "type": "shell", "command": "${workspaceFolder}/.venv/bin/python", - "args": ["create_ai_layer.py", "cmsis-executorch.cbuild-mlops.yml"], + "args": [ + "create_ai_layer.py", + "${command:cmsis-csolution.getSolutionName}.cbuild-mlops.yml" + ], "windows": { "command": "${workspaceFolder}\\.venv\\Scripts\\python.exe" }, diff --git a/README.md b/README.md index 1e35f0fa..4786beda 100644 --- a/README.md +++ b/README.md @@ -1,20 +1,35 @@ # ExecuTorch on Ethos-U -This example shows how to deploy and run an -[ExecuTorch](https://github.com/pytorch/executorch) model on an Arm Ethos-U NPU. -The pack [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) -provides the source code components to build the ExecuTorch runtime, required operators, and Ethos-U backend. -The build process uses the [CMSIS-Toolbox 2.15.0](https://open-cmsis-pack.github.io/cmsis-toolbox/) or higher. - -This example application targets the Arm Corstone-320 reference platform with -an Ethos-U85 NPU. It demonstrates the same overall workflow used for other -Ethos-U systems: export and quantize a PyTorch model, delegate it to Ethos-U, -select only the required runtime components, and build it into an embedded -application. - -## What the example demonstrates - -- Exporting an ExecuTorch model for Ethos-U from a Python virtual environment. +[![Build and test Ethos-U85-256](https://github.com/Arm-Examples/CMSIS-Executorch/actions/workflows/test-cmsis-executorch.yml/badge.svg)](https://github.com/Arm-Examples/CMSIS-Executorch/actions/workflows/test-cmsis-executorch.yml) +[![Build and test Ethos-U55-128](https://github.com/Arm-Examples/CMSIS-Executorch/actions/workflows/test-cmsis-executorch-u55.yml/badge.svg)](https://github.com/Arm-Examples/CMSIS-Executorch/actions/workflows/test-cmsis-executorch-u55.yml) +[![Test Python environment](https://github.com/Arm-Examples/CMSIS-Executorch/actions/workflows/test-python-environment.yml/badge.svg)](https://github.com/Arm-Examples/CMSIS-Executorch/actions/workflows/test-python-environment.yml) +[![License: Apache-2.0](https://img.shields.io/badge/License-Apache--2.0-green.svg)](LICENSE) +[![CMSIS-Toolbox: 2.15](https://img.shields.io/badge/CMSIS--Toolbox-2.15-blue.svg)](https://open-cmsis-pack.github.io/cmsis-toolbox/) +[![ExecuTorch: 1.5.1](https://img.shields.io/badge/ExecuTorch-1.5.1-blue.svg)](https://www.keil.arm.com/packs/executorch-pytorch/) + +This repository is a template for creating embedded applications that deploy +and run an [ExecuTorch](https://github.com/pytorch/executorch) ML model on an Arm +Ethos-U NPU. + +- The [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) + pack provides the ExecuTorch runtime, required operators, and Ethos-U backend. +- The [`ARM::CMSIS-Ethos-U`](https://www.keil.arm.com/packs/cmsis-ethos-u-arm/overview/) + pack provides Ethos-U drivers, configuration support, Corstone reference + integrations and examples, and documentation for deploying ML models on + Ethos-U. +- The build process uses [CMSIS-Toolbox 2.15.0](https://open-cmsis-pack.github.io/cmsis-toolbox/) + or higher. + +The template can be used for applications targeting any Ethos-U configuration; +the default solution targets the Arm Corstone-320 reference platform with an +Ethos-U85 NPU. The same workflow applies to other ML models, targets, and +applications: export and quantize an ML model developed in PyTorch, delegate it +to Ethos-U, select only the required runtime components, and build it into an +embedded application. + +## What the template provides + +- Exporting an ExecuTorch ML model for Ethos-U from a Python virtual environment. - The pack [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) links only the required and operator components that the ML model needs. - Managing the NPU and Vela configuration in the CMSIS solution project rather than duplicating it in the Python exporter. - A three-step flow with a clean hand-over from the CMSIS-Toolbox to an MLOps system: the toolbox describes the target in a `*.cbuild-mlops.yml` file, a script turns that into the AI layer, and the toolbox builds the application. @@ -22,49 +37,78 @@ application. ## Prerequisites -- Python `>=3.10,<3.14` (tosa-tools 2026.5.0 has no 3.14 wheels). +- [Git](https://git-scm.com/) to clone the repository created from this template. - [Keil Studio for VS Code](https://marketplace.visualstudio.com/items?itemName=Arm.keil-studio-pack) from the VS Code marketplace. -- Tools listed in [`vcpkg-configuration.json`](./vcpkg-configuration.json). -- Keil Studio manages the required license; the free Keil MDK Community edition can be used for evaluation. - [Python extension for VS Code](https://marketplace.visualstudio.com/items?itemName=ms-python.python). +- [Astral's uv](https://docs.astral.sh/uv/getting-started/installation/) on `PATH` for the + recommended environment task, or an installed Python `>=3.10,<3.14` for pip. +- On macOS, follow [FVPs on macOS](https://github.com/Arm-Examples/FVPs-on-Mac) + to install Docker Desktop and configure the FVP environment. + +Keil Studio manages the required license; the free Keil MDK Community edition +can be used for evaluation. + +> [!NOTE] +> On Windows, enable [long-path support](https://learn.microsoft.com/windows/win32/fileio/maximum-file-path-limitation#enable-long-paths-in-windows-10-version-1607-and-later). + +## Quick start + +The steps below build the default Corstone-320 / Ethos-U85-256 application +using `cmsis-executorch.csolution.yml`. The alternative +`cmsis-executorch-u55.csolution.yml` targets Corstone-300 / Ethos-U55-128. +Both can be built and run entirely in Keil Studio for VS Code. + +### 1. Create the application + +On [GitHub](https://github.com/Arm-Examples/CMSIS-Executorch), select **Use this +template** to create your application repository, then clone it and open its +folder in VS Code. In the CMSIS view, select **... > Select Active Solution +from Workspace**, then choose `cmsis-executorch.csolution.yml` for this Quick +start. -The pack [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) can be optionally installed manually with: +### 2. Set up the project tools + +When the folder opens, Arm Environment Manager installs the tools listed in +`vcpkg-configuration.json`. + +To set up ML model export, select **Terminal > Run Task > Create Python environment +(uv)**. This task uses [Astral's uv](https://docs.astral.sh/uv/) from `PATH` and can +download a supported Python (`>=3.10,<3.14`) before installing the dependencies. +Alternatively, **Create Python environment (pip)** uses a compatible Python +already installed on the host. Python 3.14 is not supported because +tosa-tools 2026.5.0 has no 3.14 wheels. + +The [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) +pack is resolved through the Arm pack service. To install it manually instead: ```bash cpackget add PyTorch::ExecuTorch@1.5.1 ``` -> [!Note] -> The pack and Python exporter versions must match, as the generated `.pte` -> format is consumed by the runtime supplied in `PyTorch::ExecuTorch@1.5.1`. -> The matching wheel is `executorch==1.5.1` from PyPI, pinned in -> `requirements.txt`. +> [!IMPORTANT] +> The pack and [ExecuTorch Python exporter](https://docs.pytorch.org/executorch/stable/getting-started.html) +> versions must match, as the generated `.pte` is consumed by the runtime in +> `PyTorch::ExecuTorch@1.5.1`. The matching `executorch==1.5.1` wheel is pinned +> in `requirements.txt`. -## Quick start +### 3. Build and run + +The repository contains the generated U85 AI layer, so the default solution +builds immediately. After changing the ML model or target, select **Terminal > Run +Task > Create AI layer**. The task exports the ML model for the active solution's +NPU from its `*.cbuild-mlops.yml` file and rewrites `ai_layer/`. -The example can be built and run entirely in Keil Studio for VS Code. - -1. Install [Keil Studio for VS Code](https://marketplace.visualstudio.com/items?itemName=Arm.keil-studio-pack) and [Python extension](https://marketplace.visualstudio.com/items?itemName=ms-python.python) from the VS Code marketplace. -2. Clone or download this repository, then open its folder in VS Code. -3. Before using the example for the first time, select **Terminal > Run Task > - Setup Python virtual environment**. Wait for the task to create the `.venv` - environment and install the packages required to export the model. (The - **(uv)** variant of the task uses [uv](https://docs.astral.sh/uv/) instead - of pip and can download the Python version it asks for.) -4. Select **Terminal > Run Task > Create AI layer**. This exports the model for - the NPU of the active target and writes the `ai_layer/` directory. It reads - `cmsis-executorch.cbuild-mlops.yml`, which the extension writes when the - solution is loaded or built (`cbuild setup` on the command line). The - repository ships a generated layer, so this step is only needed after - changing the model or the target. -5. Use the CMSIS action buttons to build the application, then select **Run** or - **Debug**. Keil Studio starts the Corstone-320 FVP automatically. On macOS, - where Arm ships no FVP build, run the model in Docker instead: set `model:` - in the csolution's target-set to `${workspaceFolder}/.vscode/fvp.sh` and - copy `.vscode/launch.json.mac` to `.vscode/launch.json` (its debug - configuration waits for the model to come up in the container). Docker - Desktop must be running, and the first Run or Debug builds the container - image (about 100 MB download). +To use Ethos-U55-128 instead, select +`cmsis-executorch-u55.csolution.yml` as the active solution and run **Create AI +layer** before building. + +Use the CMSIS action buttons to build the application, then select **Run** or +**Debug**. Keil Studio starts the selected FVP simulation model automatically. +On macOS, where Arm ships no native FVP, set `model:` in the active csolution's +target-set to `${workspaceFolder}/.vscode/fvp.sh` and copy +`.vscode/launch.json.mac` to +`.vscode/launch.json`. Docker Desktop must be running; the first Run or Debug +builds the container image (about 100 MB download). A successful run prints the Ethos-U configuration, output logits, and a pass result: @@ -74,7 +118,7 @@ Ethos-U version info: Arch: v2.0.0 MACs/cc: 256 Cmd stream: v1 -ExecuTorch Ethos-U85 example: 8720 byte model +ExecuTorch Ethos-U85-256 application: 8720 byte model Output: 10 element(s): -0.0142 0.0206 0.0601 -0.0886 0.0791 0.0522 -0.0301 -0.0775 -0.2800 -0.0095 Test_result: PASS ``` @@ -100,20 +144,16 @@ On Windows: ``` The setup script creates `.venv/` and installs the packages required to -quantize and export the model. It is safe to run again; use `--recreate` when +quantize and export the ML model. It is safe to run again; use `--recreate` when you want a completely new environment. The wrappers use `python3` (`python` on Windows); point them at another interpreter with `PYTHON=python3.12 ./setup_venv.sh`. -With [uv](https://docs.astral.sh/uv/getting-started/installation/) on `PATH`, +With [Astral's uv](https://docs.astral.sh/uv/getting-started/installation/) on `PATH`, `./setup_venv.sh --uv --python 3.12` (or `.\setup_venv.bat ...`) creates the environment with `uv venv` for that Python version, downloading the interpreter if needed, and installs with `uv pip`. Add `--recreate` to change the Python version of an existing environment. -> [!Note] -> On Windows, enable long-path support or keep the repository close to the drive -> root. PyTorch packages can otherwise exceed the legacy 260-character path limit. - #### 1. Generate the MLOps information ```bash @@ -134,7 +174,7 @@ python3 create_ai_layer.py cmsis-executorch.cbuild-mlops.yml This is the MLOps step. The script reads the NPU and Vela settings from the file, quantizes and exports `model/model.py` for that NPU, and writes the -complete AI layer into `ai_layer/`: the component selection and the model as a +complete AI layer into `ai_layer/`: the component selection and the ML model as a C array. It runs itself in `.venv` when started with another interpreter (use `python` on Windows). @@ -158,10 +198,11 @@ FVP_Corstone_SSE-320 \ -a out/cmsis-executorch/SSE-320-U85/Debug/cmsis-executorch.axf ``` -This is the model command the Run and Debug buttons use too. On macOS, call -`.vscode/fvp.sh` with the same arguments; it runs the model in Docker. +This is the FVP command the Run and Debug buttons use too. On macOS, call +`.vscode/fvp.sh` with the same arguments; it runs the FVP simulation model in +Docker. -## How model generation works +## How ML model generation works The target is described by the `mlops:` node in `cmsis-executorch.csolution.yml`: @@ -182,14 +223,15 @@ mlops: `cbuild setup --active SSE-320-U85` resolves it into `cmsis-executorch.cbuild-mlops.yml`, which contains the processor, NPU -and Vela options, and the FVP target-set as the `simulator:` to test on. +and Vela options, and the FVP simulation target-set as the `simulator:` to test +on. `create_ai_layer.py` reads those options and passes all of them to ExecuTorch's `EthosUCompileSpec`, so the target configuration is never duplicated in -Python. The two extra keys under `model:` are parameters of the model itself; +Python. The two extra keys under `model:` are parameters of the ML model itself; the toolbox passes them through and the script hands them to `model/model.py`. The script then writes: -- `ai_layer/ai_layer.clayer.yml`: the CMSIS components required by the model. +- `ai_layer/ai_layer.clayer.yml`: the CMSIS components required by the ML model. - `ai_layer/model_pte.c` and `model_pte.h`: the ExecuTorch program embedded as a C array. - `ai_layer/model.pte`: the program itself, for inspection. @@ -197,27 +239,27 @@ See [the MLOps flow](documentation/mlops-flow.md) for a detailed walkthrough. ## Component selection -The [ExecuTorch CMSIS Pack](https://www.keil.arm.com/packs/executorch-pytorch/) +The [ExecuTorch pack](https://www.keil.arm.com/packs/executorch-pytorch/) provides the runtime, backends, and individual operators as selectable CMSIS components. `create_ai_layer.py` examines the exported program and writes `ai_layer/ai_layer.clayer.yml` so only the required components are linked. -Because the layer is complete before the build starts, a model change that +Because the layer is complete before the build starts, an ML model change that changes the operator set needs nothing more than re-running steps 2 and 3. -## Adapting the example +## Adapting the template -To use a different model, replace or modify `model/model.py` and update the -model name or input handling as required: `get_model(input_shape)` builds the -model for the `input-shape` of the `mlops:` node, and +To use a different ML model, replace or modify `model/model.py` and update the +ML model name or input handling as required: `get_model(input_shape)` builds the +ML model for the `input-shape` of the `mlops:` node, and `get_calibration_inputs(input_shape, calibration_samples)` returns the samples the quantizer is calibrated with; give it representative data for a trained -model. The runner in `src/app_main.cpp` builds its input tensor with the same -fixed shape and prints the output as ten floats, so a model with another input -shape or output needs matching changes there. Then re-run `create_ai_layer.py` -and build. +ML model. The runner in `src/app_main.cpp` builds its input tensor with the same +fixed shape and prints the output as ten floats, so an ML model with another +input shape or output needs matching changes there. Then re-run +`create_ai_layer.py` and build. -Give an image model its input as NHWC, the layout of a camera frame, as -`model/model.py` does: the model permutes it to the NCHW its convolutions take, +Give a vision ML model its input as NHWC, the layout of a camera frame, as +`model/model.py` does: the ML model permutes it to the NCHW its convolutions take, and Vela folds that into the first convolution. With an NCHW input the NPU first reorders the image in an operation of its own. @@ -228,43 +270,57 @@ further Vela option, for example `--optimise Size`. Moving to a different board or reference platform also requires the corresponding device pack, board support, memory layout, and FVP configuration. -When updating ExecuTorch, update the CMSIS pack and Python package versions +When updating ExecuTorch, update the pack and Python package versions together. More information is available in -[pack provenance](documentation/pack-provenance.md). +[ExecuTorch pack maintenance and versioning](documentation/executorch-pack-maintenance.md). + +## Continuous integration + +Two GitHub Actions workflows validate the supplied Ethos-U configurations on +every push and pull request to `main`. They create the Python environment, +generate the target-specific AI layer, build the Corstone-320/Ethos-U85-256 and +Corstone-300/Ethos-U55-128 solutions with AC6, GCC, and Clang, run each +application on its FVP simulation model, verify the reported test result, and +upload the build artifacts. A separate workflow verifies the Python environment +setup on Linux, macOS, and Windows. The badges at the top of this README show +the current status of all three workflows. ## Project layout | Path | Purpose | | ------ | --------- | -| `cmsis-executorch.csolution.yml` | Solution, target, and MLOps configuration | +| `cmsis-executorch.csolution.yml` | Corstone-320 / Ethos-U85 solution and MLOps configuration | +| `cmsis-executorch-u55.csolution.yml` | Corstone-300 / Ethos-U55-128 solution and MLOps configuration | | `cmsis-executorch.cproject.yml` | Application project: sources plus the Board and AI layers | -| `model/model.py` | Example TinyCNN model | -| `create_ai_layer.py` | Exports the model for the target and writes the AI layer | -| `ai_layer/` | Generated: component selection and the embedded model data | +| `model/model.py` | Starter TinyCNN ML model | +| `create_ai_layer.py` | Exports the ML model for the target and writes the AI layer | +| `ai_layer/` | Generated: component selection and the embedded ML model data | | `setup_venv.py` (`.sh` / `.bat`) | Creates the Python environment for the export | | `.vscode.d/tasks.json` | The VS Code tasks (venv setup, Create AI layer) merged by the CMSIS Solution extension | | `.vscode/fvp.sh`, `.vscode/fvp.Dockerfile`, `.vscode/launch.json.mac` | macOS only: runs the FVP in Docker, and the debug configuration that waits for it | -| `board/Corstone-320/` | Corstone-320 platform support and FVP configuration | -| `src/app_main.cpp` | Loads the model, runs inference, and prints the result; pool sizes overridable with `APP_METHOD_POOL_SIZE`, `APP_TEMP_POOL_SIZE`, `APP_POOL_SECTION` | +| `board/Corstone-300/`, `board/Corstone-320/` | Platform support and FVP configurations | +| `src/app_main.cpp` | Loads the ML model, runs inference, and prints the result; pool sizes overridable with `APP_METHOD_POOL_SIZE`, `APP_TEMP_POOL_SIZE`, `APP_POOL_SECTION` | | `src/arm_embedded_module.*` | `EmbeddedModule`: ExecuTorch's `Module` class without the POSIX file loading (BSD-3-Clause, `src/LICENSE-ExecuTorch`) | | `documentation/mlops-flow.md` | The MLOps flow in detail | -| `documentation/pack-provenance.md` | Where the ExecuTorch pack comes from, how to update it | +| `documentation/executorch-pack-maintenance.md` | Where the ExecuTorch pack comes from, how to update it | -## Known limitations +## Usage notes -- The supplied platform configuration targets Corstone-320 with Ethos-U85; - another target needs its corresponding platform integration. +The generated `ai_layer/` is target-specific. After switching targets, run +`create_ai_layer.py` with the selected solution's `*.cbuild-mlops.yml`. ## License -The example code is licensed under Apache-2.0; see `LICENSE`. ExecuTorch and +The template code is licensed under Apache-2.0; see `LICENSE`. ExecuTorch and `src/arm_embedded_module.*`, which is derived from it, use a BSD-3-Clause license; see `src/LICENSE-ExecuTorch`. ## References -- [PyTorch ExecuTorch CMSIS Pack](https://www.keil.arm.com/packs/executorch-pytorch/) +- [PyTorch ExecuTorch pack](https://www.keil.arm.com/packs/executorch-pytorch/) - [ExecuTorch](https://github.com/pytorch/executorch) - [ExecuTorch Arm Ethos-U backend](https://docs.pytorch.org/executorch/main/backends-arm-ethos-u.html) +- [CMSIS-Ethos-U documentation](https://arm-software.github.io/CMSIS-Ethos-U/) +- [CMSIS-Ethos-U pack](https://www.keil.arm.com/packs/cmsis-ethos-u-arm/overview/) - [CMSIS-Toolbox MLOps information](https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information) - [Arm CMSIS documentation](https://arm-software.github.io/CMSIS_6/latest/index.html) diff --git a/RTE/_Debug_SSE-300-U55/Pre_Include_Global.h b/RTE/_Debug_SSE-300-U55/Pre_Include_Global.h new file mode 100644 index 00000000..d8f319f9 --- /dev/null +++ b/RTE/_Debug_SSE-300-U55/Pre_Include_Global.h @@ -0,0 +1,26 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.15.0 + * + * Project: 'cmsis-executorch.Debug+SSE-300-U55' + * Target: 'Debug+SSE-300-U55' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U55@2.0.0 */ +// enabling global pre includes + #define ETHOSU55 + #define ETHOSU_ARCH u55 +/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.5.1 */ +#define EXECUTORCH_BUILD_ARM_BAREMETAL 1 + #define ET_USE_ETHOS_U_BACKEND 1 +/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.5.1 */ +/* ExecuTorch global configuration */ + #define C10_USING_CUSTOM_GENERATED_MACROS + #define FLATBUFFERS_MAX_ALIGNMENT 1024 + #define FLATBUFFERS_LOCALE_INDEPENDENT 0 + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/RTE/_Debug_SSE-300-U55/RTE_Components.h b/RTE/_Debug_SSE-300-U55/RTE_Components.h new file mode 100644 index 00000000..d8e1715e --- /dev/null +++ b/RTE/_Debug_SSE-300-U55/RTE_Components.h @@ -0,0 +1,50 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.15.0 + * + * Project: 'cmsis-executorch.Debug+SSE-300-U55' + * Target: 'Debug+SSE-300-U55' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "SSE300MPS3.h" + +/* ARM::CMSIS Driver:USART@1.0.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:UART&CMSIS@1.0.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ +#define RTE_CMSIS_Compiler_STDERR_UART_CMSIS /* CMSIS-Compiler STDERR: UART: CMSIS */ +/* ARM::CMSIS-Compiler:STDIN:UART&CMSIS@1.0.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ +#define RTE_CMSIS_Compiler_STDIN_UART_CMSIS /* CMSIS-Compiler STDIN: UART: CMSIS */ +/* ARM::CMSIS-Compiler:STDOUT:UART&CMSIS@1.0.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ +#define RTE_CMSIS_Compiler_STDOUT_UART_CMSIS /* CMSIS-Compiler STDOUT: UART: CMSIS */ +/* ARM::Device:Native Driver:SysCounter@1.1.0 */ +#define RTE_SYSCOUNTER 1 +/* ARM::Device:Native Driver:Timeout@1.0.0 */ +#define RTE_TIMEOUT 1 +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U55@2.0.0 */ +#define RTE_ETHOS_U_CORE_DRIVER +/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized dequantize@1.5.1 */ +#define RTE_ML_EXECUTORCH_OP_QUANTIZED_DEQUANTIZE /* ExecuTorch op_dequantize */ +/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized quantize@1.5.1 */ +#define RTE_ML_EXECUTORCH_OP_QUANTIZED_QUANTIZE /* ExecuTorch op_quantize */ +/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.5.1 */ +#define RTE_ML_EXECUTORCH_BACKEND_ETHOS_U /* ExecuTorch Ethos-U Backend (Cortex-M host) */ +/* PyTorch::Machine Learning:ExecuTorch:Kernel Registration@1.5.1 */ +#define RTE_ML_EXECUTORCH_KERNEL_REGISTRATION /* ExecuTorch Kernel Registration */ +/* PyTorch::Machine Learning:ExecuTorch:Kernel Utils@1.5.1 */ +#define RTE_ML_EXECUTORCH_KERNEL_UTILS /* ExecuTorch Kernel Utils */ +/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.5.1 */ +#define RTE_ML_EXECUTORCH_RUNTIME /* ExecuTorch Runtime */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h b/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h index 83d53110..0eacdd5e 100644 --- a/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h +++ b/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.14.1+p38-gf512b381 + * Generated by: csolution version 2.15.1+p3-gf46d68bf * * Project: 'cmsis-executorch.Debug+SSE-320-U85' * Target: 'Debug+SSE-320-U85' @@ -9,8 +9,9 @@ #ifndef PRE_INCLUDE_GLOBAL_H #define PRE_INCLUDE_GLOBAL_H -/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.26.2 */ -// enabling global pre includes +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@2.0.0 */ +// enabling global pre includes + #define ETHOSU85 #define ETHOSU_ARCH u85 /* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.5.1 */ #define EXECUTORCH_BUILD_ARM_BAREMETAL 1 diff --git a/RTE/_Debug_SSE-320-U85/RTE_Components.h b/RTE/_Debug_SSE-320-U85/RTE_Components.h index a80a87c2..3e0c1eea 100644 --- a/RTE/_Debug_SSE-320-U85/RTE_Components.h +++ b/RTE/_Debug_SSE-320-U85/RTE_Components.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.14.1+p38-gf512b381 + * Generated by: csolution version 2.15.1+p3-gf46d68bf * * Project: 'cmsis-executorch.Debug+SSE-320-U85' * Target: 'Debug+SSE-320-U85' @@ -15,20 +15,23 @@ */ #define CMSIS_device_header "SSE320.h" -/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +/* ARM::CMSIS Driver:USART@1.1.0 */ +#define RTE_USART0 1 + +/* ARM::CMSIS-Compiler:STDERR:UART&CMSIS@1.0.0 */ #define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ -#define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ -/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR_UART_CMSIS /* CMSIS-Compiler STDERR: UART: CMSIS */ +/* ARM::CMSIS-Compiler:STDIN:UART&CMSIS@1.0.0 */ #define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ -#define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ -/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN_UART_CMSIS /* CMSIS-Compiler STDIN: UART: CMSIS */ +/* ARM::CMSIS-Compiler:STDOUT:UART&CMSIS@1.0.0 */ #define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ -#define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +#define RTE_CMSIS_Compiler_STDOUT_UART_CMSIS /* CMSIS-Compiler STDOUT: UART: CMSIS */ /* ARM::Device:Native Driver:SysCounter@1.0.1 */ #define RTE_SYSCOUNTER 1 /* ARM::Device:Native Driver:Timeout@1.0.1 */ #define RTE_TIMEOUT 1 -/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.26.2 */ +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@2.0.0 */ #define RTE_ETHOS_U_CORE_DRIVER /* PyTorch::Machine Learning:ExecuTorch Operators:Quantized dequantize@1.5.1 */ #define RTE_ML_EXECUTORCH_OP_QUANTIZED_DEQUANTIZE /* ExecuTorch op_dequantize */ diff --git a/ai_layer/ai_layer.clayer.yml b/ai_layer/ai_layer.clayer.yml index 87928945..718f7758 100644 --- a/ai_layer/ai_layer.clayer.yml +++ b/ai_layer/ai_layer.clayer.yml @@ -1,9 +1,9 @@ -# Generated by create_ai_layer.py from cmsis-executorch.cbuild-mlops.yml -- do not edit. -# Re-run `python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml` after changing +# Generated by create_ai_layer.py from cmsis-executorch-u55.cbuild-mlops.yml -- do not edit. +# Re-run `python create_ai_layer.py cmsis-executorch-u55.cbuild-mlops.yml` after changing # model/model.py or the csolution's mlops: node. layer: type: AI - description: TinyCNN int8 image classifier for Ethos-U85 + description: TinyCNN int8 image classifier for Ethos-U55-128 packs: - pack: PyTorch::ExecuTorch@1.5.1 diff --git a/ai_layer/model_pte.c b/ai_layer/model_pte.c index 75bd1634..0a8cc913 100644 --- a/ai_layer/model_pte.c +++ b/ai_layer/model_pte.c @@ -3,220 +3,235 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0x24, 0x00, 0x00, 0x00, 0x45, 0x54, 0x31, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x18, 0x00, 0x00, 0x00, 0x14, 0x00, 0x10, 0x00, 0x0c, 0x00, 0x08, 0x00, 0x04, 0x00, 0x10, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, - 0x2c, 0x00, 0x00, 0x00, 0x4c, 0x1a, 0x00, 0x00, 0x4c, 0x1a, 0x00, 0x00, 0x60, 0xe2, 0xff, 0xff, + 0x2c, 0x00, 0x00, 0x00, 0x44, 0x1b, 0x00, 0x00, 0x44, 0x1b, 0x00, 0x00, 0xa0, 0xe0, 0xff, 0xff, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x90, 0xe0, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00, 0xe2, 0xdf, 0xff, 0xff, 0x04, 0x00, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xbb, 0xf7, 0xfe, 0xff, 0xff, 0x17, 0x40, 0x0d, 0x69, 0x2a, 0xd8, 0x70, 0x01, 0x00, 0x00, 0x93, + 0x1f, 0x1b, 0x1a, 0x28, 0x56, 0x05, 0x01, 0x00, 0x00, 0x7f, 0x57, 0xbc, 0x68, 0x2a, 0x31, 0xf9, + 0xfe, 0xff, 0xff, 0x73, 0xfa, 0x3b, 0x1a, 0x28, 0xcb, 0xa8, 0x00, 0x00, 0x00, 0xb9, 0x67, 0x86, + 0x06, 0x26, 0x2c, 0x9e, 0x00, 0x00, 0x00, 0xc9, 0x97, 0x1a, 0x69, 0x2a, 0x94, 0xeb, 0xfe, 0xff, + 0xff, 0x37, 0xeb, 0x04, 0x69, 0x2a, 0x8d, 0xf0, 0xfe, 0xff, 0xff, 0x49, 0x60, 0xbe, 0x68, 0x2a, + 0x4c, 0xc0, 0xfe, 0xff, 0xff, 0x59, 0xfa, 0xc7, 0x68, 0x2a, 0x15, 0xac, 0x00, 0x00, 0x00, 0x55, + 0xcf, 0x5c, 0x34, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x4f, 0x5c, 0x01, 0x0c, 0x00, 0x8e, 0xdc, 0xc8, 0xa5, 0x48, 0x69, 0x7e, 0x15, 0x00, 0xf0, 0x35, 0x0a, 0xc6, 0x72, 0x7b, 0x6a, 0x07, 0x0c, 0x00, 0x1e, 0x81, 0x15, 0x1f, 0xef, 0xaa, 0x19, 0xdb, 0xb8, 0x07, 0x73, 0x2a, 0xd3, 0x43, 0x44, 0x0f, 0x00, 0x10, 0xe8, 0x95, 0xed, 0x47, 0x51, @@ -235,31 +250,31 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0x00, 0xdd, 0x14, 0x7c, 0xaa, 0x0a, 0x7b, 0xc0, 0x20, 0x32, 0x52, 0x3b, 0x65, 0x48, 0x4a, 0x66, 0x15, 0x00, 0x52, 0x1a, 0x4c, 0x3f, 0x14, 0x82, 0xfd, 0xa9, 0x06, 0x01, 0x8e, 0x7c, 0x46, 0xc7, 0x8c, 0xc9, 0xe4, 0xaa, 0x00, 0x70, 0x26, 0x73, 0x4a, 0x83, 0x28, 0x4d, 0x1d, 0x1b, 0x75, 0xc7, - 0xb2, 0x6f, 0xc1, 0x6a, 0x76, 0x07, 0x00, 0xe9, 0xcd, 0x02, 0xed, 0xd0, 0x71, 0xb3, 0x1b, 0x00, - 0xb0, 0x5a, 0x08, 0xa8, 0x86, 0xb6, 0xfd, 0x5d, 0x2c, 0x10, 0x1a, 0x35, 0x94, 0x06, 0xc2, 0x53, - 0x01, 0x00, 0xab, 0x25, 0x8f, 0x9b, 0x7d, 0x36, 0x6a, 0x65, 0x00, 0xd0, 0x85, 0x3c, 0x78, 0xfc, - 0xf0, 0xa1, 0x6b, 0xab, 0x3a, 0x77, 0x4c, 0x5a, 0xe8, 0x92, 0x8f, 0x07, 0x00, 0xaa, 0xbc, 0x12, - 0x42, 0x36, 0x92, 0x84, 0x87, 0x80, 0xe0, 0xaa, 0x0a, 0xc2, 0x5a, 0x96, 0x78, 0x58, 0x11, 0xff, - 0x8d, 0xff, 0x6b, 0x87, 0x0b, 0xf7, 0x08, 0x04, 0xc6, 0xf6, 0x25, 0x62, 0x3a, 0xea, 0xe4, 0xa1, - 0x00, 0x80, 0x42, 0x78, 0x8a, 0x4c, 0x96, 0xad, 0xbb, 0xdf, 0xd0, 0x7b, 0x22, 0x6f, 0x23, 0xf2, - 0xe1, 0x09, 0x00, 0x7d, 0xed, 0x5a, 0xe3, 0xfd, 0x7f, 0xd5, 0x63, 0x00, 0xf0, 0x49, 0x49, 0x85, - 0xea, 0xd8, 0x8d, 0x51, 0x95, 0xd7, 0xbd, 0x69, 0x64, 0xc5, 0x0e, 0xa8, 0x05, 0x00, 0x07, 0x79, - 0x2d, 0x43, 0xdf, 0x2b, 0x4c, 0x67, 0x00, 0x90, 0xa0, 0x83, 0xde, 0xbf, 0x01, 0xd3, 0xad, 0x17, - 0xc6, 0xfd, 0x34, 0x16, 0xaa, 0x7b, 0xf4, 0x05, 0x00, 0xaa, 0x9d, 0xd9, 0x18, 0x7b, 0xb6, 0xc7, - 0xd2, 0x00, 0x80, 0xc9, 0xaa, 0xa3, 0x21, 0xd2, 0xc9, 0x4b, 0x78, 0x1c, 0x08, 0xff, 0x02, 0x4d, - 0xf0, 0x91, 0x04, 0x00, 0xb5, 0xb0, 0x23, 0x26, 0x9e, 0xaa, 0x86, 0x2b, 0x00, 0x10, 0xce, 0xba, - 0x65, 0x96, 0x17, 0x40, 0x29, 0x97, 0x13, 0xd0, 0x6f, 0xcb, 0xcc, 0x3a, 0x25, 0x08, 0x00, 0xed, - 0x5b, 0xc9, 0x66, 0xb9, 0x35, 0x70, 0xbe, 0x00, 0x80, 0x83, 0x9e, 0x30, 0xeb, 0x7c, 0x55, 0x37, - 0x9b, 0xc7, 0x9d, 0xb4, 0x99, 0x2a, 0xdd, 0xf7, 0x01, 0x00, 0x27, 0xed, 0x41, 0xa8, 0x7d, 0xec, - 0x7f, 0xe7, 0x00, 0xe0, 0xb6, 0xec, 0xda, 0x74, 0x8f, 0x2e, 0x90, 0x7a, 0x3c, 0xef, 0x34, 0xf0, - 0xe9, 0x46, 0x2e, 0x09, 0x00, 0x23, 0x03, 0x8d, 0x74, 0xaa, 0x56, 0xf5, 0xb5, 0x00, 0x80, 0x6a, - 0xab, 0xdd, 0xb5, 0x87, 0x82, 0xc8, 0x53, 0xb3, 0xf1, 0x77, 0x9f, 0x0e, 0x36, 0xd7, 0xf6, 0xff, - 0x93, 0xa1, 0xd8, 0xa5, 0xf5, 0x65, 0x30, 0x5c, 0xff, 0x0f, 0xc6, 0xdc, 0x43, 0x8a, 0x5c, 0xcc, - 0xfb, 0xf2, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0xff, 0xf2, 0x93, 0x61, 0x71, 0x7b, 0xd5, 0x32, - 0x49, 0xff, 0x5f, 0x0f, 0x78, 0xef, 0x82, 0xb5, 0x05, 0x3c, 0xfd, 0xff, 0x0f, 0x00, 0xf0, 0xff, - 0xff, 0x34, 0x99, 0xd9, 0xd6, 0xb9, 0xa2, 0xd5, 0xfc, 0xff, 0x15, 0xf0, 0xf8, 0x7e, 0x97, 0xdb, - 0xcf, 0x3f, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0x8e, 0x49, 0x81, 0x37, 0x6b, 0x06, 0xb7, 0x2e, - 0xff, 0x8f, 0xee, 0xd4, 0x41, 0x6e, 0x7c, 0xd7, 0x16, 0xf0, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, + 0x62, 0xab, 0xdd, 0xb5, 0x87, 0x02, 0xf0, 0x88, 0x3c, 0x35, 0x1b, 0x7f, 0xf7, 0xe9, 0x60, 0xff, + 0x3f, 0xd7, 0x36, 0x19, 0x8a, 0x5d, 0x5a, 0x5f, 0xf6, 0xff, 0x30, 0x5c, 0x60, 0xcc, 0x3d, 0xa4, + 0xc8, 0xc5, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0xbc, 0x2f, 0xf2, 0x93, 0x61, 0x71, 0x7b, 0xd5, + 0xff, 0x2f, 0x93, 0x54, 0x0f, 0x78, 0xef, 0x82, 0xb5, 0xf5, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, + 0xff, 0xc0, 0xd3, 0x4f, 0x93, 0x99, 0x6d, 0x9d, 0x2b, 0xff, 0xaf, 0xd5, 0x5c, 0x01, 0x8f, 0xef, + 0x77, 0xb9, 0xfd, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0xff, 0xfc, 0xe3, 0xb8, 0x6f, 0xc1, 0x6a, 0x76, + 0xf7, 0xff, 0xe9, 0xcd, 0x02, 0xed, 0xd0, 0x71, 0xb3, 0x1b, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, + 0xab, 0x85, 0x80, 0x6a, 0x68, 0xdb, 0xdf, 0xc5, 0x00, 0x20, 0x10, 0x1a, 0x35, 0x94, 0x06, 0xc2, + 0x53, 0xb1, 0x5a, 0xf2, 0xb8, 0xd9, 0x67, 0xa3, 0x56, 0x06, 0x00, 0x5d, 0xc8, 0x83, 0xc7, 0x0f, + 0x1f, 0xba, 0xb6, 0x00, 0xa0, 0x3a, 0x77, 0x4c, 0x5a, 0xe8, 0x92, 0x8f, 0xa7, 0xca, 0x2b, 0x21, + 0x64, 0x23, 0x49, 0x78, 0x08, 0x80, 0xae, 0xaa, 0x20, 0xac, 0x65, 0x89, 0x87, 0x15, 0x00, 0x14, + 0xff, 0x8d, 0xff, 0x6b, 0x87, 0x0b, 0xf7, 0x68, 0x6c, 0x5f, 0x22, 0xa6, 0xa3, 0x4e, 0x1e, 0x0a, + 0x00, 0x28, 0x84, 0xa7, 0xc8, 0x64, 0xd9, 0xba, 0xfb, 0x00, 0xd0, 0xd0, 0x7b, 0x22, 0x6f, 0x23, + 0xf2, 0xe1, 0xd9, 0xd7, 0xae, 0x35, 0xde, 0xff, 0x57, 0x3d, 0x06, 0x00, 0x9f, 0x94, 0x54, 0xa8, + 0x8e, 0xdd, 0x18, 0x55, 0x00, 0x90, 0xd7, 0xbd, 0x69, 0x64, 0xc5, 0x0e, 0xa8, 0x75, 0x90, 0xd7, + 0x32, 0xf4, 0xbd, 0xc2, 0x74, 0x06, 0x00, 0x09, 0x3a, 0xe8, 0xfd, 0x1b, 0x30, 0xdd, 0x7a, 0x00, + 0x10, 0xc6, 0xfd, 0x34, 0x16, 0xaa, 0x7b, 0xf4, 0xa5, 0xda, 0x99, 0x8d, 0xb1, 0x67, 0x7b, 0x2c, + 0x0d, 0x00, 0x98, 0xac, 0x3a, 0x1a, 0x22, 0x9d, 0xbc, 0x84, 0x00, 0x70, 0x1c, 0x08, 0xff, 0x02, + 0x4d, 0xf0, 0x91, 0x54, 0x0b, 0x3b, 0x62, 0xe2, 0xa9, 0x6a, 0xb8, 0x02, 0x00, 0xe1, 0xac, 0x5b, + 0x66, 0x79, 0x01, 0x94, 0x72, 0x00, 0x90, 0x13, 0xd0, 0x6f, 0xcb, 0xcc, 0x3a, 0x25, 0xd8, 0xbe, + 0x95, 0x6c, 0x96, 0x5b, 0x03, 0xe7, 0x0b, 0x00, 0x38, 0xe8, 0x09, 0xb3, 0xce, 0x57, 0x75, 0xb3, + 0x00, 0x90, 0xc7, 0x9d, 0xb4, 0x99, 0x2a, 0xdd, 0xf7, 0x71, 0xd2, 0x1e, 0x84, 0xda, 0xc7, 0xfe, + 0x77, 0x0e, 0x00, 0x6e, 0xcb, 0xae, 0x4d, 0xf7, 0xe8, 0x02, 0xa9, 0x00, 0x70, 0x3c, 0xef, 0x34, + 0xf0, 0xe9, 0x46, 0x2e, 0x39, 0x32, 0xd0, 0x48, 0xa7, 0x6a, 0x55, 0x5f, 0x0b, 0x00, 0xa8, 0x49, + 0x81, 0x37, 0x6b, 0x06, 0xb7, 0x2e, 0xf0, 0x8f, 0xee, 0xd4, 0x41, 0x6e, 0x7c, 0xd7, 0x16, 0xf0, 0xff, 0x32, 0xd2, 0x71, 0x4c, 0xef, 0xd4, 0xfd, 0xe3, 0xff, 0x3f, 0x1e, 0x00, 0xe6, 0xda, 0xc2, 0x07, 0x02, 0xf6, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0x6f, 0xb6, 0x0e, 0x32, 0xc4, 0xf3, 0x50, 0xb0, 0xf5, 0xff, 0x97, 0x43, 0x71, 0x6c, 0xa3, 0x84, 0xa3, 0xac, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, @@ -282,32 +297,32 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0xd8, 0x7e, 0xbb, 0xdc, 0x03, 0x0b, 0xa2, 0x00, 0x70, 0x72, 0xa8, 0x09, 0x81, 0xd0, 0xe4, 0x3b, 0x00, 0x00, 0xa5, 0x05, 0xf4, 0xca, 0xc0, 0x19, 0x02, 0x6f, 0x9d, 0x30, 0xd6, 0xa9, 0x86, 0x1d, 0x50, 0x54, 0x00, 0x90, 0x2e, 0x17, 0x2c, 0x12, 0x03, 0x49, 0xcf, 0x0f, 0x00, 0x45, 0x62, 0xfc, - 0x4a, 0x62, 0x5c, 0x67, 0x27, 0xdf, 0xe3, 0xc5, 0x69, 0x26, 0x77, 0x09, 0xc6, 0x00, 0x60, 0x61, - 0x8a, 0x46, 0xf8, 0xbd, 0x68, 0x59, 0x04, 0x00, 0x43, 0x0a, 0x7b, 0xed, 0x83, 0x31, 0xc0, 0x8c, - 0x2c, 0x24, 0x82, 0x9c, 0x67, 0x1b, 0x6e, 0x8a, 0x00, 0x30, 0x75, 0x86, 0xcd, 0xb0, 0x4a, 0x8d, - 0x62, 0x0c, 0x00, 0x44, 0xd3, 0x4d, 0x30, 0xd7, 0x28, 0x89, 0x38, 0x07, 0x7d, 0x5c, 0x79, 0x66, - 0x6d, 0xaa, 0x3c, 0x00, 0x70, 0x88, 0xbd, 0x86, 0x93, 0xe4, 0x27, 0xd0, 0x01, 0x00, 0xe8, 0x73, - 0xee, 0xc3, 0xd3, 0x50, 0x93, 0x33, 0xdd, 0xe6, 0x05, 0xcc, 0xc5, 0x56, 0x5f, 0xba, 0x00, 0x90, - 0x99, 0x90, 0x74, 0xb8, 0x72, 0xc5, 0xb8, 0x07, 0x00, 0xec, 0xad, 0x74, 0xb7, 0x50, 0xb0, 0x1c, - 0x86, 0xdd, 0x2e, 0x9a, 0x23, 0x8f, 0xca, 0x74, 0x31, 0x00, 0xa0, 0xd5, 0x3c, 0x2a, 0xd7, 0xef, - 0x5a, 0x0c, 0x0c, 0x00, 0x9a, 0x00, 0x74, 0xe7, 0xcc, 0x41, 0x5a, 0x8a, 0x43, 0x95, 0x60, 0x8f, - 0xcf, 0x60, 0x97, 0x80, 0x00, 0xd0, 0x68, 0x4c, 0xef, 0x40, 0xc3, 0x6e, 0x99, 0x06, 0x00, 0x35, - 0x5d, 0x8a, 0x2f, 0xbe, 0x38, 0x27, 0x7d, 0x26, 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0x60, 0x97, 0x80, 0x8d, 0xc6, 0xf4, 0x0e, 0x34, 0xec, 0x96, 0x69, 0x35, 0x00, 0xd0, 0xa5, + 0xf8, 0xe2, 0x8b, 0x73, 0xd2, 0x67, 0x02, 0x00, 0x8f, 0x4f, 0xc8, 0x7d, 0x0f, 0xf2, 0x19, 0xa0, + 0xb7, 0xab, 0xd9, 0x9b, 0x04, 0x73, 0x46, 0x3a, 0x00, 0x40, 0x00, 0x79, 0x53, 0x09, 0x26, 0x34, + 0x20, 0x03, 0x00, 0x62, 0x9d, 0x20, 0x6c, 0xda, 0xbf, 0x2b, 0x55, 0x77, 0xa2, 0x89, 0x2b, 0x7e, + 0x18, 0x5f, 0x3f, 0x00, 0x00, 0x71, 0xb5, 0xf5, 0x03, 0xab, 0xd4, 0x7d, 0x00, 0x00, 0xe5, 0xc0, + 0x2d, 0x01, 0x9b, 0x89, 0x91, 0xe7, 0x49, 0xeb, 0x2f, 0x02, 0x0f, 0x7b, 0x56, 0x81, 0x00, 0x90, + 0x99, 0xf5, 0xe4, 0x76, 0x63, 0x6d, 0x63, 0x00, 0x00, 0xd2, 0x6d, 0x45, 0xa6, 0x3f, 0xf2, 0x5e, + 0x1b, 0x21, 0x13, 0x42, 0xc3, 0xed, 0x5e, 0x7f, 0x48, 0x00, 0x70, 0xb0, 0x7a, 0x3d, 0x1e, 0xbb, + 0x56, 0xbd, 0x0f, 0x00, 0x7b, 0xe8, 0xb3, 0x8a, 0xb4, 0x69, 0x79, 0xaf, 0x04, 0x50, 0x05, 0x92, + 0xd4, 0x48, 0x20, 0xd0, 0x00, 0xf0, 0x67, 0x41, 0x2e, 0x1e, 0xc3, 0xbe, 0xad, 0x05, 0xf0, 0xdf, + 0xcb, 0x97, 0xf0, 0x47, 0x69, 0xb4, 0xb0, 0xff, 0x5f, 0xa6, 0x81, 0x47, 0xdb, 0xce, 0xbf, 0x2a, 0xfa, 0xff, 0x29, 0x30, 0x3a, 0x46, 0xa2, 0x0c, 0x3f, 0x66, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0x9d, 0xc3, 0xab, 0x94, 0x7d, 0x92, 0x18, 0x0f, 0xff, 0x5f, 0x9c, 0x03, 0x3f, 0xfb, 0xb9, 0xcf, 0x44, 0xf6, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0x7f, 0xf3, 0x74, 0xd7, 0xa8, 0xde, 0xe0, 0xd0, 0xfe, @@ -330,32 +345,32 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0xb9, 0x3a, 0xbb, 0x7a, 0x97, 0x53, 0xd8, 0xe2, 0xc3, 0x5c, 0x60, 0x60, 0x21, 0x3e, 0xeb, 0xb8, 0x00, 0x00, 0x95, 0xca, 0x53, 0x54, 0xb6, 0x61, 0x59, 0x09, 0x00, 0x48, 0x07, 0x8a, 0xa8, 0x42, 0x06, 0xd4, 0x73, 0x7d, 0x33, 0x15, 0x7f, 0x3d, 0x07, 0x30, 0x7a, 0x00, 0xe0, 0x64, 0xdb, 0x81, - 0x08, 0xf5, 0x84, 0x98, 0x0a, 0x00, 0x42, 0x8b, 0xce, 0x41, 0x35, 0xdf, 0xf8, 0x54, 0x17, 0x3e, - 0x91, 0xd5, 0xbf, 0xd5, 0x79, 0xc8, 0x00, 0x30, 0x0b, 0xe8, 0x27, 0xeb, 0xa3, 0xe8, 0x63, 0x0f, - 0x00, 0xf3, 0x5f, 0xab, 0x7b, 0x30, 0x9a, 0x77, 0xdc, 0xda, 0x1b, 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0x0f, 0x00, 0x00, 0xb3, 0x80, 0x7e, 0xb2, 0x3e, 0x8a, 0x3e, 0xf6, 0x00, + 0x30, 0xff, 0xb5, 0xba, 0x07, 0xa3, 0x79, 0xc7, 0x0d, 0x00, 0xda, 0x1b, 0xe1, 0x0f, 0x0e, 0xa8, + 0xdb, 0x64, 0x9a, 0x5b, 0xfd, 0xce, 0x3b, 0x32, 0x70, 0xea, 0x00, 0xa0, 0x8b, 0xf1, 0x00, 0x94, + 0x10, 0x32, 0x6b, 0x0e, 0x00, 0x4b, 0xbe, 0x9e, 0x09, 0xd1, 0x12, 0xe3, 0x10, 0x28, 0x88, 0xdd, + 0x2a, 0x23, 0x94, 0x32, 0x30, 0x00, 0xb0, 0x76, 0x8f, 0xf8, 0x98, 0x52, 0x8d, 0x0c, 0x03, 0x00, + 0x54, 0xc7, 0x43, 0x16, 0x1c, 0x59, 0xbf, 0xa4, 0xd2, 0x7d, 0x2a, 0x81, 0x34, 0x75, 0x06, 0x48, + 0x00, 0x20, 0xf4, 0xd8, 0x39, 0x1e, 0xc0, 0x74, 0x24, 0x0a, 0x00, 0xf8, 0x9e, 0x51, 0xb2, 0x7a, + 0x16, 0x56, 0xcd, 0xd7, 0x00, 0x4d, 0x7d, 0xeb, 0xa8, 0x79, 0x40, 0x00, 0x50, 0x26, 0x5c, 0x3e, + 0x64, 0x62, 0x31, 0xa7, 0x04, 0x00, 0x64, 0x7e, 0x57, 0x50, 0x31, 0x42, 0x8f, 0x68, 0xeb, 0x8f, + 0xbc, 0x81, 0x69, 0x47, 0xfd, 0x41, 0x00, 0x00, 0xa6, 0x5d, 0x8e, 0x17, 0x3f, 0x3f, 0x96, 0x0a, + 0x00, 0xd3, 0xca, 0x1f, 0x07, 0x7d, 0xb0, 0x11, 0xf6, 0x2f, 0xa5, 0x28, 0x47, 0x21, 0xf4, 0xcd, + 0x6d, 0x00, 0xd0, 0xaf, 0xaa, 0x4f, 0x09, 0xa5, 0x93, 0x70, 0x08, 0x00, 0x67, 0x40, 0xb7, 0x0e, + 0x03, 0x54, 0xce, 0x4f, 0xc9, 0xa6, 0x46, 0xa6, 0x95, 0x95, 0x9b, 0xc9, 0x00, 0xf0, 0xfc, 0xb9, + 0x46, 0x72, 0x13, 0xa9, 0x56, 0x0a, 0x00, 0x18, 0x66, 0x11, 0x2c, 0xc1, 0x70, 0x9f, 0x21, 0x46, + 0xc1, 0xc4, 0xe6, 0x0e, 0xce, 0x91, 0x67, 0x00, 0x70, 0x5c, 0x0d, 0x3e, 0x3c, 0x92, 0x74, 0xc0, + 0x0d, 0x00, 0x20, 0x5d, 0xb8, 0x8f, 0x06, 0x38, 0xf4, 0x81, 0x55, 0xe5, 0x19, 0x10, 0x44, 0xb1, + 0x62, 0xa5, 0x00, 0xc0, 0xe6, 0xeb, 0x00, 0xf8, 0x05, 0x53, 0x06, 0x01, 0x00, 0x54, 0x91, 0x17, + 0x2b, 0xe6, 0x5b, 0x00, 0x4f, 0x9c, 0xd1, 0x5d, 0xa3, 0x1e, 0x0c, 0xf5, 0x51, 0x00, 0x90, 0x4a, + 0x6c, 0xab, 0xe3, 0x8c, 0x47, 0xb6, 0xf4, 0xff, 0xac, 0x46, 0xbe, 0x27, 0xcf, 0x30, 0xef, 0x19, 0xff, 0x9f, 0x92, 0x69, 0xf4, 0x94, 0x17, 0x60, 0xc6, 0xfc, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0x0f, 0xc6, 0x85, 0x7c, 0x05, 0x0e, 0x98, 0x0a, 0xfd, 0xff, 0xa0, 0xf0, 0x2d, 0x52, 0x09, 0xd1, 0xa8, 0xb4, 0xff, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0xff, 0x2c, 0xc8, 0x3e, 0x5b, 0xb1, 0x29, 0x17, @@ -378,32 +393,32 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0xe4, 0x67, 0x86, 0xfd, 0xf3, 0x20, 0x76, 0x0a, 0x00, 0x11, 0x47, 0x84, 0xce, 0x9e, 0x1e, 0xdf, 0xd2, 0x8e, 0xdc, 0x6e, 0x55, 0x53, 0xdd, 0x0c, 0x1d, 0x00, 0xe0, 0x3d, 0x45, 0xac, 0x10, 0x87, 0xfd, 0xcd, 0x03, 0x00, 0x8e, 0x27, 0x8a, 0x06, 0xc0, 0x5d, 0xed, 0x91, 0xf6, 0xe9, 0xf1, 0x11, - 0x4e, 0x24, 0xf9, 0xd1, 0x80, 0xb1, 0x8f, 0x80, 0x18, 0x42, 0x8e, 0xb8, 0x51, 0x0c, 0x00, 0xdb, - 0xb3, 0xea, 0x53, 0x54, 0x46, 0x95, 0x16, 0x00, 0x10, 0xbc, 0x34, 0xc6, 0x3b, 0x9e, 0xc5, 0x71, - 0x4d, 0x74, 0xca, 0xa6, 0x17, 0x03, 0x53, 0xdf, 0x07, 0x00, 0x5c, 0x0b, 0x79, 0x3b, 0x1d, 0x00, - 0x29, 0x4a, 0x00, 0x00, 0x6d, 0xa2, 0x45, 0x10, 0xea, 0xab, 0x64, 0xed, 0x43, 0xc8, 0xd9, 0xbf, - 0x0e, 0x50, 0x05, 0x0b, 0x00, 0x48, 0xdb, 0xe5, 0x2d, 0x32, 0xe4, 0x80, 0x07, 0x00, 0x40, 0x7f, - 0xc9, 0xc5, 0xab, 0xe8, 0x0a, 0xe6, 0x68, 0xba, 0xf3, 0xe1, 0x5d, 0x5e, 0x99, 0xef, 0x03, 0x00, - 0xc3, 0x50, 0xb1, 0xcc, 0xd9, 0xd4, 0x74, 0xa7, 0x00, 0x20, 0xbf, 0xbd, 0xda, 0x0d, 0x3a, 0x93, - 0x4f, 0xaf, 0x77, 0x99, 0xcb, 0x69, 0x43, 0x47, 0xe8, 0x0e, 0x00, 0xe9, 0x56, 0x0b, 0x28, 0x3b, - 0x32, 0xb1, 0x06, 0x00, 0x10, 0xe5, 0x90, 0xcc, 0xda, 0xf2, 0xe6, 0x14, 0x83, 0xe7, 0xd3, 0x06, - 0xda, 0xf9, 0x0e, 0xf5, 0x25, 0x00, 0x7f, 0x30, 0xb7, 0xb4, 0xa5, 0xc5, 0x8c, 0xd0, 0x00, 0x40, - 0x8c, 0x32, 0x1a, 0x48, 0xa2, 0xee, 0x3e, 0x91, 0x3f, 0xd5, 0xb7, 0xc0, 0x92, 0x14, 0xdf, 0x01, - 0x00, 0xc0, 0xc2, 0xf4, 0x00, 0x99, 0x90, 0x35, 0x10, 0x00, 0x30, 0x78, 0xdd, 0x12, 0x86, 0x89, - 0xfe, 0x8c, 0xe8, 0xaa, 0xa2, 0x99, 0xae, 0x66, 0x7a, 0x4e, 0x0e, 0x00, 0xbb, 0x31, 0xcb, 0x88, - 0x97, 0x1b, 0x20, 0x93, 0x00, 0x80, 0x18, 0x4b, 0x5e, 0x11, 0x45, 0x4d, 0xe4, 0x92, 0x27, 0xef, - 0x9a, 0x7e, 0x3b, 0xaf, 0x1c, 0x00, 0x00, 0x75, 0x54, 0x61, 0x35, 0x60, 0x7e, 0x70, 0x48, 0x00, - 0x70, 0x16, 0xe0, 0x47, 0xe2, 0x33, 0x6c, 0xd6, 0x9f, 0x36, 0x94, 0xba, 0x71, 0x8b, 0x0f, 0x10, - 0x06, 0x00, 0x62, 0xe1, 0x02, 0xc2, 0x06, 0x3f, 0x11, 0x50, 0x00, 0xe0, 0xd3, 0x20, 0xf8, 0x04, - 0xfe, 0x16, 0x52, 0x5a, 0x67, 0xcf, 0xa3, 0xc1, 0x95, 0xcf, 0xa0, 0x07, 0x00, 0xa1, 0x3c, 0x4d, - 0xd2, 0x11, 0x7e, 0xb2, 0xbd, 0x00, 0x90, 0xba, 0xaf, 0xab, 0xd0, 0xb2, 0x78, 0x39, 0x52, 0x79, - 0x8a, 0x2d, 0x7c, 0x83, 0xa0, 0x12, 0xf3, 0xff, 0x3d, 0x73, 0x21, 0x2d, 0x9b, 0x92, 0xd6, 0xad, - 0xff, 0xef, 0x56, 0x17, 0xe9, 0xb7, 0x94, 0xe7, 0x6d, 0xf2, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, - 0xff, 0xb6, 0xe6, 0x19, 0xec, 0x1e, 0xf3, 0xe8, 0x09, 0xff, 0xff, 0x57, 0x38, 0x42, 0xa2, 0xfe, - 0xba, 0x24, 0xf2, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0x1f, 0x21, 0x84, 0x2d, 0xa0, 0x68, 0x1a, 0x46, - 0xf1, 0xff, 0xa3, 0xd2, 0x84, 0x67, 0x12, 0xe4, 0x8f, 0xab, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, - 0xc3, 0x96, 0x85, 0xa8, 0x3e, 0x9c, 0xb3, 0x07, 0xff, 0x2f, 0x98, 0x90, 0xbe, 0xa7, 0x7a, 0xe9, - 0x7c, 0xf7, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0xff, 0x26, 0x20, 0x03, 0x7a, 0xbd, 0x33, 0x72, + 0x4e, 0x24, 0xf9, 0xd1, 0x00, 0xb0, 0x8f, 0x80, 0x18, 0x42, 0xae, 0xab, 0xd0, 0x02, 0xf0, 0x8b, + 0x97, 0x23, 0x95, 0xa7, 0xd8, 0xc2, 0x37, 0xff, 0x8f, 0xa0, 0x12, 0xd3, 0x33, 0x17, 0xd2, 0xb2, + 0xf9, 0xff, 0x92, 0xd6, 0xad, 0x6e, 0x75, 0x91, 0x7e, 0x4b, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, + 0x79, 0xde, 0x26, 0xb6, 0xe6, 0x19, 0xec, 0x1e, 0xff, 0x3f, 0x8f, 0x9e, 0xf0, 0x57, 0x38, 0x42, + 0xa2, 0xfe, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0xba, 0x24, 0x12, 0x21, 0x84, 0x2d, 0xa0, 0xf8, + 0xff, 0xa6, 0x61, 0x14, 0xa3, 0xd2, 0x84, 0x67, 0x12, 0xff, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, + 0x4f, 0xfe, 0xb8, 0x3a, 0x6c, 0x89, 0xb8, 0x51, 0xfc, 0xff, 0xdb, 0xb3, 0xea, 0x53, 0x54, 0x46, + 0x95, 0x16, 0xff, 0xff, 0x8f, 0x01, 0x00, 0x00, 0xc1, 0x4b, 0x63, 0xbc, 0xe3, 0x59, 0x1c, 0xd7, + 0x00, 0x40, 0x74, 0xca, 0xa6, 0x17, 0x03, 0x53, 0xdf, 0xc7, 0xb5, 0x90, 0xb7, 0xd3, 0x01, 0x90, + 0xa2, 0x04, 0x00, 0xd0, 0x26, 0x5a, 0x04, 0xa1, 0xbe, 0x4a, 0xd6, 0x00, 0xe0, 0x43, 0xc8, 0xd9, + 0xbf, 0x0e, 0x50, 0x05, 0x8b, 0xb4, 0x5d, 0xde, 0x22, 0x43, 0x0e, 0x78, 0x00, 0x00, 0xf4, 0x97, + 0x5c, 0xbc, 0x8a, 0xae, 0x60, 0x8e, 0x00, 0x60, 0xba, 0xf3, 0xe1, 0x5d, 0x5e, 0x99, 0xef, 0x33, + 0x0c, 0x15, 0xcb, 0x9c, 0x4d, 0x4d, 0x77, 0x0a, 0x00, 0xf2, 0xdb, 0xab, 0xdd, 0xa0, 0x33, 0xf9, + 0xf4, 0x00, 0xa0, 0x77, 0x99, 0xcb, 0x69, 0x43, 0x47, 0xe8, 0x9e, 0x6e, 0xb5, 0x80, 0xb2, 0x23, + 0x13, 0x6b, 0x00, 0x00, 0x51, 0x0e, 0xc9, 0xac, 0x2d, 0x6f, 0x4e, 0x31, 0x20, 0x80, 0xe7, 0xd3, + 0x06, 0xda, 0xf9, 0x0e, 0xf5, 0xf5, 0x07, 0x73, 0x4b, 0x5b, 0x5a, 0xcc, 0x08, 0x0d, 0x00, 0xc4, + 0x28, 0xa3, 0x81, 0x24, 0xea, 0xee, 0x13, 0x00, 0x90, 0x3f, 0xd5, 0xb7, 0xc0, 0x92, 0x14, 0xdf, + 0x01, 0x2c, 0x4c, 0x0f, 0x90, 0x09, 0x59, 0x03, 0x01, 0x00, 0x83, 0xd7, 0x2d, 0x61, 0x98, 0xe8, + 0xcf, 0x88, 0x00, 0xe0, 0xaa, 0xa2, 0x99, 0xae, 0x66, 0x7a, 0x4e, 0xbe, 0x1b, 0xb3, 0x8c, 0x78, + 0xb9, 0x01, 0x32, 0x09, 0x00, 0x88, 0xb1, 0xe4, 0x15, 0x51, 0xd4, 0x44, 0x2e, 0x00, 0x90, 0x27, + 0xef, 0x9a, 0x7e, 0x3b, 0xaf, 0x1c, 0x50, 0x47, 0x15, 0x56, 0x03, 0xe6, 0x07, 0x87, 0x04, 0x00, + 0x67, 0x01, 0x7e, 0x24, 0x3e, 0xc3, 0x66, 0xfd, 0x00, 0x90, 0x36, 0x94, 0xba, 0x71, 0x8b, 0x0f, + 0x10, 0x26, 0x16, 0x2e, 0x20, 0x6c, 0xf0, 0x13, 0x01, 0x05, 0x00, 0x3e, 0x0d, 0x82, 0x4f, 0xe0, + 0x6f, 0x21, 0xa5, 0x00, 0x50, 0x67, 0xcf, 0xa3, 0xc1, 0x95, 0xcf, 0xa0, 0x17, 0xca, 0xd3, 0x24, + 0x1d, 0xe1, 0x27, 0xdb, 0x0b, 0x00, 0xa9, 0xfb, 0x85, 0xa8, 0x3e, 0x9c, 0xb3, 0x07, 0xf0, 0x2f, + 0x98, 0x90, 0xbe, 0xa7, 0x7a, 0xe9, 0x7c, 0xf7, 0xff, 0x26, 0x20, 0x03, 0x7a, 0xbd, 0x33, 0x72, 0x7c, 0xff, 0xaf, 0x1e, 0x53, 0xc0, 0x69, 0xfd, 0xe9, 0x28, 0xf4, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0x3f, 0x10, 0xab, 0xd3, 0x97, 0xf2, 0xa7, 0x0b, 0xf0, 0xff, 0x66, 0x8a, 0x4a, 0xb8, 0xd9, 0xeb, 0xf9, 0x38, 0xff, 0xff, 0x0f, 0x00, 0xf0, 0xff, 0x49, 0x4f, 0x2e, 0x1a, 0x11, 0xd7, 0x28, 0x37, @@ -411,7 +426,7 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0xff, 0x84, 0x38, 0xff, 0xff, 0xff, 0x0f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x73, 0x63, 0x72, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x73, 0x69, 0x7a, 0x65, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xf0, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x69, 0x6e, 0x70, 0x75, 0x74, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, @@ -424,38 +439,51 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x76, 0x65, 0x6c, 0x61, 0x5f, 0x65, 0x6e, 0x64, 0x5f, 0x73, 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0x67, 0x73, 0x00, 0x00, 0x00, 0xa8, 0xfb, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, - 0x1a, 0x00, 0x00, 0x00, 0x54, 0x4f, 0x53, 0x41, 0x2d, 0x31, 0x2e, 0x30, 0x2b, 0x49, 0x4e, 0x54, - 0x2b, 0x69, 0x6e, 0x74, 0x31, 0x36, 0x2b, 0x69, 0x6e, 0x74, 0x34, 0x2b, 0x63, 0x66, 0x00, 0x00, + 0x1b, 0x00, 0x00, 0x00, 0x54, 0x4f, 0x53, 0x41, 0x2d, 0x31, 0x2e, 0x30, 0x2b, 0x49, 0x4e, 0x54, + 0x2b, 0x69, 0x6e, 0x74, 0x31, 0x36, 0x2b, 0x69, 0x6e, 0x74, 0x34, 0x2b, 0x75, 0x35, 0x35, 0x00, 0x09, 0x00, 0x00, 0x00, 0x74, 0x6f, 0x73, 0x61, 0x5f, 0x73, 0x70, 0x65, 0x63, 0x00, 0x00, 0x00, 0xc8, 0xfc, 0xff, 0xff, 0x0d, 0x00, 0x00, 0x00, 0x45, 0x74, 0x68, 0x6f, 0x73, 0x55, 0x42, 0x61, 0x63, 0x6b, 0x65, 0x6e, 0x64, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x4c, 0x00, 0x00, 0x00, @@ -494,7 +522,7 @@ __attribute__((aligned(16))) const unsigned char model_pte[] = { 0x00, 0x00, 0x00, 0x02, 0x32, 0xfe, 0xff, 0xff, 0x80, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0, 0xfe, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x4a, 0xfe, 0xff, 0xff, 0x4d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0xff, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x04, 0x62, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x40, 0x31, 0xeb, 0x59, 0x3f, + 0x00, 0x00, 0x00, 0x04, 0x62, 0xfe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x60, 0x31, 0xeb, 0x59, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x24, 0xff, 0xff, 0xff, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x02, 0xff, 0xff, 0xff, 0x10, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x92, 0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, diff --git a/board/Corstone-300/Board-U55.clayer.yml b/board/Corstone-300/Board-U55.clayer.yml new file mode 100644 index 00000000..0575a776 --- /dev/null +++ b/board/Corstone-300/Board-U55.clayer.yml @@ -0,0 +1,59 @@ +layer: + type: Board + description: Base configuration of SSE-300 FVP with Ethos U55 + for-board: ARM::V2M-MPS3-SSE-300-FVP + for-device: ARM::SSE-300-MPS3 + + connections: + - connect: Corstone-300-U55 + provides: + - CMSIS_USART + - CMSIS_VIO + - STDIN + - STDOUT + - STDERR + - Heap: 98304 + + define: + - CMSIS_target_header: \"Corstone-300.h\" + - ETHOSU_MACS: 128 + - CORSTONE300_FVP + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0-0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + + components: + - component: CMSIS:CORE + + - component: CMSIS Driver:USART + - component: CMSIS Driver:VIO:Virtual + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS + + - component: Device:Definition + - component: Device:Startup&C Startup + + - component: Device:Native Driver:SysCounter + - component: Device:Native Driver:SysTimer + - component: Device:Native Driver:Timeout + - component: Device:Native Driver:UART + + - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + + groups: + - group: Board + files: + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c + + linker: + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/board/Corstone-300/Board-U65.clayer.yml b/board/Corstone-300/Board-U65.clayer.yml new file mode 100644 index 00000000..edbd5a51 --- /dev/null +++ b/board/Corstone-300/Board-U65.clayer.yml @@ -0,0 +1,59 @@ +layer: + type: Board + description: Base configuration of SSE-300 FVP with Ethos U65 + for-board: ARM::V2M-MPS3-SSE-300-FVP + for-device: ARM::SSE-300-MPS3 + + connections: + - connect: Corstone-300-U65 + provides: + - CMSIS_USART + - CMSIS_VIO + - STDIN + - STDOUT + - STDERR + - Heap: 98304 + + define: + - CMSIS_target_header: \"Corstone-300.h\" + - ETHOSU_MACS: 256 + - CORSTONE300_FVP + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0-0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + + components: + - component: CMSIS:CORE + + - component: CMSIS Driver:USART + - component: CMSIS Driver:VIO:Virtual + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS + + - component: Device:Definition + - component: Device:Startup&C Startup + + - component: Device:Native Driver:SysCounter + - component: Device:Native Driver:SysTimer + - component: Device:Native Driver:Timeout + - component: Device:Native Driver:UART + + - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U65 + + groups: + - group: Board + files: + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c + + linker: + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/board/Corstone-300/Board.clayer.yml b/board/Corstone-300/Board.clayer.yml new file mode 100644 index 00000000..643c1a0b --- /dev/null +++ b/board/Corstone-300/Board.clayer.yml @@ -0,0 +1,52 @@ +layer: + type: Board + description: Base configuration of SSE-300 FVP + for-board: ARM::V2M-MPS3-SSE-300-FVP + for-device: ARM::SSE-300-MPS3 + + connections: + - connect: Corstone-300 + provides: + - CMSIS_USART + - CMSIS_VIO + - STDIN + - STDOUT + - STDERR + - Heap: 98304 + + define: + - CMSIS_target_header: \"Corstone-300.h\" + - CORSTONE300_FVP + + packs: + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + + components: + - component: CMSIS:CORE + + - component: CMSIS Driver:USART + - component: CMSIS Driver:VIO:Virtual + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS + + - component: Device:Definition + - component: Device:Startup&C Startup + + - component: Device:Native Driver:SysCounter + - component: Device:Native Driver:SysTimer + - component: Device:Native Driver:Timeout + - component: Device:Native Driver:UART + + groups: + - group: Board + files: + - file: main.c + - file: main.h + + linker: + - regions: RTE/Device/SSE-300-MPS3/regions_SSE-300.h diff --git a/board/Corstone-300/Corstone-300.h b/board/Corstone-300/Corstone-300.h new file mode 100644 index 00000000..4abb85d3 --- /dev/null +++ b/board/Corstone-300/Corstone-300.h @@ -0,0 +1,37 @@ +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef CORSTONE_300_H_ +#define CORSTONE_300_H_ + +#include "Driver_USART.h" + +// CMSIS Driver instances of Board peripherals +#define CMSIS_DRIVER_USART 0 // CMSIS Driver USART instance number + +// Retarget stdio to CMSIS UART +#define RETARGET_STDIO_UART 0 + +// CMSIS Drivers +extern ARM_DRIVER_USART Driver_USART0; /* Serial */ + +#ifdef CMSIS_shield_header +#include CMSIS_shield_header +#endif + +#endif /* CORSTONE_300_H_ */ diff --git a/board/Corstone-300/README.md b/board/Corstone-300/README.md new file mode 100644 index 00000000..5cb1c757 --- /dev/null +++ b/board/Corstone-300/README.md @@ -0,0 +1,40 @@ +# Board: Arm V2M-MPS3-SSE-300-FVP + +## Board Layer for Corstone-300 FVP + +This layer works for: + +```yml + board: ARM::V2M-MPS3-SSE-300-FVP + device: ARM::SSE-300-MPS3 +``` + +### System Configuration + +| System Component | Setting +|:------------------------|:---------------------------------- +| Heap | 96 kB (configured in linker file) +| Stack (MSP) | 32 kB (configured in linker file) + +### STDIO mapping + +**STDIO** is routed to terminal via **UART0** peripheral + +### CMSIS-Driver mapping + +| CMSIS-Driver | Peripheral | Connection +|:-----------------------|:-----------|:---------------------- +| Driver_USART0 | UART0 | STDIN, STDOUT, STDERR +| CMSIS-Driver VIO | VIO | CMSIS_VIO + +### CMSIS-Driver Virtual I/O mapping + +VIO driver interfaces with the `arm_vio.py` Python stub implementation which +stores and loads signal values. + +### FVP Configuration File + +| File | Description +|:-------------------|:------------- +| fvp_config_u65.txt | Corstone-300 FVP with an Ethos-U65-256 +| fvp_config_u55.txt | Corstone-300 FVP with an Ethos-U55-128 diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h b/board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h new file mode 100644 index 00000000..d6a30a31 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 1 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..192648e0 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h b/board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h new file mode 100644 index 00000000..bce0ba24 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..bce0ba24 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h b/board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h new file mode 100644 index 00000000..aeeca61f --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..aeeca61f --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h b/board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h new file mode 100644 index 00000000..3cdc2aea --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 1 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..323d2176 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src new file mode 100644 index 00000000..6faef068 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif +} + +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + + ER_ROM1 __ROM1_BASE __ROM1_SIZE { + *(+RO +XO) + } + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + ; Ethos-U arena (AXI1, DDR4_1; U65 only) + ; *.o (*ethos_arena) ; Dedicated_Sram_384KB + + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + ; Ethos-U model: command stream and constants (AXI0, SRAM_VM0) + ; *.o (ethos_model) ; Sram_Only + + ; Ethos-U arena cache (AXI0, SRAM_VM0; U65 only) + ; *.o (*ethos_cache) ; Dedicated_Sram_384KB + + ; Ethos-U arena (AXI0, SRAM_VM0) + *.o (*ethos_arena) ; Sram_Only / Shared_Sram + + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + ; Ethos-U model: command stream and constants (AXI1, DDR4_3) + *.o (ethos_model) ; Shared_Sram / Dedicated_Sram_384KB + + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src new file mode 100644 index 00000000..545300e9 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/clang_linker_script.ld.src @@ -0,0 +1,386 @@ +/* + * SPDX-License-Identifier: BSD-3-Clause + * + * Copyright © 2019 Keith Packard + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED + * OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx!w) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx!w) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx!w) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx!w) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (w!rx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (w!rx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (w!rx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (w!rx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +ENTRY(Reset_Handler) + +PHDRS +{ + boot PT_LOAD; + text PT_LOAD; + ram PT_LOAD; + ram_init PT_LOAD; + tls PT_TLS; +} + +SECTIONS +{ + .init : { + KEEP (*(.vectors)) + + /* Disable by default + * + * *.init.enter contains a vector table provided by picolibc, + * whereas CMSIS already provides a vector table via .vectors + */ + /* + KEEP (*(.text.init.enter)) + KEEP (*(.data.init.enter)) + */ + + KEEP (*(SORT_BY_NAME(.init) SORT_BY_NAME(.init.*))) + } >ROM0 AT>ROM0 :boot + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .veneers : + { + . = ALIGN(32); + KEEP(*(.gnu.sgstubs)) + } > ROM0 AT>ROM0 :boot +#endif + + .text : { + + /* code */ + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.* .opd .opd.*) + *(.gnu.linkonce.t.*) + KEEP (*(.fini .fini.*)) + __text_end = .; + + PROVIDE (__etext = __text_end); + PROVIDE (_etext = __text_end); + PROVIDE (etext = __text_end); + + /* read-only data */ + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + *(.data.rel.ro .data.rel.ro.*) + *(.got .got.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + /* lists of constructors and destructors */ + PROVIDE_HIDDEN ( __bothinit_array_start = . ); + PROVIDE_HIDDEN ( __preinit_array_start = . ); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN ( __preinit_array_end = . ); + + PROVIDE_HIDDEN ( __init_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array .ctors)) + PROVIDE_HIDDEN ( __init_array_end = . ); + PROVIDE_HIDDEN ( __bothinit_array_end = . ); + + PROVIDE_HIDDEN ( __fini_array_start = . ); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array .dtors)) + PROVIDE_HIDDEN ( __fini_array_end = . ); + + } >ROM1 AT>ROM1 :text + + .toc : { + *(.toc .toc.*) + } >ROM1 AT>ROM1 :text + + /* additional sections when compiling with C++ exception support */ + + .except_ordered : { + *(.gcc_except_table *.gcc_except_table.*) + KEEP (*(.eh_frame .eh_frame.*)) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >ROM1 AT>ROM1 :text + + .except_unordered : { + . = ALIGN(8); + + PROVIDE(__exidx_start = .); + *(.ARM.exidx*) + PROVIDE(__exidx_end = .); + } >ROM1 AT>ROM1 :text + + + /* + * Data values which are preserved across reset + */ + .preserve (NOLOAD) : { + PROVIDE(__preserve_start__ = .); + KEEP(*(SORT_BY_NAME(.preserve.*))) + KEEP(*(.preserve)) + PROVIDE(__preserve_end__ = .); + } >RAM0 AT>RAM0 :ram + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + + /* Need to pre-align so that the symbols come after padding */ + . = ALIGN(8); + + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + } >RAM0 AT>ROM1 :ram_init + PROVIDE(__data_start = ADDR(.data)); + PROVIDE(__data_source = LOADADDR(.data)); + + /* Thread local initialized data. This gets + * space allocated as it is expected to be placed + * in ram to be used as a template for TLS data blocks + * allocated at runtime. We're slightly abusing that + * by placing the data in flash where it will be copied + * into the allocate ram addresses by the existing + * data initialization code in crt0 + */ + .tdata : { + *(.tdata .tdata.* .gnu.linkonce.td.*) + PROVIDE(__data_end = .); + PROVIDE(__tdata_end = .); + } >RAM0 AT>ROM1 :tls :ram_init + PROVIDE( __tls_base = ADDR(.tdata)); + PROVIDE( __tdata_start = ADDR(.tdata)); + PROVIDE( __tdata_source = LOADADDR(.tdata) ); + PROVIDE( __tdata_source_end = LOADADDR(.tdata) + SIZEOF(.tdata) ); + PROVIDE( __data_source_end = __tdata_source_end ); + PROVIDE( __tdata_size = SIZEOF(.tdata) ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata),ALIGNOF(.tbss)) ); + + PROVIDE( __edata = __data_end ); + PROVIDE( _edata = __data_end ); + PROVIDE( edata = __data_end ); + PROVIDE( __data_size = __data_end - __data_start ); + PROVIDE( __data_source_size = __data_source_end - __data_source ); + + .tbss (NOLOAD) : { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + *(.tcommon) + PROVIDE( __tls_end = . ); + PROVIDE( __tbss_end = . ); + } >RAM0 AT>RAM0 :tls :ram + PROVIDE( __bss_start = ADDR(.tbss)); + PROVIDE( __tbss_start = ADDR(.tbss)); + PROVIDE( __tbss_offset = ADDR(.tbss) - ADDR(.tdata) ); + PROVIDE( __tbss_size = SIZEOF(.tbss) ); + PROVIDE( __tls_size = __tls_end - __tls_base ); + PROVIDE( __tls_align = MAX(ALIGNOF(.tdata), ALIGNOF(.tbss)) ); + PROVIDE( __arm32_tls_tcb_offset = MAX(8, __tls_align) ); + PROVIDE( __arm64_tls_tcb_offset = MAX(16, __tls_align) ); + + /* + * The linker special cases .tbss segments which are + * identified as segments which are not loaded and are + * thread_local. + * + * For these segments, the linker does not advance 'dot' + * across them. We actually need memory allocated for tbss, + * so we create a special segment here just to make room + */ + /* + .tbss_space (NOLOAD) : { + . = ADDR(.tbss); + . = . + SIZEOF(.tbss); + } >RAM0 AT>RAM0 :ram + */ + + .bss (NOLOAD) : { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + + /* Align the end of this section, so next can start on aligned address */ + . = ALIGN(8); + __bss_end = .; + } >RAM0 AT>RAM0 :ram + PROVIDE( __non_tls_bss_start = ADDR(.bss) ); + PROVIDE( __bss_size = __bss_end - __bss_start ); + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : { + __noinit_start__ = .; + *(.noinit) + *(.noinit.*) + + /* Align the end of this section, so next (heap) can start on aligned address */ + . = ALIGN(8); + __noinit_end__ = .; + } >RAM0 AT>RAM0 :ram + + PROVIDE( __end = . ); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + /* Make the rest of memory available for heap storage */ + PROVIDE (__heap_start = __end); +#ifdef __HEAP_SIZE + PROVIDE (__heap_end = __heap_start + __HEAP_SIZE); + PROVIDE (__heap_size = __HEAP_SIZE); +#else + PROVIDE (__heap_end = __stack - __STACK_SIZE); + PROVIDE (__heap_size = __heap_end - __heap_start); +#endif + .heap (NOLOAD) : { + . += __heap_size; + } >RAM0 :ram + + /* Define a stack region to make sure it fits in memory */ + PROVIDE(__stack = ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE); + PROVIDE(__stack_limit = __stack - __STACK_SIZE); + .stack (__stack_limit) (NOLOAD) : { + . += __STACK_SIZE; + } >RAM0 :ram + +#if __STACKSEAL_SIZE > 0 + PROVIDE(__stack_seal = __stack); + .stackseal (__stack) (NOLOAD) : + { + . += __STACKSEAL_SIZE; + } >RAM0 :ram +#endif + + /* Throw away C++ exception handling information */ + + /* + + /DISCARD/ : { + *(.note .note.*) + *(.eh_frame .eh_frame.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx*) + } + + */ + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .gnu.build.attributes : { *(.gnu.build.attributes .gnu.build.attributes.*) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } +} +/* + * Check that sections that are copied from flash to RAM have matching + * padding, so that a single memcpy() of __data_size copies the correct bytes. + */ +ASSERT( __data_size == __data_source_size, + "ERROR: .data/.tdata flash size does not match RAM size"); diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 00000000..0e9746a7 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + +#endif /* __DEVICE_CFG_H__ */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 new file mode 100644 index 00000000..0e9746a7 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + +#endif /* __DEVICE_CFG_H__ */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src new file mode 100644 index 00000000..43e86484 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/gcc_linker_script.ld.src @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE ( 8 ) +#else +#define __STACKSEAL_SIZE ( 0 ) +#endif + +/* ---------------------------------------------------------------------------- + Memory definition + *----------------------------------------------------------------------------*/ +MEMORY +{ + ROM0 (rx) : ORIGIN = __ROM0_BASE, LENGTH = __ROM0_SIZE +#if __ROM1_SIZE > 0 + ROM1 (rx) : ORIGIN = __ROM1_BASE, LENGTH = __ROM1_SIZE +#endif +#if __ROM2_SIZE > 0 + ROM2 (rx) : ORIGIN = __ROM2_BASE, LENGTH = __ROM2_SIZE +#endif +#if __ROM3_SIZE > 0 + ROM3 (rx) : ORIGIN = __ROM3_BASE, LENGTH = __ROM3_SIZE +#endif + + RAM0 (rwx) : ORIGIN = __RAM0_BASE, LENGTH = __RAM0_SIZE +#if __RAM1_SIZE > 0 + RAM1 (rwx) : ORIGIN = __RAM1_BASE, LENGTH = __RAM1_SIZE +#endif +#if __RAM2_SIZE > 0 + RAM2 (rwx) : ORIGIN = __RAM2_BASE, LENGTH = __RAM2_SIZE +#endif +#if __RAM3_SIZE > 0 + RAM3 (rwx) : ORIGIN = __RAM3_BASE, LENGTH = __RAM3_SIZE +#endif +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext (deprecated) + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __noinit_start + * __noinit_end + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .boot : + { + KEEP(*(.vectors)) + } > ROM0 + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + .gnu.sgstubs : + { + . = ALIGN(32); + } > ROM0 +#endif + + .text : + { + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ROM1 + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > ROM1 + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ROM1 + __exidx_end = .; + + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + LONG (LOADADDR(.data)) + LONG (ADDR(.data)) + LONG (SIZEOF(.data) / 4) + + LONG (LOADADDR(.init_buf)) + LONG (ADDR(.init_buf)) + LONG (SIZEOF(.init_buf) / 4) + + /* Add each additional data section here */ +/* + LONG (LOADADDR(.data2)) + LONG (ADDR(.data2)) + LONG (SIZEOF(.data2) / 4) +*/ + __copy_table_end__ = .; + } > ROM1 + + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + +/* .bss initialization to zero is already done during C Run-Time Startup. + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss) / 4) +*/ + + /* Add each additional bss section here */ +/* + LONG (ADDR(.bss2)) + LONG (SIZEOF(.bss2) / 4) +*/ + __zero_table_end__ = .; + } > ROM1 + + /* + * This __etext variable is kept for backward compatibility with older, + * ASM based startup files. + */ + PROVIDE(__etext = LOADADDR(.data)); + + .data : ALIGN(4) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM0 AT > ROM1 + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table above to assure proper + * initialization during startup. + */ +/* + .data2 : ALIGN(4) + { + . = ALIGN(4); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(4); + __data2_end__ = .; + + } > RAM1 AT > ROM1 +*/ + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM0 AT > RAM0 + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table above to assure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(4); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(4); + __bss2_end__ = .; + } > RAM1 AT > RAM1 +*/ + + /* This section contains data that is not initialized during load, + or during the application's initialization sequence. */ + .noinit (NOLOAD) : + { + . = ALIGN(4); + __noinit_start = .; + *(.noinit) + *(.noinit.*) + . = ALIGN(4); + __noinit_end = .; + } > RAM0 + + /* Ethos-U buffers in external DRAM */ + .ethos_ram0 (NOLOAD) : + { + . = ALIGN(32); + /* *(*ethos_cache) */ /* Uncomment when Ethos-U cache resides in DRAM */ + /* *(*ethos_arena) */ /* Uncomment when Ethos-U arena resides in DRAM */ + } > RAM0 + + .heap (NOLOAD) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM0 + + .stack (ORIGIN(RAM0) + LENGTH(RAM0) - __STACK_SIZE - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM0 + PROVIDE(__stack = __StackTop); + +#if __STACKSEAL_SIZE > 0 + .stackseal (ORIGIN(RAM0) + LENGTH(RAM0) - __STACKSEAL_SIZE) (NOLOAD) : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM0 +#endif + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Non-initialized buffers in fast access RAM */ + .cache (NOLOAD): + { + . = ALIGN(32); + /* *(*ethos_cache) */ /* Uncomment when Ethos-U cache resides in SRAM (fast RAM) */ + *(*ethos_arena) /* Uncomment when Ethos-U arena resides in SRAM */ + } > RAM1 + + /* Initialized buffers in fast access RAM */ + /* Entry must exist in .copy.table */ + .init_buf : + { + . = ALIGN(16); + /* *(*ethos_model) */ /* Uncomment when Ethos-U command stream + constants reside in SRAM */ + /* Add other initialized objects that go into RAM1 */ + . = ALIGN(4); + } > RAM1 AT > ROM1 + + .rom2 : + { + *(*ethos_model) /* Comment out when Ethos-U command stream + constants reside in SRAM */ + } > ROM2 + + .rom3 : + { + /* Add objects that go into ROM3 */ + } > ROM3 +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src new file mode 100644 index 00000000..1a3548b4 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/iar_linker_script.icf.src @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2023-2024 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +define memory mem with size = 4G; + +#if __ROM0_SIZE > 0 + define region ROM0_region = mem:[from __ROM0_BASE to (__ROM0_BASE+__ROM0_SIZE-1)]; +#else + define region ROM0_region = []; +#endif + +#if __ROM1_SIZE > 0 + define region ROM1_region = mem:[from __ROM1_BASE to (__ROM1_BASE+__ROM1_SIZE-1)]; +#else + define region ROM1_region = []; +#endif + +#if __ROM2_SIZE > 0 + define region ROM2_region = mem:[from __ROM2_BASE to (__ROM2_BASE+__ROM2_SIZE-1)]; +#else + define region ROM2_region = []; +#endif + +#if __ROM3_SIZE > 0 + define region ROM3_region = mem:[from __ROM3_BASE to (__ROM3_BASE+__ROM3_SIZE-1)]; +#else + define region ROM3_region = []; +#endif + +#if __RAM0_SIZE > 0 + define region RAM0_region = mem:[from __RAM0_BASE to (__RAM0_BASE+__RAM0_SIZE-1)]; +#else + define region RAM0_region = []; +#endif + +#if __RAM1_SIZE > 0 + define region RAM1_region = mem:[from __RAM1_BASE to (__RAM1_BASE+__RAM1_SIZE-1)]; +#else + define region RAM1_region = []; +#endif + +#if __RAM2_SIZE > 0 + define region RAM2_region = mem:[from __RAM2_BASE to (__RAM2_BASE+__RAM2_SIZE-1)]; +#else + define region RAM2_region = []; +#endif + +#if __RAM3_SIZE > 0 + define region RAM3_region = mem:[from __RAM3_BASE to (__RAM3_BASE+__RAM3_SIZE-1)]; +#else + define region RAM3_region = []; +#endif + +do not initialize { section .noinit }; +initialize by copy { readwrite }; +if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) +{ + // Required in a multi-threaded application + initialize by copy with packing = none { section __DLIB_PERTHREAD }; +} + +place at address mem:__ROM0_BASE { readonly section .intvec }; + +if (!isempty(ROM1_region)) +{ + place in ROM1_region { readonly }; +} + +if (!isempty(RAM0_region)) +{ + define block CSTACK with alignment = 8, size = __STACK_SIZE { }; + define block PROC_STACK with alignment = 8, size = 0 { }; + define block HEAP with alignment = 8, size = __HEAP_SIZE { }; + place in RAM0_region { readwrite, block PROC_STACK, block HEAP }; + place at end of RAM0_region { block CSTACK }; +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h b/board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h new file mode 100644 index 00000000..c55a6aa1 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/regions_SSE-300.h @@ -0,0 +1,115 @@ +#ifndef REGIONS_SSE_300_H +#define REGIONS_SSE_300_H + +#include "sse300_memmap_s.h" +#include "sse300_memmap_ns.h" + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// ROM Configuration +// ======================= +// __ROM0 +// Base address +// Defines base address of memory region. +// Contains Startup and Vector Table +// Default: ITCM_S_BASE +#define __ROM0_BASE ITCM_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: ITCM_S_SIZE +#define __ROM0_SIZE ITCM_S_SIZE +// + +// __ROM1 +// Base address +// Defines base address of memory region. +// Default: FPGA_SRAM_S_BASE +#define __ROM1_BASE FPGA_SRAM_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: FPGA_SRAM_S_SIZE +#define __ROM1_SIZE FPGA_SRAM_S_SIZE +// + +// __ROM2 +// Base address +// Defines base address of memory region. +// Default: DDR4_3_S_BASE +#define __ROM2_BASE DDR4_3_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: DDR4_3_S_SIZE +#define __ROM2_SIZE DDR4_3_S_SIZE +// + +// __ROM3 +// Base address +// Defines base address of memory region. +// Default: QSPI_FLASH_S_BASE +#define __ROM3_BASE QSPI_FLASH_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: QSPI_FLASH_S_SIZE +#define __ROM3_SIZE QSPI_FLASH_S_SIZE +// + +// + +// RAM Configuration +// ======================= +// __RAM0 +// Base address +// Defines base address of memory region. +// Default: DDR4_1_S_BASE +#define __RAM0_BASE DDR4_1_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: DDR4_1_S_SIZE +#define __RAM0_SIZE DDR4_1_S_SIZE +// + +// __RAM1 +// Base address +// Defines base address of memory region. +// Default: SRAM_VM0_S_BASE +#define __RAM1_BASE SRAM_VM0_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: SRAM_VM0_S_SIZE +#define __RAM1_SIZE SRAM_VM0_S_SIZE +// + +// __RAM2 +// Base address +// Defines base address of memory region. +// Default: SRAM_VM1_S_BASE +#define __RAM2_BASE SRAM_VM1_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: SRAM_VM1_S_SIZE +#define __RAM2_SIZE SRAM_VM1_S_SIZE +// + +// __RAM3 +// Base address +// Defines base address of memory region. +// Default: DTCM_S_BASE +#define __RAM3_BASE DTCM_S_BASE +// Region size [bytes] +// Defines size of memory region. +// Default: DTCM_S_SIZE +#define __RAM3_SIZE DTCM_S_SIZE +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00001000 +#define __HEAP_SIZE 0x00018000 +// + +#endif /* REGIONS_SSE_300_H */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h b/board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h new file mode 100644 index 00000000..811a1c68 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_ns.h @@ -0,0 +1,92 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#ifndef SSE300_MEMMAP_NS_H +#define SSE300_MEMMAP_NS_H + +/*============================================================================*/ +/* NON-SECURE MEMORY REGIONS */ +/*============================================================================*/ + +/*---------------------------------------------------------------------------*/ +/* Non-Secure Code Regions */ +/*---------------------------------------------------------------------------*/ + +/* ITCM - Non-Secure */ +#define ITCM_NS_BASE 0x00000000 +#define ITCM_NS_SIZE 0x00080000 /* 512KB */ +#define ITCM_NS_LIMIT (ITCM_NS_BASE + ITCM_NS_SIZE - 1) + +/* FPGA SRAM - Non-Secure */ +#define FPGA_SRAM_NS_BASE 0x01000000 +#define FPGA_SRAM_NS_SIZE 0x00100000 /* 1MB */ +#define FPGA_SRAM_NS_LIMIT (FPGA_SRAM_NS_BASE + FPGA_SRAM_NS_SIZE - 1) + +/*---------------------------------------------------------------------------*/ +/* Non-Secure SRAM Regions */ +/*---------------------------------------------------------------------------*/ + +/* DTCM - Non-Secure */ +#define DTCM_NS_BASE 0x20000000 +#define DTCM_NS_SIZE 0x00080000 /* 512KB */ +#define DTCM_NS_LIMIT (DTCM_NS_BASE + DTCM_NS_SIZE - 1) + +/* SRAM VM0 - Non-Secure */ +#define SRAM_VM0_NS_BASE 0x21000000 +#define SRAM_VM0_NS_SIZE 0x00100000 /* 1MB */ +#define SRAM_VM0_NS_LIMIT (SRAM_VM0_NS_BASE + SRAM_VM0_NS_SIZE - 1) + +/* SRAM VM1 - Non-Secure */ +#define SRAM_VM1_NS_BASE 0x21100000 +#define SRAM_VM1_NS_SIZE 0x00100000 /* 1MB */ +#define SRAM_VM1_NS_LIMIT (SRAM_VM1_NS_BASE + SRAM_VM1_NS_SIZE - 1) + +/*---------------------------------------------------------------------------*/ +/* Non-Secure QSPI Flash Regions */ +/*---------------------------------------------------------------------------*/ + +/* QSPI Flash - Non-Secure */ +#define QSPI_FLASH_NS_BASE 0x28000000 +#define QSPI_FLASH_NS_SIZE 0x00800000 /* 8MB */ +#define QSPI_FLASH_NS_LIMIT (QSPI_FLASH_NS_BASE + QSPI_FLASH_NS_SIZE - 1) + +/*---------------------------------------------------------------------------*/ +/* Non-Secure DDR4 Regions */ +/*---------------------------------------------------------------------------*/ + +/* DDR4 Region 0 - Non-Secure */ +#define DDR4_0_NS_BASE 0x60000000 +#define DDR4_0_NS_SIZE 0x10000000 /* 256MB */ +#define DDR4_0_NS_LIMIT (DDR4_0_NS_BASE + DDR4_0_NS_SIZE - 1) + +/* DDR4 Region 2 - Non-Secure */ +#define DDR4_2_NS_BASE 0x80000000 +#define DDR4_2_NS_SIZE 0x10000000 /* 256MB */ +#define DDR4_2_NS_LIMIT (DDR4_2_NS_BASE + DDR4_2_NS_SIZE - 1) + +/* DDR4 Region 4 - Non-Secure */ +#define DDR4_4_NS_BASE 0xA0000000 +#define DDR4_4_NS_SIZE 0x10000000 /* 256MB */ +#define DDR4_4_NS_LIMIT (DDR4_4_NS_BASE + DDR4_4_NS_SIZE - 1) + +/* DDR4 Region 6 - Non-Secure */ +#define DDR4_6_NS_BASE 0xC0000000 +#define DDR4_6_NS_SIZE 0x10000000 /* 256MB */ +#define DDR4_6_NS_LIMIT (DDR4_6_NS_BASE + DDR4_6_NS_SIZE - 1) + +#endif /* SSE300_MEMMAP_NS_H */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h b/board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h new file mode 100644 index 00000000..3746461b --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/sse300_memmap_s.h @@ -0,0 +1,92 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#ifndef SSE300_MEMMAP_S_H +#define SSE300_MEMMAP_S_H + +/*============================================================================*/ +/* SECURE MEMORY REGIONS */ +/*============================================================================*/ + +/*---------------------------------------------------------------------------*/ +/* Secure Code Regions */ +/*---------------------------------------------------------------------------*/ + +/* ITCM - Secure (Startup) */ +#define ITCM_S_BASE 0x10000000 +#define ITCM_S_SIZE 0x00080000 /* 512KB */ +#define ITCM_S_LIMIT (ITCM_S_BASE + ITCM_S_SIZE - 1) + +/* FPGA SRAM - Secure */ +#define FPGA_SRAM_S_BASE 0x11000000 +#define FPGA_SRAM_S_SIZE 0x00100000 /* 1MB */ +#define FPGA_SRAM_S_LIMIT (FPGA_SRAM_S_BASE + FPGA_SRAM_S_SIZE - 1) + +/*---------------------------------------------------------------------------*/ +/* Secure SRAM Regions */ +/*---------------------------------------------------------------------------*/ + +/* DTCM - Secure */ +#define DTCM_S_BASE 0x30000000 +#define DTCM_S_SIZE 0x00080000 /* 512KB */ +#define DTCM_S_LIMIT (DTCM_S_BASE + DTCM_S_SIZE - 1) + +/* SRAM VM0 - Secure */ +#define SRAM_VM0_S_BASE 0x31000000 +#define SRAM_VM0_S_SIZE 0x00100000 /* 1MB */ +#define SRAM_VM0_S_LIMIT (SRAM_VM0_S_BASE + SRAM_VM0_S_SIZE - 1) + +/* SRAM VM1 - Secure */ +#define SRAM_VM1_S_BASE 0x31100000 +#define SRAM_VM1_S_SIZE 0x00100000 /* 1MB */ +#define SRAM_VM1_S_LIMIT (SRAM_VM1_S_BASE + SRAM_VM1_S_SIZE - 1) + +/*---------------------------------------------------------------------------*/ +/* Secure QSPI Flash Regions */ +/*---------------------------------------------------------------------------*/ + +/* QSPI Flash - Secure */ +#define QSPI_FLASH_S_BASE 0x38000000 +#define QSPI_FLASH_S_SIZE 0x00800000 /* 8MB */ +#define QSPI_FLASH_S_LIMIT (QSPI_FLASH_S_BASE + QSPI_FLASH_S_SIZE - 1) + +/*---------------------------------------------------------------------------*/ +/* Secure DDR4 Regions */ +/*---------------------------------------------------------------------------*/ + +/* DDR4 Region 1 - Secure */ +#define DDR4_1_S_BASE 0x70000000 +#define DDR4_1_S_SIZE 0x10000000 /* 256MB */ +#define DDR4_1_S_LIMIT (DDR4_1_S_BASE + DDR4_1_S_SIZE - 1) + +/* DDR4 Region 3 - Secure */ +#define DDR4_3_S_BASE 0x90000000 +#define DDR4_3_S_SIZE 0x10000000 /* 256MB */ +#define DDR4_3_S_LIMIT (DDR4_3_S_BASE + DDR4_3_S_SIZE - 1) + +/* DDR4 Region 5 - Secure */ +#define DDR4_5_S_BASE 0xB0000000 +#define DDR4_5_S_SIZE 0x10000000 /* 256MB */ +#define DDR4_5_S_LIMIT (DDR4_5_S_BASE + DDR4_5_S_SIZE - 1) + +/* DDR4 Region 7 - Secure */ +#define DDR4_7_S_BASE 0xD0000000 +#define DDR4_7_S_SIZE 0x10000000 /* 256MB */ +#define DDR4_7_S_LIMIT (DDR4_7_S_BASE + DDR4_7_S_SIZE - 1) + +#endif /* SSE300_MEMMAP_S_H */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 00000000..b29bff16 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) +#ifdef CORSTONE300_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +#ifdef CORSTONE300_FVP + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 00000000..b29bff16 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) +#ifdef CORSTONE300_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +#ifdef CORSTONE300_FVP + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 00000000..20b624e3 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 00000000..20b624e3 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/board/Corstone-300/ethos_setup.c b/board/Corstone-300/ethos_setup.c new file mode 100644 index 00000000..d4033b3a --- /dev/null +++ b/board/Corstone-300/ethos_setup.c @@ -0,0 +1,104 @@ +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "ethosu_driver.h" +#include "main.h" + +#if defined(ETHOSU65) || defined(ETHOSU85) +/* Define Ethos-U NPU cache buffer size */ +#ifndef ETHOS_CACHE_SIZE +#define ETHOS_CACHE_SIZE 0 +#endif + +/* Define Ethos-U cache buffer alignment */ +#ifndef ETHOS_CACHE_ALIGNMENT +#define ETHOS_CACHE_ALIGNMENT 32 +#endif + +/* Define Ethos-U NPU cache buffer attributes */ +#ifndef ETHOS_CACHE_ATTRIBUTES +#define ETHOS_CACHE_ATTRIBUTES __attribute__((section("ethos_cache"), aligned(ETHOS_CACHE_ALIGNMENT))) +#endif +#endif + +/* Define Ethos-U NPU security mode */ +#ifndef ETHOS_SECURE_ENABLE +#define ETHOS_SECURE_ENABLE 1 +#endif + +/* Define Ethos-U NPU privilege mode */ +#ifndef ETHOS_PRIVILEGE_ENABLE +#define ETHOS_PRIVILEGE_ENABLE 1 +#endif + +/* Ethos NPU driver instance. */ +static struct ethosu_driver EthosDriver; + +#if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) +/* Ethos-U NPU cache buffer */ +static uint8_t ethos_cache_buf[ETHOS_CACHE_SIZE] ETHOS_CACHE_ATTRIBUTES; +#endif + +/* + Ethos NPU interrupt handler. +*/ +void ETHOS_U55_Handler (void) { + ethosu_irq_handler(&EthosDriver); +} + +/* + Initialize the Ethos NPU driver. +*/ +void ethos_setup (void) { + void * const ethos_base_addr = (void *)ETHOS_U55_APB_BASE_S; + struct ethosu_hw_info hw_info; + int rval; + + /* Initialize Ethos-U NPU driver. */ + rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ + ethos_base_addr, /* Ethos-U base address */ + #if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) + ethos_cache_buf, /* Cache memory pointer */ + sizeof(ethos_cache_buf), /* Cache memory size */ + #else + 0, /* Cache memory pointer */ + 0, /* Cache memory size */ + #endif + ETHOS_SECURE_ENABLE, /* Secure enable */ + ETHOS_PRIVILEGE_ENABLE); /* Privileged mode */ + if (rval != 0) { + printf("Failed to initialize Arm Ethos-U driver\n"); + } + else { + NVIC_EnableIRQ(ETHOS_U55_IRQn); + + ethosu_get_hw_info(&EthosDriver, &hw_info); + + printf("Ethos-U version info:\n"); + printf("\tArch: v%u.%u.%u\n", hw_info.version.arch_major_rev, + hw_info.version.arch_minor_rev, + hw_info.version.arch_patch_rev); + printf("\tMACs/cc: %u\n", (uint32_t)(1 << hw_info.cfg.macs_per_cc)); + printf("\tCmd stream: v%u\n", hw_info.cfg.cmd_stream_version); + } +} diff --git a/board/Corstone-300/ethosu_dcache.c b/board/Corstone-300/ethosu_dcache.c new file mode 100644 index 00000000..015a9d1f --- /dev/null +++ b/board/Corstone-300/ethosu_dcache.c @@ -0,0 +1,78 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include + +#include "ethosu_driver.h" + +/** + \brief Cleans data-cache contents associated with buffers accessed by the NPU. + + Ensures that CPU writes to cacheable buffers are committed to memory before + the NPU starts accessing them. Non-cacheable buffers require no cache clean, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Flush data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // CleanDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} + +/** + \brief Invalidates data-cache contents associated with buffers accessed by the NPU. + + Ensures that subsequent CPU reads observe data written by the NPU. Dirty + cache lines may be cleaned before invalidation to preserve pending CPU + writes. For non-cacheable buffers, no cache invalidation is required, + but the function ensures that all preceding memory accesses have completed + before it returns. + + \param[in] base_addr Array of buffer base addresses. + \param[in] base_addr_size Array containing the size, in bytes, of each buffer. + \param[in] num_base_addr Number of entries in the address and size arrays. +*/ +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + /* Base address must be cache line aligned (32 bytes) */ + // ... + return; + } + + /* Invalidate data-cache for current buffer */ + // ... + // 32-bit system must cast base_addr to uint32_t* to avoid sign expansion + // InvalidateDCache((uint32_t *)(uint32_t)base_addr[i], base_addr_size[i]); + } +} diff --git a/board/Corstone-300/ethosu_os_rtos2.c b/board/Corstone-300/ethosu_os_rtos2.c new file mode 100644 index 00000000..79d75d63 --- /dev/null +++ b/board/Corstone-300/ethosu_os_rtos2.c @@ -0,0 +1,147 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" + +#ifdef RTE_CMSIS_RTOS2 + +#include "ethosu_driver.h" +#include "cmsis_os2.h" + +/* Maximum number of Ethos-U instances. */ +/* Used as maximum semaphore count in ethosu_semaphore_create. */ +#ifndef ETHOSU_MAX_INSTANCES +#define ETHOSU_MAX_INSTANCES 2 +#endif + +/** + \brief Create a mutex object. + \return Pointer to a mutex object. +*/ +void *ethosu_mutex_create(void) { + osMutexId_t mutex_id = osMutexNew(NULL); + return (void *) mutex_id; +} + +/** + \brief Destroy a mutex object. + \param[in] mutex mutex object. +*/ +void ethosu_mutex_destroy(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osMutexDelete(mutex_id); +} + +/** + \brief Lock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_lock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexAcquire(mutex_id, osWaitForever); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Unlock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_unlock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexRelease(mutex_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Create a semaphore object. + \return Pointer to a semaphore object. +*/ +void *ethosu_semaphore_create(void) { + osSemaphoreId_t sem_id; + + sem_id = osSemaphoreNew(ETHOSU_MAX_INSTANCES, 0U, NULL); + return (void *) sem_id; +} + +/** + \brief Destroy a semaphore object. + \param[in] sem semaphore object. +*/ +void ethosu_semaphore_destroy(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osSemaphoreDelete(sem_id); +} + +/** + \brief Take a semaphore object with timeout. + \param[in] sem semaphore object. + \param[in] timeout timeout value in ticks. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_take(void *sem, uint64_t timeout) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreAcquire(sem_id, timeout); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Give a semaphore object. + \param[in] sem semaphore object. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_give(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreRelease(sem_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +#endif /* RTE_CMSIS_RTOS2 */ diff --git a/board/Corstone-300/fvp_config_u55.txt b/board/Corstone-300/fvp_config_u55.txt new file mode 100644 index 00000000..cecdf1b9 --- /dev/null +++ b/board/Corstone-300/fvp_config_u55.txt @@ -0,0 +1,16 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=128 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ diff --git a/board/Corstone-300/fvp_config_u65.txt b/board/Corstone-300/fvp_config_u65.txt new file mode 100644 index 00000000..b7d885c7 --- /dev/null +++ b/board/Corstone-300/fvp_config_u65.txt @@ -0,0 +1,16 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x100' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ diff --git a/board/Corstone-300/main.c b/board/Corstone-300/main.c new file mode 100644 index 00000000..e7c1dadc --- /dev/null +++ b/board/Corstone-300/main.c @@ -0,0 +1,43 @@ +/* + * Copyright 2024-2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "main.h" + +#ifdef RTE_CMSIS_RTOS2 +#include "cmsis_os2.h" +#endif + +int main (void) { + + /* Initialize STDIO */ + stdio_init(); + + #if defined(ETHOSU_ARCH) + /* Initialize Ethos NPU */ + ethos_setup(); + #endif + + #ifdef RTE_CMSIS_RTOS2 + osKernelInitialize(); + #endif + + return (app_main()); +} diff --git a/board/Corstone-300/main.h b/board/Corstone-300/main.h new file mode 100644 index 00000000..2b576ad2 --- /dev/null +++ b/board/Corstone-300/main.h @@ -0,0 +1,38 @@ +/* + * Copyright 2020-2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef MAIN_H__ +#define MAIN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Prototypes */ +extern int app_main (void); +extern int stdio_init (void); + +#if defined(ETHOSU_ARCH) +extern void ethos_setup (void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/Corstone-320/Board-U85.clayer.yml b/board/Corstone-320/Board-U85.clayer.yml index 3ba21104..56c52dd1 100644 --- a/board/Corstone-320/Board-U85.clayer.yml +++ b/board/Corstone-320/Board-U85.clayer.yml @@ -1,18 +1,14 @@ -# Copyright 2026 Arm Limited and/or its affiliates. -# SPDX-License-Identifier: Apache-2.0 -# -# Corstone-320 (SSE-320) board bring-up for the Ethos-U85 NPU, trimmed to what -# a headless ExecuTorch inference runner needs: device startup, stdout over -# semihosting, and the Ethos-U driver. Audio/video vStreams and VIO are omitted. layer: type: Board - description: Corstone-320 board setup for headless Ethos-U85 inference + description: Base configuration of SSE-320 FVP with Ethos U85 for-board: ARM::SSE-320 for-device: ARM::SSE-320-FVP connections: - - connect: Corstone-320 + - connect: Corstone-320-U85 provides: + - CMSIS_USART + - CMSIS_VIO - STDIN - STDOUT - STDERR @@ -20,22 +16,24 @@ layer: define: - CMSIS_target_header: \"Corstone-320.h\" - - ETHOSU85 - - ARM_MODEL_USE_PMU_COUNTERS + - ETHOSU_MACS: 256 packs: - pack: ARM::CMSIS - - pack: ARM::CMSIS-Compiler@^2.1.0 - - pack: ARM::ethos-u-core-driver@^1.25.2 - - pack: ARM::SSE_320_BSP@1.0.0 + - pack: ARM::CMSIS-Compiler@^2.3.0 + - pack: ARM::CMSIS-Ethos-U@^1.0.0-0 + - pack: ARM::SSE_320_BSP@^2.0.0 components: - component: CMSIS:CORE + - component: CMSIS Driver:USART + - component: CMSIS Driver:VIO:Virtual + - component: CMSIS-Compiler:CORE - - component: CMSIS-Compiler:STDERR:Custom - - component: CMSIS-Compiler:STDIN:Custom - - component: CMSIS-Compiler:STDOUT:Custom + - component: CMSIS-Compiler:STDERR:UART&CMSIS + - component: CMSIS-Compiler:STDIN:UART&CMSIS + - component: CMSIS-Compiler:STDOUT:UART&CMSIS - component: Device:Definition - component: Device:Startup&C Startup @@ -43,16 +41,19 @@ layer: - component: Device:Native Driver:SysCounter - component: Device:Native Driver:SysTimer - component: Device:Native Driver:Timeout + - component: Device:Native Driver:UART - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U85 groups: - group: Board files: - - file: ./main.c - - file: ./main.h - - file: ./ethos_setup.c - - file: ./retarget_stdio.c + - file: main.c + - file: main.h + - file: ethos_setup.c + - file: ethosu_os_rtos2.c + - file: ethosu_dcache.c linker: + # The pack example's default regions are too small for the embedded model. - regions: ./regions_SSE-320.h diff --git a/board/Corstone-320/Corstone-320.h b/board/Corstone-320/Corstone-320.h index c8ca7638..3d70e524 100644 --- a/board/Corstone-320/Corstone-320.h +++ b/board/Corstone-320/Corstone-320.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,11 +14,18 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef CORSTONE_320_H_ #define CORSTONE_320_H_ +#include "Driver_USART.h" + +#define CMSIS_DRIVER_USART 0 +#define RETARGET_STDIO_UART 0 + +extern ARM_DRIVER_USART Driver_USART0; + #ifdef CMSIS_shield_header #include CMSIS_shield_header #endif diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h b/board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h new file mode 100644 index 00000000..192648e0 --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..192648e0 --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stderr_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDERR to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDERR_CMSIS_UART_CONFIG_H_ +#define STDERR_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDERR Buffer Size +// UART STDERR buffer is used to store STDERR data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDERR_UART_BUFFER_SIZE +#define STDERR_UART_BUFFER_SIZE 0 +#endif + +// UART STDERR Buffer Section Name +// Specify the memory section name for UART STDERR buffer +// Default: .stderr_uart_buf +#ifndef STDERR_UART_BUFFER_SECTION +#define STDERR_UART_BUFFER_SECTION ".stderr_uart_buf" +#endif + +// UART STDERR Buffer Alignment +// Define the STDERR buffer alignment in bytes +// Default: 32 +#ifndef STDERR_UART_BUFFER_ALIGNMENT +#define STDERR_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDERR_CR_LF +#define STDERR_CR_LF 0 +#endif + +#endif /* STDERR_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h b/board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h new file mode 100644 index 00000000..bce0ba24 --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..bce0ba24 --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stdin_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDIN to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIN_CMSIS_UART_CONFIG_H_ +#define STDIN_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDIN Buffer Size +// UART STDIN buffer is used to store STDIN data received via UART +// Default: 64 +#ifndef STDIN_UART_BUFFER_SIZE +#define STDIN_UART_BUFFER_SIZE 64 +#endif + +// UART STDIN Buffer Section Name +// Specify the memory section name for UART STDIN buffer +// Default: .stdin_uart_buf +#ifndef STDIN_UART_BUFFER_SECTION +#define STDIN_UART_BUFFER_SECTION ".stdin_uart_buf" +#endif + +// UART STDIN Buffer Alignment +// Define the STDIN buffer alignment in bytes +// Default: 32 +#ifndef STDIN_UART_BUFFER_ALIGNMENT +#define STDIN_UART_BUFFER_ALIGNMENT 32 +#endif + +// Echo Input Characters +// If enabled, received characters are echoed to STDOUT +// Default: 0 +#ifndef STDIN_ECHO +#define STDIN_ECHO 0 +#endif + +#endif /* STDIN_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h b/board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h new file mode 100644 index 00000000..aeeca61f --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..aeeca61f --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stdio_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,52 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: STDIO to CMSIS Driver USART Retarget Configuration + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDIO_CMSIS_UART_CONFIG_H_ +#define STDIO_CMSIS_UART_CONFIG_H_ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#else +#define RETARGET_STDIO_UART 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Connect to hardware via Driver_USART# +// Select driver control block for hardware interface +// Default: 0 +#ifndef STDIO_UART_DRIVER +#define STDIO_UART_DRIVER RETARGET_STDIO_UART +#endif + +// UART baudrate +// Specifies the baudrate for UART communication +// Common values: 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 +// Default: 115200 +#ifndef STDIO_UART_BAUDRATE +#define STDIO_UART_BAUDRATE 115200 +#endif + +#endif /* STDIO_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h b/board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h new file mode 100644 index 00000000..323d2176 --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 b/board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 new file mode 100644 index 00000000..323d2176 --- /dev/null +++ b/board/Corstone-320/RTE/CMSIS-Compiler/stdout_cmsis_uart_config.h.base@1.0.0 @@ -0,0 +1,59 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * -------------------------------------------------------------------------- + * + * Purpose: Configure STDOUT to CMSIS-Driver USART retarget implementation + * Revision: V1.0.0 + * + * --------------------------------------------------------------------------*/ + +#ifndef STDOUT_CMSIS_UART_CONFIG_H_ +#define STDOUT_CMSIS_UART_CONFIG_H_ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// UART STDOUT Buffer Size +// UART STDOUT buffer is used to store STDOUT data before sending it via UART +// Default: 0 (unbuffered) +#ifndef STDOUT_UART_BUFFER_SIZE +#define STDOUT_UART_BUFFER_SIZE 0 +#endif + +// UART STDOUT Buffer Section Name +// Specify the memory section name for UART STDOUT buffer +// Default: .stdout_uart_buf +#ifndef STDOUT_UART_BUFFER_SECTION +#define STDOUT_UART_BUFFER_SECTION ".stdout_uart_buf" +#endif + +// UART STDOUT Buffer Alignment +// Define the buffer alignment in bytes +// Default: 32 +#ifndef STDOUT_UART_BUFFER_ALIGNMENT +#define STDOUT_UART_BUFFER_ALIGNMENT 32 +#endif + +// Convert LF to CRLF +// If enabled, LF characters are preceded by CR characters on output +// Default: 0 +#ifndef STDOUT_CR_LF +#define STDOUT_CR_LF 0 +#endif + +#endif /* STDOUT_CMSIS_UART_CONFIG_H_ */ diff --git a/board/Corstone-320/ethos_setup.c b/board/Corstone-320/ethos_setup.c index ca26dfac..2c6f12b2 100644 --- a/board/Corstone-320/ethos_setup.c +++ b/board/Corstone-320/ethos_setup.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2025 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2025-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include @@ -26,18 +26,18 @@ #if defined(ETHOSU65) || defined(ETHOSU85) /* Define Ethos-U NPU cache buffer size */ -#ifndef ETHOS_CACHE_BUF_SIZE -#define ETHOS_CACHE_BUF_SIZE 393216 +#ifndef ETHOS_CACHE_SIZE +#define ETHOS_CACHE_SIZE 0 #endif /* Define Ethos-U cache buffer alignment */ -#ifndef ETHOS_CACHE_BUF_ALIGNMENT -#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#ifndef ETHOS_CACHE_ALIGNMENT +#define ETHOS_CACHE_ALIGNMENT 32 #endif /* Define Ethos-U NPU cache buffer attributes */ -#ifndef ETHOS_CACHE_BUF_ATTRIBUTES -#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#ifndef ETHOS_CACHE_ATTRIBUTES +#define ETHOS_CACHE_ATTRIBUTES __attribute__((section("ethos_cache"), aligned(ETHOS_CACHE_ALIGNMENT))) #endif #endif @@ -54,14 +54,14 @@ /* Ethos NPU driver instance. */ static struct ethosu_driver EthosDriver; -#if defined(ETHOSU65) || defined(ETHOSU85) -static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) +static uint8_t ethos_cache_buf[ETHOS_CACHE_SIZE] ETHOS_CACHE_ATTRIBUTES; #endif /* Ethos NPU interrupt handler. */ -void NPU0_Handler(void) { +void NPU0_Handler (void) { ethosu_irq_handler(&EthosDriver); } @@ -76,9 +76,9 @@ void ethos_setup (void) { /* Initialize Ethos-U NPU driver. */ rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ ethos_base_addr, /* Ethos-U base address */ - #if defined(ETHOSU65) || defined(ETHOSU85) - ethos_cache, /* Cache memory pointer */ - sizeof(ethos_cache), /* Cache memory size */ + #if (defined(ETHOSU65) || defined(ETHOSU85)) && (ETHOS_CACHE_SIZE > 0) + ethos_cache_buf, /* Cache memory pointer */ + sizeof(ethos_cache_buf), /* Cache memory size */ #else 0, /* Cache memory pointer */ 0, /* Cache memory size */ diff --git a/board/Corstone-320/ethosu_dcache.c b/board/Corstone-320/ethosu_dcache.c new file mode 100644 index 00000000..fb17e4b8 --- /dev/null +++ b/board/Corstone-320/ethosu_dcache.c @@ -0,0 +1,26 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "ethosu_driver.h" + +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + (void)base_addr_size; + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + return; + } + } +} + +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) { + (void)base_addr_size; + for (int i = 0; i < num_base_addr; i++) { + if ((base_addr[i] & 0x1F) != 0) { + return; + } + } +} diff --git a/board/Corstone-320/ethosu_os_rtos2.c b/board/Corstone-320/ethosu_os_rtos2.c new file mode 100644 index 00000000..79d75d63 --- /dev/null +++ b/board/Corstone-320/ethosu_os_rtos2.c @@ -0,0 +1,147 @@ +/* + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "RTE_Components.h" + +#ifdef RTE_CMSIS_RTOS2 + +#include "ethosu_driver.h" +#include "cmsis_os2.h" + +/* Maximum number of Ethos-U instances. */ +/* Used as maximum semaphore count in ethosu_semaphore_create. */ +#ifndef ETHOSU_MAX_INSTANCES +#define ETHOSU_MAX_INSTANCES 2 +#endif + +/** + \brief Create a mutex object. + \return Pointer to a mutex object. +*/ +void *ethosu_mutex_create(void) { + osMutexId_t mutex_id = osMutexNew(NULL); + return (void *) mutex_id; +} + +/** + \brief Destroy a mutex object. + \param[in] mutex mutex object. +*/ +void ethosu_mutex_destroy(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osMutexDelete(mutex_id); +} + +/** + \brief Lock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_lock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexAcquire(mutex_id, osWaitForever); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Unlock a mutex. + \param[in] mutex mutex object. + \return 0 on success, else negative error codes +*/ +int ethosu_mutex_unlock(void *mutex) { + osMutexId_t mutex_id = (osMutexId_t) mutex; + osStatus_t status; + int rval; + + status = osMutexRelease(mutex_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Create a semaphore object. + \return Pointer to a semaphore object. +*/ +void *ethosu_semaphore_create(void) { + osSemaphoreId_t sem_id; + + sem_id = osSemaphoreNew(ETHOSU_MAX_INSTANCES, 0U, NULL); + return (void *) sem_id; +} + +/** + \brief Destroy a semaphore object. + \param[in] sem semaphore object. +*/ +void ethosu_semaphore_destroy(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osSemaphoreDelete(sem_id); +} + +/** + \brief Take a semaphore object with timeout. + \param[in] sem semaphore object. + \param[in] timeout timeout value in ticks. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_take(void *sem, uint64_t timeout) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreAcquire(sem_id, timeout); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +/** + \brief Give a semaphore object. + \param[in] sem semaphore object. + \return 0 on success, else negative error codes +*/ +int ethosu_semaphore_give(void *sem) { + osSemaphoreId_t sem_id = (osSemaphoreId_t) sem; + osStatus_t status; + int rval; + + status = osSemaphoreRelease(sem_id); + if (status == osOK) { + rval = 0; + } else { + rval = -1; + } + return rval; +} + +#endif /* RTE_CMSIS_RTOS2 */ diff --git a/board/Corstone-320/fvp_config.txt b/board/Corstone-320/fvp_config.txt index 7d357098..893382c1 100644 --- a/board/Corstone-320/fvp_config.txt +++ b/board/Corstone-320/fvp_config.txt @@ -29,7 +29,7 @@ mps4_board.telnetterminal5.start_telnet=0 # (bool , init-time) defa mps4_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) mps4_board.uart0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output # NOTE: without this the FVP block-buffers uart0 stdout when it is a - # pipe and output only appears when the FVP exits. This example's + # pipe and output only appears when the FVP exits. This template's # stdio goes through semihosting, so uart0 only matters for code # that writes to it directly. mps4_board.uart0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) diff --git a/board/Corstone-320/main.c b/board/Corstone-320/main.c index 3949a17f..e7c1dadc 100644 --- a/board/Corstone-320/main.c +++ b/board/Corstone-320/main.c @@ -1,5 +1,5 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved. +/* + * Copyright 2024-2026 Arm Limited and/or its affiliates. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #include "RTE_Components.h" #include CMSIS_device_header @@ -35,9 +35,9 @@ int main (void) { ethos_setup(); #endif -#ifdef RTE_CMSIS_RTOS2 + #ifdef RTE_CMSIS_RTOS2 osKernelInitialize(); -#endif + #endif return (app_main()); } diff --git a/board/Corstone-320/main.h b/board/Corstone-320/main.h index 6e2048ee..2b576ad2 100644 --- a/board/Corstone-320/main.h +++ b/board/Corstone-320/main.h @@ -1,6 +1,6 @@ -/*--------------------------------------------------------------------------- - * Copyright (c) 2020-2025 Arm Limited (or its affiliates). - * All rights reserved. +/* + * Copyright 2020-2026 Arm Limited and/or its affiliates. + * * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the License); you may @@ -14,7 +14,7 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - *---------------------------------------------------------------------------*/ + */ #ifndef MAIN_H__ #define MAIN_H__ diff --git a/board/Corstone-320/regions_SSE-320.h b/board/Corstone-320/regions_SSE-320.h index fa441955..137fd9e9 100644 --- a/board/Corstone-320/regions_SSE-320.h +++ b/board/Corstone-320/regions_SSE-320.h @@ -1,7 +1,7 @@ // Copyright 2026 Arm Limited and/or its affiliates. // SPDX-License-Identifier: Apache-2.0 // -// Memory regions of the Corstone-320 FVP for this example. Every region that +// Memory regions of the Corstone-320 FVP for this template. Every region that // differs from the SSE_320_BSP pack default says so in its comment. #ifndef REGIONS_SSE_320_H #define REGIONS_SSE_320_H diff --git a/cmsis-executorch-u55.csolution.yml b/cmsis-executorch-u55.csolution.yml new file mode 100644 index 00000000..73fc76de --- /dev/null +++ b/cmsis-executorch-u55.csolution.yml @@ -0,0 +1,66 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# ExecuTorch application template targeting an Ethos-U55 on the +# Corstone-300 (SSE-300) FVP. +# +# cbuild setup cmsis-executorch-u55.csolution.yml --active SSE-300-U55 +# python create_ai_layer.py cmsis-executorch-u55.cbuild-mlops.yml +# cbuild cmsis-executorch-u55.csolution.yml --active SSE-300-U55 +# +# See CMSIS-Toolbox MLOps information: +# https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information +# `cbuild setup` exports it for create_ai_layer.py to generate the AI layer. +solution: + created-for: CMSIS-Toolbox@2.15.0 + cdefault: + compiler: AC6 + + packs: + # The PyTorch::ExecuTorch pack version must match the ExecuTorch Python + # exporter in requirements.txt because its runtime consumes the generated .pte. + - pack: PyTorch::ExecuTorch@1.5.1 + - pack: ARM::Cortex_DFP + + target-types: + # Corstone-300 with an Ethos-U55-128 NPU, simulated on the Arm FVP. + - type: SSE-300-U55 + board: V2M-MPS3-SSE-300-FVP + device: SSE-300-MPS3 + variables: + - Board-Layer: $SolutionDir()$/board/Corstone-300/Board-U55.clayer.yml + - AI-Layer: $SolutionDir()$/ai_layer/ai_layer.clayer.yml + target-set: + - set: + images: + - project-context: cmsis-executorch.Debug + debugger: + name: Arm-FVP + # See: https://github.com/Arm-Examples/FVPs-on-Mac/tree/main/skills/fvp-debug-setup + # On macOS use .vscode/fvp.sh and copy launch.json.mac to launch.json. + model: FVP_Corstone_SSE-300_Ethos-U55 + config-file: board/Corstone-300/fvp_config_u55.txt + args: "--simlimit 60" + + build-types: + - type: Debug + debug: on + optimize: debug + + projects: + - project: ./cmsis-executorch.cproject.yml + + # Target and model settings consumed by create_ai_layer.py. + mlops: + description: TinyCNN int8 image classifier for Ethos-U55-128 + npu: + type: Ethos-U55 + macs: 128 + vela: + system: Ethos_U55_High_End_Embedded + memory: Shared_Sram + model: + clayer: $AI-Layer$ + name: TinyCNN + input-shape: 1x16x16x3 + calibration-samples: 2 diff --git a/cmsis-executorch.cproject.yml b/cmsis-executorch.cproject.yml index 62ac0773..0a61ec8e 100644 --- a/cmsis-executorch.cproject.yml +++ b/cmsis-executorch.cproject.yml @@ -14,6 +14,11 @@ project: - CPP: - -std=gnu++17 - -Wno-deprecated-declarations + - for-compiler: AC6 + CPP: + # ExecuTorch tests INFINITY while the selected bare-metal floating-point + # mode assumes finite values. + - -Wno-nan-infinity-disabled - for-compiler: GCC C: - -Wno-psabi diff --git a/cmsis-executorch.csolution.yml b/cmsis-executorch.csolution.yml index ba2d260b..2ea8c8a9 100644 --- a/cmsis-executorch.csolution.yml +++ b/cmsis-executorch.csolution.yml @@ -1,29 +1,26 @@ # Copyright 2026 Arm Limited and/or its affiliates. # SPDX-License-Identifier: Apache-2.0 # -# A minimal ExecuTorch-on-Ethos-U85 example for the Corstone-320 (SSE-320) FVP. +# A template for ExecuTorch applications, initially targeting an Ethos-U85 on +# the Corstone-320 (SSE-320) FVP. # Three steps build it: # # cbuild setup cmsis-executorch.csolution.yml --active SSE-320-U85 # python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml # cbuild cmsis-executorch.csolution.yml --active SSE-320-U85 # -# The `mlops:` node below makes `cbuild setup` emit the *.cbuild-mlops.yml; -# create_ai_layer.py reads the NPU and Vela settings from it, exports the model -# from PyTorch in the project's venv and writes the AI layer. +# See CMSIS-Toolbox MLOps information: +# https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information +# `cbuild setup` exports it for create_ai_layer.py to generate the AI layer. solution: created-for: CMSIS-Toolbox@2.15.0 cdefault: compiler: AC6 packs: - # Pinned exactly: the pack's C++ runtime and the Python exporter pinned in - # requirements.txt must be the same ExecuTorch version, or the .pte fails - # to load. `cbuild setup --packs` fetches it from the public index. + # The PyTorch::ExecuTorch pack version must match the ExecuTorch Python + # exporter in requirements.txt because its runtime consumes the generated .pte. - pack: PyTorch::ExecuTorch@1.5.1 - - pack: ARM::CMSIS - - pack: ARM::CMSIS-NN - - pack: ARM::CMSIS-Compiler - pack: ARM::Cortex_DFP target-types: @@ -40,11 +37,8 @@ solution: - project-context: cmsis-executorch.Debug debugger: name: Arm-FVP - # The model is its own GDB server (plugins/GDBServer.so, MDK FVP - # models 11.32.23+). On Windows and Linux the FVP from vcpkg runs - # as it is. On macOS, where Arm ships no FVP build, set this to - # ${workspaceFolder}/.vscode/fvp.sh, which runs the model in - # Docker, and copy .vscode/launch.json.mac to .vscode/launch.json. + # On macOS use .vscode/fvp.sh and copy launch.json.mac to launch.json. + # See: https://github.com/Arm-Examples/FVPs-on-Mac/tree/main/skills/fvp-debug-setup model: FVP_Corstone_SSE-320 config-file: board/Corstone-320/fvp_config.txt args: "--simlimit 60" @@ -57,19 +51,14 @@ solution: projects: - project: ./cmsis-executorch.cproject.yml - # MLOps information: exported to cmsis-executorch.cbuild-mlops.yml by - # `cbuild setup ... --active SSE-320-U85`. Retarget the NPU here and - # create_ai_layer.py picks it up on its next run. The simulator target comes - # from the Arm-FVP target-set, and the extra keys under model: are passed - # through to create_ai_layer.py. - # https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information + # Target and model settings consumed by create_ai_layer.py. mlops: description: TinyCNN int8 image classifier for Ethos-U85 npu: - type: Ethos-U85 # explicit: the SSE-320 device pack declares no NPU + type: Ethos-U85 # explicit: the SSE-320 device pack declares no NPU vela: system: Ethos_U85_SYS_DRAM_Mid # system-config from the Vela config - memory: Shared_Sram # memory-mode from the Vela config + memory: Shared_Sram # memory-mode from the Vela config model: clayer: $AI-Layer$ name: TinyCNN diff --git a/create_ai_layer.py b/create_ai_layer.py index e55cce24..5392de3b 100644 --- a/create_ai_layer.py +++ b/create_ai_layer.py @@ -146,7 +146,7 @@ def compile_spec(mlops: dict, mlops_dir: Path): npu = mlops.get("npu") if not npu: - sys.exit("the solution's mlops: node names no NPU; this example needs an Ethos-U") + sys.exit("the solution's mlops: node names no NPU; this template needs an Ethos-U") vela = mlops.get("vela", {}) spec, extra = vela_options(vela.get("options", "")) diff --git a/documentation/pack-provenance.md b/documentation/executorch-pack-maintenance.md similarity index 95% rename from documentation/pack-provenance.md rename to documentation/executorch-pack-maintenance.md index 5cf2144a..ec67913a 100644 --- a/documentation/pack-provenance.md +++ b/documentation/executorch-pack-maintenance.md @@ -1,4 +1,4 @@ -# Where the ExecuTorch CMSIS pack comes from +# ExecuTorch pack maintenance and versioning The `PyTorch::ExecuTorch` pack is installed into your CMSIS pack root like any other pack; nothing of it lives in this repository. This page explains @@ -48,7 +48,7 @@ ExecuTorch versions cannot make it read the wrong one. | `include/` | Public headers, **including the bundled `include/flatbuffers/`** | | `armclang_shims/` | Small compatibility shims for Arm Compiler 6 | | `Documentation/` | Pack README | -| `LICENSE` | Upstream BSD-3-Clause (the example code around it is Apache-2.0) | +| `LICENSE` | Upstream BSD-3-Clause (the template code around it is Apache-2.0) | It is a **source** pack: nothing is prebuilt. Every operator is a selectable component, which is what lets `create_ai_layer.py` narrow the link to @@ -96,12 +96,12 @@ cmake -S . -B cmake-out-arm \ -DEXECUTORCH_BUILD_KERNELS_QUANTIZED=ON \ -DEXECUTORCH_BUILD_FLATC=ON \ -DEXECUTORCH_BUILD_EXECUTOR_RUNNER=OFF \ - -DPYTHON_EXECUTABLE=/path/to/this/example/.venv/bin/python + -DPYTHON_EXECUTABLE=/path/to/this/template/.venv/bin/python cmake --build cmake-out-arm --config Release -j4 ``` `arm-none-eabi-gcc` must be on `PATH` (the one from `vcpkg-configuration.json` -does); `PYTHON_EXECUTABLE` points at this example's `.venv`, which has the +does); `PYTHON_EXECUTABLE` points at this template's `.venv`, which has the Python packages the generators import. Then run the generator with all four arguments (it refuses to run without @@ -138,7 +138,7 @@ python3 backends/arm/cmsis_pack/test/validate_pack.py "$PACK.pack" These checks catch the parts that go missing quietly; they do not prove that the operators a model needs are present or that the pack compiles. Install it -and build this example against it, with the pack version pinned in the +and build this template against it, with the pack version pinned in the csolution and the cproject: ```bash diff --git a/documentation/mlops-flow.md b/documentation/mlops-flow.md index ed93f9bb..a96a7f87 100644 --- a/documentation/mlops-flow.md +++ b/documentation/mlops-flow.md @@ -1,7 +1,7 @@ # The MLOps flow The `mlops:` node in `cmsis-executorch.csolution.yml` is the central -definition of the Ethos-U target for this example. It follows the CMSIS-Toolbox +definition of the initial Ethos-U target for this template. It follows the CMSIS-Toolbox [MLOps information](https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information) specification. This document explains how the three build steps use and propagate that information. @@ -80,7 +80,7 @@ on the FVP. This is the hand-over point to the MLOps side: everything a model-export pipeline needs to know about the target is in this one file, and nothing in it -is specific to this example's Python code. +is specific to this template's Python code. `cbuild setup` writes the file even when the AI layer does not exist yet, so the flow also works on a checkout without a generated layer. diff --git a/model/model.py b/model/model.py index 8af0e024..4c63245d 100644 --- a/model/model.py +++ b/model/model.py @@ -1,6 +1,6 @@ # Copyright 2026 Arm Limited and/or its affiliates. # SPDX-License-Identifier: Apache-2.0 -"""The example model: a tiny CNN classifier, quantized to int8 for Ethos-U85 by create_ai_layer.py. +"""The starter model: a tiny CNN classifier, quantized to int8 for Ethos-U85 by create_ai_layer.py. Small enough to export in seconds and fully partition onto the NPU, but real enough to exercise conv / relu / pool / linear through Vela. Input is a single @@ -38,7 +38,7 @@ def forward(self, x: torch.Tensor) -> torch.Tensor: def get_model(input_shape: tuple[int, ...] = INPUT_SHAPE) -> nn.Module: - # Fixed seed: the example uses untrained (random) weights, and a fixed seed + # Fixed seed: the starter model uses untrained (random) weights, and a fixed seed # keeps the exported program identical from one export to the next (the # C array also embeds the Vela options, so the same working directory is # part of that guarantee). @@ -49,7 +49,7 @@ def get_model(input_shape: tuple[int, ...] = INPUT_SHAPE) -> nn.Module: def get_calibration_inputs( input_shape: tuple[int, ...] = INPUT_SHAPE, calibration_samples: int = 2 ) -> list[torch.Tensor]: - """Float samples for quantization calibration; the first one is also the export example. + """Float samples for quantization calibration; the first one is also the export input. Fixed values keep the quantization parameters, and with them the output logits in the README, the same from one export to the next. Replace them diff --git a/src/app_main.cpp b/src/app_main.cpp index b7fc869f..ecd29d9b 100644 --- a/src/app_main.cpp +++ b/src/app_main.cpp @@ -1,7 +1,7 @@ // Copyright 2026 Arm Limited and/or its affiliates. // SPDX-License-Identifier: Apache-2.0 // -// Headless ExecuTorch runner for the Ethos-U85 example. Loads the .pte +// Headless ExecuTorch runner for an Ethos-U application. Loads the .pte // embedded by the AI layer (model_pte.h, see create_ai_layer.py), runs one // inference on the NPU, and prints the output logits. Built entirely from the // PyTorch::ExecuTorch pack's runtime + operator components; the board layer @@ -24,6 +24,25 @@ #include "arm_embedded_module.hpp" #include "model_pte.h" +#define APP_STRINGIFY_IMPL(value) #value +#define APP_STRINGIFY(value) APP_STRINGIFY_IMPL(value) + +#if defined(ETHOSU55) +#define APP_ETHOS_U_NAME "Ethos-U55" +#elif defined(ETHOSU65) +#define APP_ETHOS_U_NAME "Ethos-U65" +#elif defined(ETHOSU85) +#define APP_ETHOS_U_NAME "Ethos-U85" +#else +#error "Unknown Ethos-U configuration" +#endif + +#ifdef ETHOSU_MACS +#define APP_ETHOS_U_CONFIG APP_ETHOS_U_NAME "-" APP_STRINGIFY(ETHOSU_MACS) +#else +#define APP_ETHOS_U_CONFIG APP_ETHOS_U_NAME +#endif + using arm::embedded::EmbeddedModule; using executorch::aten::DimOrderType; using executorch::aten::ScalarType; @@ -63,7 +82,7 @@ alignas(16) uint8_t g_temp_pool[kTempPoolSize] APP_POOL_ATTRIBUTES; extern "C" int app_main(void) { executorch::runtime::runtime_init(); - printf("ExecuTorch Ethos-U85 example: %lu byte model\n", model_pte_size); + printf("ExecuTorch %s application: %lu byte model\n", APP_ETHOS_U_CONFIG, model_pte_size); EmbeddedModule module( model_pte, model_pte_size, @@ -107,7 +126,8 @@ extern "C" int app_main(void) { } printf("Test_result: PASS\n"); - printf("\x04"); // EOT: ends the FVP run (semihosting exit); a board just sees a 0x04 + fflush(stdout); + putchar('\x04'); // EOT: ends the FVP run fflush(stdout); return 0; }