From 7abfde470e16f3a5fc6a205ab0d9f9c003244522 Mon Sep 17 00:00:00 2001 From: Matthias Hertel <11649409+MatthiasHertel80@users.noreply.github.com> Date: Fri, 16 Oct 2026 14:48:32 +0200 Subject: [PATCH 1/4] Traffic counter on the Alif AppKit-E7: YOLO26n on the Ethos-U55 The traffic counter as developed on github.com/MatthiasHertelArm/ cmsis-executorch-traffic-counter (full history there): one CMSIS solution with the project traffic/traffic.cproject.yml on two target-types with the same Cortex-M55 and Ethos-U55-256, the AppKit-E7 (camera, panel, joystick, SDS over the User USB) and the Corstone-300 FVP (the detector and the tracker on the test image). Ultralytics YOLO26n without its attention blocks, fine-tuned on the COCO images with vehicles, exported with ExecuTorch and compiled by Vela, runs whole on the NPU in 31 ms per 416x416 frame; a tracker counts each vehicle once, per class and direction, as it crosses a line. The AI layer, the weights and the pack lock file are committed so that a clone builds the validated image; CI exports the layer, builds both targets and runs the FVP. --- .alif/M55_HP_mram_cfg_e7.json | 43 + .alif/M55_HP_mram_stub.bin | Bin 0 -> 3040 bytes .alif/app-device-config-e7.json | 150 + .github/workflows/build.yml | 166 + .gitignore | 91 +- .vscode.d/tasks.json | 205 + .vscode/fvp.Dockerfile | 41 + .vscode/fvp.sh | 144 + .vscode/launch.json | 183 + LICENSE | 1 + README.md | 229 +- ai_layer/ai_layer.clayer.yml | 28 + ai_layer/model_io.h | 35 + ai_layer/model_pte.c | 142325 +++++++++++++++ ai_layer/model_pte.h | 10 + board/AppKit-E7/AppKit-E7.h | 37 + board/AppKit-E7/Board-Traffic.clayer.yml | 186 + .../BSP/AE722F80F55D5LS_M55_HP/board_defs.h | 2401 + .../board_defs.h.base@2.2.0 | 2401 + .../RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h | 241 + .../AE722F80F55D5LS_M55_HP/gpios.h.base@2.2.0 | 241 + .../RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h | 934 + .../AE722F80F55D5LS_M55_HP/pins.h.base@2.2.0 | 931 + board/AppKit-E7/RTE/CMSIS/RTX_Config.c | 67 + .../RTE/CMSIS/RTX_Config.c.base@5.2.0 | 67 + board/AppKit-E7/RTE/CMSIS/RTX_Config.h | 663 + .../RTE/CMSIS/RTX_Config.h.base@5.6.1 | 663 + .../AE722F80F55D5LS_M55_HP/RTE_Device.h | 9675 + .../RTE_Device.h.base@2.2.0 | 9675 + .../AE722F80F55D5LS_M55_HP/app_mem_regions.h | 197 + .../app_mem_regions.h.base@3.0.0 | 197 + .../Device/AE722F80F55D5LS_M55_HP/app_tz.h | 1288 + .../app_tz.h.base@2.1.0 | 1288 + .../AE722F80F55D5LS_M55_HP/core_config.h | 43 + .../core_config.h.base@2.1.0 | 43 + .../linker_ac6_mram.sct | 119 + .../linker_ac6_mram.sct.base@2.2.0 | 119 + .../linker_ac6_ospi_boot.sct | 114 + .../linker_ac6_ospi_boot.sct.base@2.1.0 | 114 + .../AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct | 109 + .../linker_ac6_tcm.sct.base@2.1.0 | 109 + .../regions_AppKit-E7-AIML.h | 113 + board/AppKit-E7/RTE/SDS/sds_config.h | 55 + .../AppKit-E7/RTE/SDS/sds_config.h.base@3.1.0 | 55 + .../RTE/SDS/sdsio_client_usb_mdk_config.h | 51 + .../sdsio_client_usb_mdk_config.h.base@3.0.0 | 51 + board/AppKit-E7/RTE/USB/USBD_Config_0.h | 150 + .../RTE/USB/USBD_Config_0.h.base@8.0.0 | 139 + .../RTE/USB/USBD_Config_CustomClass_0.h | 3772 + .../USBD_Config_CustomClass_0.h.base@5.3.1 | 3772 + board/AppKit-E7/RTE/USB/USB_Debug.h | 73 + .../AppKit-E7/RTE/USB/USB_Debug.h.base@8.0.0 | 73 + board/AppKit-E7/board_display.c | 122 + board/AppKit-E7/board_display.h | 43 + board/AppKit-E7/ethos_setup.c | 117 + board/AppKit-E7/ethosu_cb_dcache.c | 114 + board/AppKit-E7/linker_ac6_traffic.sct.src | 123 + board/AppKit-E7/main.c | 139 + board/AppKit-E7/main.h | 41 + board/AppKit-E7/retarget_stdio_log.c | 87 + board/Corstone-300/Board-Traffic.clayer.yml | 79 + board/Corstone-300/Corstone-300.h | 26 + board/Corstone-300/RTE/CMSIS/RTX_Config.c | 67 + .../RTE/CMSIS/RTX_Config.c.base@5.2.0 | 67 + board/Corstone-300/RTE/CMSIS/RTX_Config.h | 663 + .../RTE/CMSIS/RTX_Config.h.base@5.6.1 | 663 + .../SSE-300-MPS3/ac6_linker_script.sct.src | 109 + .../RTE/Device/SSE-300-MPS3/device_cfg.h | 148 + .../SSE-300-MPS3/device_cfg.h.base@1.1.4 | 148 + .../Device/SSE-300-MPS3/startup_SSE300MPS3.c | 487 + .../startup_SSE300MPS3.c.base@1.1.1 | 487 + .../Device/SSE-300-MPS3/system_SSE300MPS3.c | 105 + .../system_SSE300MPS3.c.base@1.1.1 | 105 + board/Corstone-300/ethos_setup.c | 103 + board/Corstone-300/fvp_config.txt | 35 + board/Corstone-300/main.c | 69 + board/Corstone-300/main.h | 38 + board/Corstone-300/regions_SSE-300.h | 82 + board/Corstone-300/retarget_stdio.c | 101 + cmsis-executorch.cbuild-pack.yml | 31 + cmsis-executorch.csolution.yml | 139 + create_ai_layer.py | 391 + documentation/mlops-flow.md | 150 + documentation/pack-provenance.md | 149 + documentation/traffic-counter.md | 466 + model/model.py | 40 + model/traffic.py | 435 + model/yolo.py | 101 + model/yolo26n-noattn-vehicles.pt | Bin 0 -> 5515721 bytes model/yolo26n-noattn.yaml | 52 + recordings/traffic/CameraIn.sds.yml | 14 + recordings/traffic/Detections.sds.yml | 212 + recordings/traffic/Panel.sds.yml | 17 + requirements-arm-tosa.txt | 15 + requirements.txt | 15 + setup_venv.bat | 40 + setup_venv.py | 223 + setup_venv.sh | 33 + src/LICENSE-ExecuTorch | 37 + src/arm_embedded_module.cpp | 260 + src/arm_embedded_module.hpp | 553 + tools/console_log.py | 98 + tools/sdsio_rtt_bridge.py | 144 + tools/setools_mram.py | 95 + traffic/app_traffic.cpp | 772 + traffic/attention.c | 183 + traffic/attention.h | 45 + traffic/camera.c | 148 + traffic/camera.h | 89 + traffic/count_playback.py | 273 + traffic/detector.cpp | 506 + traffic/detector.h | 76 + traffic/ethosu_rtos.c | 107 + traffic/eval_vehicles.py | 192 + traffic/image.c | 378 + traffic/image.h | 84 + traffic/images_to_sds.py | 128 + traffic/joystick.c | 101 + traffic/joystick.h | 44 + traffic/make_test_image.py | 90 + traffic/panel_to_video.py | 153 + traffic/rec_play.c | 318 + traffic/rec_play.h | 72 + traffic/sds_session.py | 161 + traffic/tracker.c | 223 + traffic/tracker.h | 79 + traffic/traffic.cproject.yml | 99 + traffic/train_vehicles.py | 166 + vcpkg-configuration.json | 18 + 129 files changed, 196443 insertions(+), 17 deletions(-) create mode 100644 .alif/M55_HP_mram_cfg_e7.json create mode 100644 .alif/M55_HP_mram_stub.bin create mode 100644 .alif/app-device-config-e7.json create mode 100644 .github/workflows/build.yml create mode 100644 .vscode.d/tasks.json create mode 100644 .vscode/fvp.Dockerfile create mode 100755 .vscode/fvp.sh create mode 100644 .vscode/launch.json create mode 100644 ai_layer/ai_layer.clayer.yml create mode 100644 ai_layer/model_io.h create mode 100644 ai_layer/model_pte.c create mode 100644 ai_layer/model_pte.h create mode 100644 board/AppKit-E7/AppKit-E7.h create mode 100644 board/AppKit-E7/Board-Traffic.clayer.yml create mode 100644 board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h create mode 100644 board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h.base@2.2.0 create mode 100644 board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h create mode 100644 board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h.base@2.2.0 create mode 100644 board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h create mode 100644 board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h.base@2.2.0 create mode 100644 board/AppKit-E7/RTE/CMSIS/RTX_Config.c create mode 100644 board/AppKit-E7/RTE/CMSIS/RTX_Config.c.base@5.2.0 create mode 100644 board/AppKit-E7/RTE/CMSIS/RTX_Config.h create mode 100644 board/AppKit-E7/RTE/CMSIS/RTX_Config.h.base@5.6.1 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h.base@3.0.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h.base@2.1.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h.base@2.1.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct.base@2.2.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct.base@2.1.0 create mode 100644 board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/regions_AppKit-E7-AIML.h create mode 100644 board/AppKit-E7/RTE/SDS/sds_config.h create mode 100644 board/AppKit-E7/RTE/SDS/sds_config.h.base@3.1.0 create mode 100644 board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h create mode 100644 board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h.base@3.0.0 create mode 100644 board/AppKit-E7/RTE/USB/USBD_Config_0.h create mode 100644 board/AppKit-E7/RTE/USB/USBD_Config_0.h.base@8.0.0 create mode 100644 board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h create mode 100644 board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h.base@5.3.1 create mode 100644 board/AppKit-E7/RTE/USB/USB_Debug.h create mode 100644 board/AppKit-E7/RTE/USB/USB_Debug.h.base@8.0.0 create mode 100644 board/AppKit-E7/board_display.c create mode 100644 board/AppKit-E7/board_display.h create mode 100644 board/AppKit-E7/ethos_setup.c create mode 100644 board/AppKit-E7/ethosu_cb_dcache.c create mode 100644 board/AppKit-E7/linker_ac6_traffic.sct.src create mode 100644 board/AppKit-E7/main.c create mode 100644 board/AppKit-E7/main.h create mode 100644 board/AppKit-E7/retarget_stdio_log.c create mode 100644 board/Corstone-300/Board-Traffic.clayer.yml create mode 100644 board/Corstone-300/Corstone-300.h create mode 100644 board/Corstone-300/RTE/CMSIS/RTX_Config.c create mode 100644 board/Corstone-300/RTE/CMSIS/RTX_Config.c.base@5.2.0 create mode 100644 board/Corstone-300/RTE/CMSIS/RTX_Config.h create mode 100644 board/Corstone-300/RTE/CMSIS/RTX_Config.h.base@5.6.1 create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c create mode 100644 board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 create mode 100644 board/Corstone-300/ethos_setup.c create mode 100644 board/Corstone-300/fvp_config.txt create mode 100644 board/Corstone-300/main.c create mode 100644 board/Corstone-300/main.h create mode 100644 board/Corstone-300/regions_SSE-300.h create mode 100644 board/Corstone-300/retarget_stdio.c create mode 100644 cmsis-executorch.cbuild-pack.yml create mode 100644 cmsis-executorch.csolution.yml create mode 100644 create_ai_layer.py create mode 100644 documentation/mlops-flow.md create mode 100644 documentation/pack-provenance.md create mode 100644 documentation/traffic-counter.md create mode 100644 model/model.py create mode 100644 model/traffic.py create mode 100644 model/yolo.py create mode 100644 model/yolo26n-noattn-vehicles.pt create mode 100644 model/yolo26n-noattn.yaml create mode 100644 recordings/traffic/CameraIn.sds.yml create mode 100644 recordings/traffic/Detections.sds.yml create mode 100644 recordings/traffic/Panel.sds.yml create mode 100644 requirements-arm-tosa.txt create mode 100644 requirements.txt create mode 100644 setup_venv.bat create mode 100755 setup_venv.py create mode 100755 setup_venv.sh create mode 100644 src/LICENSE-ExecuTorch create mode 100644 src/arm_embedded_module.cpp create mode 100644 src/arm_embedded_module.hpp create mode 100644 tools/console_log.py create mode 100644 tools/sdsio_rtt_bridge.py create mode 100644 tools/setools_mram.py create mode 100644 traffic/app_traffic.cpp create mode 100644 traffic/attention.c create mode 100644 traffic/attention.h create mode 100644 traffic/camera.c create mode 100644 traffic/camera.h create mode 100644 traffic/count_playback.py create mode 100644 traffic/detector.cpp create mode 100644 traffic/detector.h create mode 100644 traffic/ethosu_rtos.c create mode 100644 traffic/eval_vehicles.py create mode 100644 traffic/image.c create mode 100644 traffic/image.h create mode 100644 traffic/images_to_sds.py create mode 100644 traffic/joystick.c create mode 100644 traffic/joystick.h create mode 100644 traffic/make_test_image.py create mode 100644 traffic/panel_to_video.py create mode 100644 traffic/rec_play.c create mode 100644 traffic/rec_play.h create mode 100644 traffic/sds_session.py create mode 100644 traffic/tracker.c create mode 100644 traffic/tracker.h create mode 100644 traffic/traffic.cproject.yml create mode 100644 traffic/train_vehicles.py create mode 100644 vcpkg-configuration.json diff --git a/.alif/M55_HP_mram_cfg_e7.json b/.alif/M55_HP_mram_cfg_e7.json new file mode 100644 index 0000000..15f8140 --- /dev/null +++ b/.alif/M55_HP_mram_cfg_e7.json @@ -0,0 +1,43 @@ +{ + "DEVICE": { + "disabled": false, + "binary": "app-device-config-e7.json", + "version": "0.5.00", + "signed": true + }, + "A32_STUB": { + "disabled": false, + "binary": "a32_stub_0.bin", + "version": "1.0.0", + "signed": true, + "loadAddress": "0x02000000", + "cpu_id": "A32_0", + "flags": [ + "load", + "boot" + ] + }, + "HP_APP": { + "disabled": false, + "binary": "M55_HP_mram_stub.bin", + "version": "1.0.0", + "signed": false, + "mramAddress": "0x80200000", + "cpu_id": "M55_HP", + "flags": [ + "boot" + ] + }, + "HE_STUB": { + "disabled": false, + "binary": "m55_stub_he.bin", + "version": "1.0.0", + "signed": true, + "loadAddress": "0x58000000", + "cpu_id": "M55_HE", + "flags": [ + "load", + "boot" + ] + } +} diff --git a/.alif/M55_HP_mram_stub.bin b/.alif/M55_HP_mram_stub.bin new file mode 100644 index 0000000000000000000000000000000000000000..9b5f905696b418b66cb6185ba8e4378f52526686 GIT binary patch literal 3040 zcmeHJPiP!f82{evY-TpuvXeH!P1Nk0B($Li+1gS~L7j9ryR$LvnnE$)!O6vpr`>{w zf`X&zq5gq*@}dV1R-r0s)CJLOXCrHg&_mJ`6g_l9i5n8FZ!>9Ul0u%}qy$0;z0^xf z9=!Sf{pNe$_j_+11EA3NLe%<3rqc`_q4*vR+-U26bqM4q}Gt)$tKS7$V)|@G2rc!njvxI?=8+ z^@sMufi82%kw8?t3}1`TiyNA@@;2P_#EdQ@_*Adg^_DbCQ?kn4D_nd=e4ZY0sx&32 z#RU&5o3Klm_rnHiDTT&&#?c_$eJI1;D6PM@) zYM7eZ25vL16gx5Brj<_FCdW8DC0q!q%!~9aA{Y1Oo z(f^AFd+6)hN}kdoV0~UpC#Je$ogs#{Jg*u#jDRuxxK0f2Uf}-vaY~T`$|!aYl)EKf z_R7$$Qx=1=Hw8y^@+@U-s9yy_%iaV4qh5m^&JZJv*?SoD5W|-i%1cGCGtbLb;$L1#{D(Dqee>D@Z?9=?_ctOal1Hcm&Cqlgfi$K@;J zxw}B$b*HPtYb~rUgEA|*KR5G**pA9X}NTWE)vj~md6u8=g^-|U&nLh^Cse> z6aT9P0AY^5AfS}z`2iU}z1EwYx9$ZPoaceTy_/ folders +# are generated; the layers' RTE/ configuration files are sources. +out/ +tmp/ +**/RTE/_*/ +.cmsis/ +*.cbuild-idx.yml +*.cbuild-pack.yml +# The solution's pack lock file is source: it pins the pack versions the +# AppKit-E7 build was validated with (its RTE config files are from them). +!/cmsis-executorch.cbuild-pack.yml +*.cbuild-mlops.yml +*.update@* +.cmd.jlink + +# Compiler-generated dependencies *.d +# CMSIS Solution drop-ins are source files, despite the directory suffix. +!.vscode.d/ # Object files *.o *.ko *.obj -*.elf # Linker output +*.elf *.ilk *.map *.exp -# Precompiled Headers +# Precompiled headers *.gch *.pch @@ -22,13 +48,13 @@ *.la *.lo -# Shared objects (inc. Windows DLLs) +# Shared objects *.dll *.so *.so.* *.dylib -# Executables +# Executables and images *.exe *.out *.app @@ -41,15 +67,50 @@ *.su *.idb *.pdb +*.dwo -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf +# Regenerated by the CMSIS Solution / clangd extensions on every build, with +# absolute paths for the machine that built it -- so it cannot be committed in +# a portable form. Not committing it loses nothing: it is generated for you. +.clangd -# debug information files -*.dwo +# FVP output captured by CI and by the manual run in the README +fvp_stdout.log + +# Editor config. The CMSIS Solution extension regenerates tasks.json, +# settings.json and cmsis.json; only the FVP run/debug wiring is kept: the +# model shim + its Dockerfile, and launch.json, whose Arm-FVP launch config is +# "manual" (see the comment in it). The leading negation overrides a global +# excludes file that ignores every .vscode directory. +!.vscode/ +.vscode/* +!.vscode/fvp.sh +!.vscode/fvp.Dockerfile +!.vscode/launch.json + +# SDS recordings and the videos made from them; the stream metadata *.sds.yml +# next to them is source. +recordings/*.sds +recordings/*.index.txt +recordings/*.mp4 +# The traffic counter's recordings (documentation/traffic-counter.md): the +# streams anywhere under recordings/, and every folder under recordings/traffic +# (camera recordings, video clips turned into CameraIn streams, their +# playbacks); recordings/traffic/*.sds.yml is source. The SDS extension's +# local state: its database and the SDSIO server configuration it writes. +recordings/**/*.sds +recordings/traffic/*/ +.sdsstudio +*.sdsio.yml + +# The test image is generated from a photo that is not ours to redistribute +# (traffic/make_test_image.py), and model/yolo.py caches the COCO-pretrained +# YOLO26n weights and the COCO128 calibration images next to itself. +traffic/test_image.c +traffic/test_image.h +model/.cache +# Frames ffmpeg extracts for the "SDS: video to CameraIn stream" task. +.sds_frames/ + +# macOS Finder metadata +.DS_Store diff --git a/.vscode.d/tasks.json b/.vscode.d/tasks.json new file mode 100644 index 0000000..95c3f61 --- /dev/null +++ b/.vscode.d/tasks.json @@ -0,0 +1,205 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Setup Python virtual environment", + "type": "shell", + "command": "./setup_venv.sh", + "windows": { + "command": ".\\setup_venv.bat" + }, + "options": { + "cwd": "${workspaceFolder}" + }, + "problemMatcher": [] + }, + { + "label": "Setup Python virtual environment (uv)", + "detail": "Same as above, but with uv (must be on PATH): uv creates .venv for the Python version you enter and can download that interpreter", + "type": "shell", + "command": "./setup_venv.sh", + "windows": { + "command": ".\\setup_venv.bat" + }, + "args": [ + "--uv", + "--python", + "${input:setupPythonVersion}" + ], + "options": { + "cwd": "${workspaceFolder}" + }, + "problemMatcher": [] + }, + { + "label": "Create AI layer", + "detail": "Export model/traffic.py for the NPU in cmsis-executorch.cbuild-mlops.yml and write ai_layer/ (run a CMSIS build or 'cbuild setup' first)", + "type": "shell", + "command": "python3", + "args": [ + "create_ai_layer.py", + "cmsis-executorch.cbuild-mlops.yml" + ], + "windows": { + "command": "python" + }, + "options": { + "cwd": "${workspaceFolder}" + }, + "problemMatcher": [] + }, + { + "label": "Alif: Install M55_HP debug stubs (AppKit-E7, single core configuration)", + "detail": "Programs the ATOC/MRAM stubs with Alif SETOOLS for the AppKit-E7's device (AE722F80F55D5LS), so that the Secure Enclave boots the HP core from its MRAM region and J-Link can load and debug it. The AppKit-E7 is silicon revision B4 (tools-config -p resets it to A0, and every later step then says 'Revision is invalid'). Set SW4 to SEUART, set 'alif.setools.root' in your VS Code settings.", + "type": "shell", + "command": [ + "cp './.alif/M55_HP_mram_cfg_e7.json' '${config:alif.setools.root}/build/config/M55_HP_mram_cfg_e7.json';", + "cp './.alif/app-device-config-e7.json' '${config:alif.setools.root}/build/config/app-device-config-e7.json';", + "cp './.alif/M55_HP_mram_stub.bin' '${config:alif.setools.root}/build/images/M55_HP_mram_stub.bin';", + "cd '${config:alif.setools.root}';", + "./tools-config -p 'E7 (AE722F80F55D5LS) - 5.5 MRAM / 13.5 SRAM' -r B4;", + "./app-gen-toc -f 'build/config/M55_HP_mram_cfg_e7.json';", + "./app-write-mram -p ${input:discoverCOM};" + ], + "options": { + "shell": { + "executable": "/bin/bash", + "args": [ + "-c" + ] + } + }, + "problemMatcher": [] + }, + { + "label": "SDS: play recording to the board (USB)", + "detail": "Plays CameraIn..sds of the chosen folder into the detector over the User USB (SDS:IO:USB firmware, board running) and records Detections..p.sds next to it. One SDSIO server at a time: stop any other playback first.", + "type": "shell", + "command": "${workspaceFolder}/.venv/bin/python", + "args": [ + "traffic/sds_session.py", + "play", + "--transport", + "usb", + "--workdir", + "recordings/traffic/${input:sdsRecording}" + ], + "options": { + "cwd": "${workspaceFolder}" + }, + "problemMatcher": [] + }, + { + "label": "SDS: record from the camera (USB)", + "detail": "Records CameraIn (model inputs) and Detections from the live camera for the given seconds into recordings/traffic over the User USB.", + "type": "shell", + "command": "${workspaceFolder}/.venv/bin/python", + "args": [ + "traffic/sds_session.py", + "record", + "${input:sdsSeconds}", + "--transport", + "usb" + ], + "options": { + "cwd": "${workspaceFolder}" + }, + "problemMatcher": [] + }, + { + "label": "SDS: check playback against the host model", + "detail": "Lists the board's detections of the last playback of the chosen folder next to the float model's on the same inputs.", + "type": "shell", + "command": "${workspaceFolder}/.venv/bin/python", + "args": [ + "traffic/images_to_sds.py", + "check", + "recordings/traffic/${input:sdsRecording}" + ], + "options": { + "cwd": "${workspaceFolder}" + }, + "problemMatcher": [] + }, + { + "label": "SDS: video to CameraIn stream", + "detail": "Extracts frames from a video with ffmpeg at the given rate and builds recordings/traffic/playback/CameraIn.0.sds (letterboxed or filled), ready for 'SDS: play recording to the board'.", + "type": "shell", + "command": "rm -rf .sds_frames && mkdir -p .sds_frames && ffmpeg -v error -i \"${input:sdsVideo}\" -vf fps=${input:sdsFps} -q:v 3 .sds_frames/f%06d.jpg && rm -rf recordings/traffic/playback && ${workspaceFolder}/.venv/bin/python traffic/images_to_sds.py make ${input:sdsFraming} recordings/traffic/playback .sds_frames/f*.jpg && rm -rf .sds_frames", + "options": { + "cwd": "${workspaceFolder}", + "shell": { + "executable": "/bin/bash", + "args": [ + "-c" + ] + } + }, + "problemMatcher": [] + } + ], + "inputs": [ + { + "id": "discoverCOM", + "type": "pickString", + "description": "Select COM Port for SETOOLS?", + "options": [ + { + "label": "Yes - Enable COM Port Discovery using command option", + "value": "-d" + }, + { + "label": "No - COM port is already selected", + "value": "" + } + ], + "default": "" + }, + { + "id": "setupPythonVersion", + "type": "promptString", + "description": "Python version for uv (>=3.10,<3.15), e.g. 3.12 or 3.12.10", + "default": "3.12" + }, + { + "id": "sdsRecording", + "type": "promptString", + "description": "Recording folder under recordings/traffic (with CameraIn..sds for a playback): playback is what 'SDS: video to CameraIn stream' writes, . the top level that 'SDS: record from the camera' writes", + "default": "playback" + }, + { + "id": "sdsSeconds", + "type": "promptString", + "description": "Recording length in seconds", + "default": "20" + }, + { + "id": "sdsVideo", + "type": "promptString", + "description": "Video file to convert (any format ffmpeg reads)", + "default": "" + }, + { + "id": "sdsFps", + "type": "promptString", + "description": "Frames per second to take from the video (the board detects about 11 per second)", + "default": "5" + }, + { + "id": "sdsFraming", + "type": "pickString", + "description": "How a wide frame meets the square model input", + "options": [ + { + "label": "fill: cut the sides, no black bars", + "value": "--fill" + }, + { + "label": "letterbox: keep the whole frame, bars above and below", + "value": "" + } + ], + "default": "--fill" + } + ] +} diff --git a/.vscode/fvp.Dockerfile b/.vscode/fvp.Dockerfile new file mode 100644 index 0000000..3c08cc5 --- /dev/null +++ b/.vscode/fvp.Dockerfile @@ -0,0 +1,41 @@ +# MDK FVP models for macOS hosts, which Arm does not build for. +# +# The image is the Linux build of the very same release the rest of the project +# pins in vcpkg-configuration.json (arm:models/arm/avh-fvp), so the model, the +# Ethos-U plugins and plugins/GDBServer.so are bit-identical to what a Linux or +# Windows developer gets from vcpkg. .vscode/fvp.sh builds it on first use. +FROM ubuntu:22.04 + +ARG DEBIAN_FRONTEND=noninteractive + +# 11.32.23 -> mdk-fvp-11.32_23_linux_arm64.tar.gz (fvp.sh derives and passes it) +ARG FVP_VERSION=11.32.23 +ARG FVP_ARCHIVE=mdk-fvp-11.32_23_linux_arm64.tar.gz +ARG FVP_BASE_URL=https://artifacts.tools.arm.com/avh + +# libpython is dlopen'd by the VSI/VIO bridges. We do not use them, but without +# a libpython3*.so the model prints a five-paragraph error before every run. +# The archive unpacks as .//{bin,plugins,...}, hence --strip-components 2. +RUN apt-get update && \ + apt-get install -y --no-install-recommends ca-certificates curl libatomic1 libpython3.10 && \ + ln -sf libpython3.10.so.1.0 "/usr/lib/$(uname -m)-linux-gnu/libpython3.10.so" && \ + curl -fsSL -o /tmp/fvp.tar.gz "${FVP_BASE_URL}/${FVP_VERSION}/${FVP_ARCHIVE}" && \ + mkdir -p /opt/avh-fvp && \ + tar -xf /tmp/fvp.tar.gz --strip-components 2 -C /opt/avh-fvp && \ + rm /tmp/fvp.tar.gz && \ + apt-get purge -y curl && apt-get autoremove -y && \ + rm -rf /var/lib/apt/lists/* + +# The Arm user-based licence in ~/.armlm is bound to the account that activated +# it, so the container has to run as that same user name and uid or the model +# aborts with "The license found is assigned to another user". +ARG USERNAME=root +ARG USERID=0 +RUN if [ "${USERID}" != "0" ]; then \ + groupadd -g "${USERID}" "${USERNAME}" && \ + useradd -l -r -u "${USERID}" -g "${USERNAME}" "${USERNAME}"; \ + fi +USER ${USERNAME} + +ENV PATH="${PATH}:/opt/avh-fvp/bin" +ENV AVH_FVP_PLUGINS=/opt/avh-fvp/plugins diff --git a/.vscode/fvp.sh b/.vscode/fvp.sh new file mode 100755 index 0000000..5f420aa --- /dev/null +++ b/.vscode/fvp.sh @@ -0,0 +1,144 @@ +#!/usr/bin/env bash +# Stand-in for the FVP_Corstone_SSE-300_Ethos-U55 executable, referenced from +# the `debugger: model:` node of the SSE-300-U55 target-set. The CMSIS Solution +# extension runs it both as the "CMSIS Run" task and as the gdbtarget debug +# server, in the latter case with +# +# -D --plugin $AVH_FVP_PLUGINS/GDBServer.so -C GDBServer.port=3333 \ +# -f board/Corstone-300/fvp_config.txt --simlimit 600 -a .hex +# +# It does two things the bare model command cannot: +# +# * resolves plugins/GDBServer.so itself. The generated launch config takes +# the path from $AVH_FVP_PLUGINS, which only exists in a shell that has run +# `vcpkg activate` -- VS Code, started from Finder or Spotlight, has not. +# * runs the model in Docker on macOS, where Arm publishes no FVP build, with +# the GDB port forwarded to the host so arm-none-eabi-gdb can reach it. +# +# On Linux it just execs the real model. On Windows, where the extension cannot +# run a bash script, point the csolution's `model:` at FVP_Corstone_SSE-300_Ethos-U55.exe. +set -euo pipefail + +MODEL="${FVP_MODEL:-FVP_Corstone_SSE-300_Ethos-U55}" +FVP_VERSION="${FVP_VERSION:-11.32.23}" # keep in sync with vcpkg-configuration.json +IMAGE="${FVP_IMAGE:-cmsis-fvp:${FVP_VERSION}}" +HERE="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" + +is_macos() { [[ "$(uname -s)" == "Darwin" ]]; } + +# Where GDBServer.so lives, given that $AVH_FVP_PLUGINS is often unset. +plugin_dir() { + if is_macos; then + echo "/opt/avh-fvp/plugins" # inside the container + return + fi + if [[ -n "${AVH_FVP_PLUGINS:-}" && -d "${AVH_FVP_PLUGINS}" ]]; then + echo "${AVH_FVP_PLUGINS%/}" + return + fi + local model_path + model_path="$(command -v "${MODEL}" 2>/dev/null || true)" + [[ -n "${model_path}" ]] && echo "$(dirname "$(dirname "$(realpath "${model_path}")")")/plugins" +} + +# Rewrite `--plugin ` when does not resolve, and pick the GDB port +# out of `-C GDBServer.port=` so the macOS branch knows what to forward. +ARGS=() +GDB_PORT="" +ALLOW_REMOTE_SET=0 +while [[ $# -gt 0 ]]; do + case "$1" in + --plugin) + plugin="${2:-}" + if [[ ! -f "${plugin}" ]] || is_macos; then + dir="$(plugin_dir)" + [[ -n "${dir}" ]] && plugin="${dir}/$(basename "${plugin}")" + fi + ARGS+=("--plugin" "${plugin}") + shift 2 + ;; + -C) + [[ "${2:-}" == GDBServer.port=* ]] && GDB_PORT="${2#GDBServer.port=}" + [[ "${2:-}" == GDBServer.allow_remote=* ]] && ALLOW_REMOTE_SET=1 + ARGS+=("-C" "${2:-}") + shift 2 + ;; + -C*) + [[ "$1" == -CGDBServer.port=* ]] && GDB_PORT="${1#-CGDBServer.port=}" + [[ "$1" == -CGDBServer.allow_remote=* ]] && ALLOW_REMOTE_SET=1 + ARGS+=("$1") + shift + ;; + *) + ARGS+=("$1") + shift + ;; + esac +done + +# The model block-buffers its own stdout whenever it is a pipe -- which it +# always is under VS Code -- so "GDBServer: Listening ... port=3333" and every +# semihosting printf sit in a 4KB buffer until the model exits. The debug +# adapter waits for that banner to know the server is up (target.serverPortRegExp +# in launch.json), so without line buffering it gives up and kills the model +# just before the line it was waiting for gets flushed. +RUNNER=() +command -v stdbuf >/dev/null 2>&1 && RUNNER=(stdbuf -oL -eL) + +if ! is_macos; then + command -v "${MODEL}" >/dev/null 2>&1 || { + echo "${MODEL} not found on PATH. Run 'vcpkg activate' in this folder," >&2 + echo "or set FVP_MODEL to the full path of the model executable." >&2 + exit 1 + } + exec "${RUNNER[@]}" "${MODEL}" "${ARGS[@]}" +fi + +# ---------------------------------------------------------------- macOS/Docker +docker info >/dev/null 2>&1 || { + echo "Docker is not running. On macOS the FVP runs in a container because" >&2 + echo "Arm ships no macOS build of the model." >&2 + exit 1 +} + +if ! docker image inspect "${IMAGE}" >/dev/null 2>&1; then + case "$(uname -m)" in + arm64|aarch64) arch="arm64" ;; + *) arch="x86" ;; + esac + archive="mdk-fvp-${FVP_VERSION%.*}_${FVP_VERSION##*.}_linux_${arch}.tar.gz" + echo "Building ${IMAGE} from ${archive} (first run only, ~100MB download)." + echo "By using these models you accept the Arm FVP End User License Agreement:" + echo " https://artifacts.tools.arm.com/avh/${FVP_VERSION}/license_agreement.txt" + docker build -t "${IMAGE}" -f "${HERE}/fvp.Dockerfile" \ + --build-arg "FVP_VERSION=${FVP_VERSION}" \ + --build-arg "FVP_ARCHIVE=${archive}" \ + --build-arg "USERNAME=$(whoami)" \ + --build-arg "USERID=$(id -u)" \ + "${HERE}" >&2 +fi + +PORTS=() +NAME=() +if [[ -n "${GDB_PORT}" ]]; then + PORTS=(-p "${GDB_PORT}:${GDB_PORT}") + # GDBServer binds to localhost unless told otherwise, and a connection + # arriving through Docker's port forwarder is not localhost as far as the + # container is concerned -- without this GDB's first packet is met with a + # connection reset. + [[ "${ALLOW_REMOTE_SET}" == "0" ]] && ARGS+=("-C" "GDBServer.allow_remote=1") + # A container left behind by a debug session that ended badly still holds + # the port; the next launch would fail on bind rather than on connect. + NAME=(--name "cmsis-fvp-${GDB_PORT}") + docker rm -f "cmsis-fvp-${GDB_PORT}" >/dev/null 2>&1 || true +fi + +# $HOME is bind-mounted at the same path so the ELF, the config file and +# ~/.armlm are reachable under the paths the extension passes in. +MOUNTS=(--mount "type=bind,src=${HOME}/,dst=${HOME}/") +[[ "${PWD}" == "${HOME}"* ]] || MOUNTS+=(--mount "type=bind,src=${PWD}/,dst=${PWD}/") + +exec docker run --rm -i --init "${NAME[@]}" "${PORTS[@]}" "${MOUNTS[@]}" \ + --workdir "${PWD}" \ + --env "ARMLM_CACHED_LICENSES_LOCATION=${HOME}/.armlm" \ + "${IMAGE}" stdbuf -oL -eL "${MODEL}" "${ARGS[@]}" diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..59a33d7 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,183 @@ +{ + "version": "0.2.0", + "configurations": [ + { + // Generated by the CMSIS Solution extension from its Arm-FVP adapter + // template, then switched to "manual" because two "target" fields + // differ from the generated ones and would be lost on regeneration: + // "port": "" + "serverPortRegExp" -- with a port set, the debug + // adapter connects 0 ms after spawning the model, before the + // GDBServer plugin listens; blank port makes it wait for the + // "GDBServer: Listening ... port=3333" banner instead. + // "portDetectionTimeout" -- the first run on macOS builds the + // Docker image (see .vscode/fvp.sh). + // and one model option: GDBServer.shutdown_on_disconnect=1, or the + // model (its container on macOS) outlives the debug session once + // the application has exited. + // To re-sync after changing target-type or build-type: set + // "updateConfiguration" to "auto", run "CMSIS: Update Debug Tasks + // and Launch Configurations", then re-apply the fields above and + // set it back to "manual". + "name": "Arm-FVP@GDB (launch)", + "type": "gdbtarget", + "request": "launch", + "cwd": "${workspaceFolder}/", + "program": "out/traffic/SSE-300-U55/Release/traffic.axf", + "gdb": "arm-none-eabi-gdb", + "auxiliaryGdb": false, + "initCommands": [ + "set remote verbose-resume-supported-packet off", + "set remote verbose-resume-packet off", + "tbreak main" + ], + "target": { + "server": "${workspaceFolder}/.vscode/fvp.sh", + "serverParameters": [ + "-D", + "--plugin", + "${env:AVH_FVP_PLUGINS}/GDBServer.so", + "-C", + "GDBServer.port=3333", + "-C", + "GDBServer.shutdown_on_disconnect=1", + "-f", + "board/Corstone-300/fvp_config.txt", + "--simlimit", + "600", + "-a", + "out/traffic/SSE-300-U55/Release/traffic.hex" + ], + "port": "", + "serverPortRegExp": "GDBServer: Listening .*port=([0-9]+)", + "portDetectionTimeout": 300000 + }, + "cmsis": { + "cbuildRunFile": "${command:cmsis-csolution.getCbuildRunFile}", + "updateConfiguration": "manual" + } + }, + { + "name": "M55_HP JLink (launch)", + "type": "gdbtarget", + "request": "launch", + "cwd": "${workspaceFolder}/", + "program": "out/traffic/AppKit-E7/Release/traffic.axf", + "gdb": "arm-none-eabi-gdb", + "auxiliaryGdb": true, + "preLaunchTask": "CMSIS Load", + "initCommands": [ + "monitor reset 0", + "tbreak main", + "" + ], + "customResetCommands": [ + "monitor reset 0", + "maintenance flush register-cache", + "maintenance flush dcache", + "tbreak main", + "continue" + ], + "target": { + "server": "JLinkGDBServerCL", + "serverParameters": [ + "-device", + "AE722F80F55D5LS_M55_HP", + "-endian", + "little", + "-if", + "swd", + "-speed", + "4000", + "-halt", + "-noir", + "-vd", + "-nogui", + "-localhostonly", + "-silent", + "-port", + "3333", + "-TelnetPort", + "4444" + ], + "port": "3333" + }, + "cmsis": { + "cbuildRunFile": "${command:cmsis-csolution.getCbuildRunFile}", + "updateConfiguration": "auto" + } + }, + { + "name": "M55_HP JLink (attach)", + "type": "gdbtarget", + "request": "attach", + "cwd": "${workspaceFolder}/", + "program": "out/traffic/AppKit-E7/Release/traffic.axf", + "gdb": "arm-none-eabi-gdb", + "auxiliaryGdb": true, + "initCommands": [ + "" + ], + "customResetCommands": [ + "monitor reset 0", + "maintenance flush register-cache", + "maintenance flush dcache", + "tbreak main", + "continue" + ], + "target": { + "port": "3333" + }, + "cmsis": { + "cbuildRunFile": "${command:cmsis-csolution.getCbuildRunFile}", + "updateConfiguration": "auto" + } + }, + { + "name": "M55_HE JLink (launch)", + "type": "gdbtarget", + "request": "launch", + "cwd": "${workspaceFolder}/", + "program": "", + "gdb": "arm-none-eabi-gdb", + "auxiliaryGdb": true, + "initCommands": [ + "" + ], + "customResetCommands": [ + "monitor reset 0", + "maintenance flush register-cache", + "maintenance flush dcache", + "tbreak main", + "continue" + ], + "target": { + "server": "JLinkGDBServerCL", + "serverParameters": [ + "-device", + "AE722F80F55D5LS_M55_HE", + "-endian", + "little", + "-if", + "swd", + "-speed", + "4000", + "-halt", + "-noir", + "-vd", + "-nogui", + "-localhostonly", + "-silent", + "-port", + "3334", + "-TelnetPort", + "4445" + ], + "port": "3334" + }, + "cmsis": { + "cbuildRunFile": "${command:cmsis-csolution.getCbuildRunFile}", + "updateConfiguration": "auto" + } + } + ] +} diff --git a/LICENSE b/LICENSE index 261eeb9..d645695 100644 --- a/LICENSE +++ b/LICENSE @@ -1,3 +1,4 @@ + Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ diff --git a/README.md b/README.md index a7c8a2b..dd92f21 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,227 @@ -# CMSIS-Executorch-Traffic-Counter -This repo contains a Ultralytics YOLO26n example for an Ethos-U via ExecuTorch, a tracker and a counting line on a Cortex-M55, SDS recording and playback over USB +# Traffic counter on the Alif AppKit-E7: YOLO26n on the Ethos-U55 + +An Alif Ensemble E7 AppKit (AK-E7-AIML, Gen 2) counts the vehicles its camera +sees. Ultralytics YOLO26n, exported with ExecuTorch and compiled by Vela, runs +whole on the Ethos-U55-256 next to the Cortex-M55 HP core and finds bicycles, +cars, motorcycles, buses and trucks in each 416x416 frame. A small tracker +follows them from frame to frame and counts each one once, per class and +direction, as it crosses a line on the picture. The panel shows the camera +picture, the boxes, the line and the tallies, and the joystick moves the line. +Over the board's User USB, SDS records the model inputs and detections, or +plays a recorded clip back into the detector instead of the camera. + +| | | +|---|---| +| NPU | 31 ms per 416x416 frame (1.12 GMAC, 2.3 MB program in MRAM) | +| Loop with the camera | 25 fps; the camera conversion runs while the NPU works | +| SDS over USB | a 40-frame clip (20.7 MB) plays in about 8 s | + +The repository is a fork of the Arm example +[cmsis-executorch](https://github.com/Arm-Examples/cmsis-executorch): one CMSIS +solution, `cmsis-executorch.csolution.yml`, with one project, +`traffic/traffic.cproject.yml`, and two target-types with the same Cortex-M55 +and Ethos-U55-256: + +| Target-type | Hardware | Runs | +|-------------|----------|------| +| **AppKit-E7** | Alif Ensemble E7 AppKit, M55 HP core | the traffic counter: camera, panel, joystick, SDS | +| **SSE-300-U55** | Corstone-300 on the Arm FVP | the detector and the tracker on the test image, without a board | + +Both use the same AI layer, `ai_layer/`. The full technical description of +the traffic counter is [documentation/traffic-counter.md](documentation/traffic-counter.md). + +## 1. Host tools + +1. [VS Code](https://code.visualstudio.com/) with the extensions **Keil + Studio Pack** (`Arm.keil-studio-pack`, CMSIS Solution 1.70.0 or newer) and + **Python** (`ms-python.python`). Sign in with an Arm account when Keil + Studio asks; the free Keil MDK Community license is enough. When the + folder opens, accept the tools that the Arm Tools Environment Manager + offers from `vcpkg-configuration.json` (CMSIS-Toolbox, Arm Compiler 6, + CMake, Ninja). The traffic counter builds with Arm Compiler 6 only. +2. **Alif SETOOLS** from the + [Alif software and tools page](https://alifsemi.com/support/software-tools/ensemble/) + (login required). Set its root directory, the one with `app-gen-toc` and + `app-write-mram`, in your VS Code user settings: + + ```json + "alif.setools.root": "/absolute/path/to/setools" + ``` + +3. **SEGGER J-Link Software** V8.42 or later from + [segger.com](https://www.segger.com/downloads/jlink/). The board has an + on-board J-Link. +4. Python `>=3.10,<3.14` for the test image and the tools, and for SDS the + Python packages of SDSIO-Server (`utilities/requirements.txt` of the + `ARM::SDS` 3.1.0 pack; the USB interface needs libusb). `ffmpeg` if you + want to turn a video into a playback. +5. For the FVP only: the Arm FVPs come with the tools from + `vcpkg-configuration.json` on Linux and Windows. On macOS, where Arm ships + no FVP build, `.vscode/fvp.sh` runs the Linux FVP in Docker, so Docker has + to be running. + +## 2. Board + +- **PRG USB** to the host: power, the on-board J-Link and the Secure + Enclave's UART. +- **User USB (J1)** to the host for SDS recording and playback (optional). +- The camera module the Gen 2 kit ships with, an MT9M114 on the MIPI + connector, and the 480x800 MIPI DSI panel. +- **SW4** on `SEUART` while SETOOLS runs. The application does not use a + UART: its console is a log buffer in the DTCM that the debugger reads. + +## 3. Project and build + +```bash +git clone https://github.com/MatthiasHertelArm/cmsis-executorch-traffic-counter.git +cd cmsis-executorch-traffic-counter +./setup_venv.sh && .venv/bin/python -m pip install ultralytics +.venv/bin/python traffic/make_test_image.py +``` + +`make_test_image.py` writes `traffic/test_image.c`, the image the detector +runs on until the camera delivers (and the only input on the FVP). It is +generated from a COCO photo that is not ours to redistribute, so it is not in +the repository, and the build needs it. The AI layer `ai_layer/` is +committed; regenerate it only after changing `model/traffic.py`. The weights +are in the repository too (`model/yolo26n-noattn-vehicles.pt`): + +```bash +cbuild setup cmsis-executorch.csolution.yml --active AppKit-E7 --packs +.venv/bin/python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml +``` + +Open the folder in VS Code and accept the pack installation +(`PyTorch::ExecuTorch`, `AlifSemiconductor::Ensemble`, `ARM::SDS`, +`Keil::MDK-Middleware`, and `ARM::V2M_MPS3_SSE_300_BSP` for the FVP). In the CMSIS view open **Manage Solution**, choose +the target-type **AppKit-E7** and click **Apply**, then **Build**. From the +command line: + +```bash +cbuild cmsis-executorch.csolution.yml --active AppKit-E7 --packs +``` + +The image is `out/traffic/AppKit-E7/Release/traffic.axf`. + +## 4. Prepare the board once + +The Secure Enclave boots the HP core from a table of contents in MRAM, which +must point at the HP core's MRAM region and carry the E7's own device +configuration (with the E8's, the camera DMA cannot reach its buffers). + +1. SW4 on **SEUART**, PRG USB attached. +2. **Terminal > Run Task > Alif: Install M55_HP debug stubs (AppKit-E7, + single core configuration)**. It installs `.alif/M55_HP_mram_cfg_e7.json` + and `.alif/app-device-config-e7.json` into SETOOLS, selects the E7 with + silicon revision B4 and writes the table. Choose COM port discovery (`-d`) + the first time. If `app-write-mram` gets no answer, press the board's reset + button while it waits. + +`tools/setools_mram.py out/traffic/AppKit-E7/Release/traffic.hex` does the +same and programs the application itself through the Secure Enclave, without +the J-Link. + +## 5. Run and debug + +In the CMSIS view click **Run** or **Debug**: the J-Link loads the image into +MRAM and starts it. The panel shows the camera picture with the line and the +tallies after a few seconds. + +- **Console:** `.venv/bin/python tools/console_log.py out/traffic/AppKit-E7/Release/traffic.axf.map` + prints the `console_log` buffer, with the tallies every 100 frames. +- **Status:** the global `traffic_status` holds the tallies, the frame + counters, the time of each step in microseconds, the camera state, the live + tracks and the latest detections. Writing 1 to `traffic_reset_counts` + zeroes the tallies. +- **The line:** horizontal through the middle by default. The joystick moves + it (left and right a vertical line, up and down a horizontal one) and the + centre button turns it by 90 degrees. The build-time default is + `TRAFFIC_LINE_POS` and `TRAFFIC_LINE_VERTICAL` in `traffic/traffic.cproject.yml`. + +## 6. Without a board: the Corstone-300 FVP + +Choose the target-type **SSE-300-U55** in **Manage Solution**, **Build**, then +**Run** (or **Debug**, which stops at `main`). The application runs the test +image through the detector and the tracker three times, prints the +detections and ends the simulation; the output is in the terminal of the +CMSIS Run task (in the Debug Console when debugging): + +```text +frame 0: 2 vehicles, detect 1203 us (NPU 163 us) + TRUCK 0.65 x1 161 y1 233 x2 293 y2 314 + TRUCK 0.50 x1 335 y1 201 x2 415 y2 363 +... +Test_result: PASS +``` + +From the command line: + +```bash +cbuild cmsis-executorch.csolution.yml --active SSE-300-U55 --packs +FVP_Corstone_SSE-300_Ethos-U55 -f board/Corstone-300/fvp_config.txt -a out/traffic/SSE-300-U55/Release/traffic.axf +``` + +(`.vscode/fvp.sh` in place of the model name on macOS.) The FVP's times are +not the board's: its NPU runs in fast mode. + +## 7. Record and play back (SDS) + +With the application running and the User USB connected, these VS Code tasks +(Terminal > Run Task) drive SDSIO-Server through `traffic/sds_session.py`: + +| Task | Does | +|------|------| +| SDS: record from the camera (USB) | records `CameraIn` (the model inputs) and `Detections` for a number of seconds into `recordings/traffic/` | +| SDS: video to CameraIn stream | turns a video into `recordings/traffic/playback/CameraIn.0.sds` with ffmpeg, letterboxed or cut to fill the square input | +| SDS: play recording to the board (USB) | plays `CameraIn..sds` of a folder into the detector instead of the camera, records the board's detections next to it | +| SDS: check playback against the host model | lists the board's detections next to the float model's on the same inputs | + +`traffic/count_playback.py [--sweep]` runs the tracker's logic on +the PC over the board's detections of a playback and over the float model's, +and shows which line positions the traffic actually crosses. One SDSIO server +owns the USB device at a time: let a run finish or stop it with Ctrl+C +before starting the next. + +## 8. If something does not work + +- **The application never gets past the Secure Enclave handshake** (the log + shows no frames, `SRAM1: power request failed`): the Secure Enclave has + stopped answering. A reset does not help; power-cycle the board (unplug PRG + USB), wait about 40 s, and load again. +- **SETOOLS says "Revision is invalid":** `tools-config -p` reset the + revision to A0. The AppKit-E7 is B4: the task and `tools/setools_mram.py` + pass `-r B4`. +- **The build fails in CMake** (`toolchain.cmake ... could not find requested + file`) after a CMSIS Solution extension update: delete `tmp/AppKit-E7` and + build again. +- **The debugger cannot start its GDB server:** another debug session holds + the port. Stop it, or change the ports in the launch configuration. +- **The first inference after a debugger reset reports error 35:** the NPU + was still busy with the job from before the reset. The loop recovers on its + own. +- **The picture never changes, or the board and its debug port die while the + camera runs:** the table of contents carries another device's + configuration. Repeat step 4. Keep the camera frames and the panel buffers + in SRAM0: neither the camera DMA nor the display controller reaches SRAM1, + and SRAM8 hangs the bus. + +## Licences + +The code is under the Apache License 2.0 ([LICENSE](LICENSE)). The YOLO26n +weights come from Ultralytics and are under the AGPL-3.0: the fine-tuned +checkpoint `model/yolo26n-noattn-vehicles.pt`, its architecture +`model/yolo26n-noattn.yaml`, and the program compiled into `ai_layer/`; +`model/` fetches the COCO-pretrained `yolo26n.pt` with the `ultralytics` +package. `src/LICENSE-ExecuTorch` covers the ExecuTorch sources +(BSD-3-Clause). + +## Read on + +- [documentation/traffic-counter.md](documentation/traffic-counter.md): the + traffic counter in detail (model, training, pipeline, the FVP, memory map, + camera bring-up on the E7, SDS over USB, NPU performance and its PMU + counters). +- [documentation/mlops-flow.md](documentation/mlops-flow.md): the `mlops:` + node, `*.cbuild-mlops.yml` and how the AI layer is made. +- [documentation/pack-provenance.md](documentation/pack-provenance.md): where + the `PyTorch::ExecuTorch` pack comes from. diff --git a/ai_layer/ai_layer.clayer.yml b/ai_layer/ai_layer.clayer.yml new file mode 100644 index 0000000..6c9631a --- /dev/null +++ b/ai_layer/ai_layer.clayer.yml @@ -0,0 +1,28 @@ +# Generated by create_ai_layer.py from cmsis-executorch.cbuild-mlops.yml -- do not edit. +# Re-run `python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml` after changing +# model/model.py or the csolution's mlops: node. +layer: + type: AI + description: YOLO26n vehicle detector of the traffic counter for the Ethos-U55 of the Ensemble E7's M55-HP + + packs: + - pack: PyTorch::ExecuTorch@1.5.1 + + define: + - ET_LOG_ENABLED: 0 + + add-path: + - . + + components: + - component: Machine Learning:ExecuTorch:Runtime + - component: Machine Learning:ExecuTorch:Kernel Utils + - component: Machine Learning:ExecuTorch:Kernel Registration + - component: Machine Learning:ExecuTorch:Backend EthosU + + groups: + - group: TrafficVehicles + files: + - file: ./model_pte.c + - file: ./model_pte.h + - file: ./model_io.h diff --git a/ai_layer/model_io.h b/ai_layer/model_io.h new file mode 100644 index 0000000..d89bf69 --- /dev/null +++ b/ai_layer/model_io.h @@ -0,0 +1,35 @@ +// Generated by create_ai_layer.py -- do not edit. +// Quantized IO of every method in model_pte: shapes, C types and the +// affine quantization q = round(x / SCALE) + ZERO_POINT the CPU applies. +#pragma once + +#define MODEL_DETECT_METHOD "detect" +#define MODEL_DETECT_NUM_INPUTS 1 +#define MODEL_DETECT_NUM_OUTPUTS 2 +#define MODEL_DETECT_INPUT0_NDIM 4 +#define MODEL_DETECT_INPUT0_SHAPE {1, 416, 416, 3} +#define MODEL_DETECT_INPUT0_NUMEL 519168 +#define MODEL_DETECT_INPUT0_CTYPE int8_t +#define MODEL_DETECT_INPUT0_DTYPE_INT8 1 +#define MODEL_DETECT_INPUT0_SCALE 0.003919653594493866f +#define MODEL_DETECT_INPUT0_ZERO_POINT -128 +#define MODEL_DETECT_INPUT0_QMIN -128 +#define MODEL_DETECT_INPUT0_QMAX 127 +#define MODEL_DETECT_OUTPUT0_NDIM 3 +#define MODEL_DETECT_OUTPUT0_SHAPE {1, 3549, 4} +#define MODEL_DETECT_OUTPUT0_NUMEL 14196 +#define MODEL_DETECT_OUTPUT0_CTYPE int8_t +#define MODEL_DETECT_OUTPUT0_DTYPE_INT8 1 +#define MODEL_DETECT_OUTPUT0_SCALE 0.050739891827106476f +#define MODEL_DETECT_OUTPUT0_ZERO_POINT -112 +#define MODEL_DETECT_OUTPUT0_QMIN -128 +#define MODEL_DETECT_OUTPUT0_QMAX 127 +#define MODEL_DETECT_OUTPUT1_NDIM 3 +#define MODEL_DETECT_OUTPUT1_SHAPE {1, 3549, 5} +#define MODEL_DETECT_OUTPUT1_NUMEL 17745 +#define MODEL_DETECT_OUTPUT1_CTYPE int8_t +#define MODEL_DETECT_OUTPUT1_DTYPE_INT8 1 +#define MODEL_DETECT_OUTPUT1_SCALE 0.003001644043251872f +#define MODEL_DETECT_OUTPUT1_ZERO_POINT -128 +#define MODEL_DETECT_OUTPUT1_QMIN -128 +#define MODEL_DETECT_OUTPUT1_QMAX 127 diff --git a/ai_layer/model_pte.c b/ai_layer/model_pte.c new file mode 100644 index 0000000..8dd0f6d --- /dev/null +++ b/ai_layer/model_pte.c @@ -0,0 +1,142325 @@ +// Generated by create_ai_layer.py -- do not edit. +__attribute__((aligned(16))) const unsigned char model_pte[] = { + 0x24, 0x00, 0x00, 0x00, 0x45, 0x54, 0x31, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x18, 0x00, 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0x00, 0x00 +}; +const unsigned long model_pte_size = sizeof(model_pte); diff --git a/ai_layer/model_pte.h b/ai_layer/model_pte.h new file mode 100644 index 0000000..56c31d2 --- /dev/null +++ b/ai_layer/model_pte.h @@ -0,0 +1,10 @@ +// Generated by create_ai_layer.py -- do not edit. +#pragma once +#ifdef __cplusplus +extern "C" { +#endif +extern const unsigned char model_pte[]; +extern const unsigned long model_pte_size; +#ifdef __cplusplus +} +#endif diff --git a/board/AppKit-E7/AppKit-E7.h b/board/AppKit-E7/AppKit-E7.h new file mode 100644 index 0000000..027d8e4 --- /dev/null +++ b/board/AppKit-E7/AppKit-E7.h @@ -0,0 +1,37 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025-2026 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * CMSIS target header of the AppKit-E7 layer: only the USART the Ensemble + * board files name for stdio (the traffic counter's console is a log buffer, + * retarget_stdio_log.c). The pack's AppKit-E7 layer has the full pin-out. + *---------------------------------------------------------------------------*/ + +#ifndef APPKIT_E7_H_ +#define APPKIT_E7_H_ + +#include "Driver_USART.h" + +// CMSIS Driver instances of Board peripherals +#define CMSIS_DRIVER_USART 4 // CMSIS Driver USART instance number (PRG USB, J3) + +// Retarget stdio to CMSIS UART +#define RETARGET_STDIO_UART 4 + +// CMSIS Drivers +extern ARM_DRIVER_USART Driver_USART4; /* PRG USB */ + +#endif /* APPKIT_E7_H_ */ diff --git a/board/AppKit-E7/Board-Traffic.clayer.yml b/board/AppKit-E7/Board-Traffic.clayer.yml new file mode 100644 index 0000000..98a103c --- /dev/null +++ b/board/AppKit-E7/Board-Traffic.clayer.yml @@ -0,0 +1,186 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# Alif Ensemble E7 AppKit (AK-E7-AIML, Gen 2) board bring-up for the traffic +# counter (traffic/traffic.cproject.yml), on the Cortex-M55 high-performance +# (HP) core with its Ethos-U55-256. Derived from the Alif Ensemble E8 board +# layers of the cmsis-executorch example it was forked from: the display +# (CDC200 -> MIPI DSI -> ILI9806E 480x800), the console in a log buffer that +# the debugger reads (SW4 stays on SEUART for the Secure Enclave tools), SDS +# over the User USB, and a scatter file whose code region runs on into the MRAM user +# region for the 2.4 MB YOLO26n program. +# +# What differs from the E8: the NPU is the HP core's Ethos-U55 (ETHOSU55, the +# pack's NPU region settings: command stream and weights through the MRAM +# port, the scratch through the SRAM port); the E7 has no ISP and its CPI has +# no streaming mode, so the camera (the kit's MT9M114 module, 640x480 RGB565 +# over MIPI CSI-2) is captured into buffers the application swaps at each +# VSYNC and scaled on the CPU (traffic/camera.c, traffic/image.c); SRAM1 +# (2.5 MB at 0x08000000) is not contiguous with SRAM0 (4 MB), see +# linker_ac6_traffic.sct.src. +# +# The pack's own AppKit-E7 layer names the MT9M114 sensor too. For an ARX3A0 +# module (560x560 RAW8 Bayer, demosaiced on the CPU) replace the sensor +# component below: traffic/camera.h follows the component. +layer: + type: Board + description: AppKit-E7 board setup for the traffic counter on M55_HP with the Ethos-U55 + for-board: Alif Semiconductor::AppKit-E7-AIML + for-device: Alif Semiconductor::AE722F80F55D5LS:M55_HP + device: :M55_HP + + processor: + trustzone: off + + connections: + - connect: AppKit-E7 Board + provides: + - STDIN + - STDOUT + - STDERR + - Heap: 98304 + + define: + - CMSIS_target_header: \"AppKit-E7.h\" + - ETHOSU55 + # The Ethos-U driver's NPU configuration of the pack's E7 layer: the + # command stream (QCONFIG) and region 0 (the weights, in the MRAM) over the + # NPU's AXI1 port, region 1 (Vela's scratch in the SRAM) over AXI0. + - NPU_QCONFIG: 1 + - NPU_REGIONCFG_0: 1 + - NPU_REGIONCFG_1: 0 + - NPU_REGIONCFG_2: 1 + - AXI_LIMIT0_MEM_TYPE: 3 + - AXI_LIMIT1_MEM_TYPE: 3 + - AXI_LIMIT2_MEM_TYPE: 3 + - AXI_LIMIT3_MEM_TYPE: 3 + # The pack's ILI9806E driver names the backlight pin BOARD_LCD_BL_LED_*, the + # AppKit's board_defs.h BOARD_LCD_BACKLIGHT_*. + - BOARD_LCD_BL_LED_GPIO_PORT: BOARD_LCD_BACKLIGHT_GPIO_PORT + - BOARD_LCD_BL_LED_GPIO_PIN: BOARD_LCD_BACKLIGHT_GPIO_PIN + # The application's ExecuTorch pools, the RTX thread stacks and the two + # frame buffers go into SRAM0 (4 MB, NPU-accessible, behind the D-cache). + - APP_POOL_SECTION: \".bss.ai_pool\" + - APP_HAS_DISPLAY: 1 + - APP_FRAMEBUFFER_SECTION: \".bss.lcd_frame_buf\" + - APP_DISPLAY_WIDTH: 480 + - APP_DISPLAY_HEIGHT: 800 + - APP_THREAD_STACK_SIZE: 0x8000 + # The camera: ARX3A0 over MIPI CSI-2 into the CPI, 560x560 RAW8 Bayer, two + # buffers the application swaps at each VSYNC (traffic/camera.c). The + # Bayer order and the mounting turn are set in traffic/camera.h. + - APP_HAS_CAMERA: 1 + # The panel's MADCTL (0x36) value, written before the video stream starts. + # On this ILI9806E in video mode only bit 0 does anything: it mirrors the + # panel along its long axis (the pack's panel driver sets 0x01, mirrored); + # bits 7 and 6 are ignored. 0x00 shows the frame buffer as drawn. + - TRAFFIC_LCD_MADCTL: 0x00 + # The panel hangs upside down: everything drawn into the panel buffer + # (picture, boxes, line, text) goes to the opposite x and y (traffic/image.c). + - IMAGE_PANEL_TURN_180: 1 + # SDS recording and playback over the User USB connector. The MDK USB + # middleware takes the driver index and the speed from these (the SDS USB + # layer expects a board layer to provide them): Driver_USBD0, high-speed. + - APP_HAS_SDS: 1 + - APP_HAS_JOYSTICK: 1 # the line moves with the joystick (traffic/joystick.c) + # The NPU scratch in SRAM1 so that both panel buffers fit SRAM0 (the + # CDC200 cannot read SRAM1, and SRAM8 hangs the bus). + - APP_TEMP_POOL_SECTION: \".bss.sram1\" + - CMSIS_DRIVER_USBD: 0 + - CMSIS_DRIVER_USBD_HS: 1 + + packs: + - pack: AlifSemiconductor::Ensemble@^2.2.0-0 + - pack: ARM::CMSIS@^6.2.0 + - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::ethos-u-core-driver@^1.26.2 + - pack: ARM::CMSIS-RTX@^5.9.1 + - pack: ARM::SDS@^3.1.0 + - pack: Keil::MDK-Middleware@^8.3.0 + + misc: + - for-compiler: AC6 + Link: + - '--diag_suppress 6312,6314,6329,6848' + + components: + - component: Device:Startup + + - component: BSP:Board Config + - component: BSP:AppKit Config&AppKit-E7-AIML + + - component: CMSIS:CORE + + - component: CMSIS Driver:USART + # The ILI9806E panel driver and the camera sensor drive their reset, + # backlight and power pins through the CMSIS GPIO driver. + - component: CMSIS Driver:GPIO + define: + - CMSIS_GPIO_DISABLE_EVENTS + + # RTX5: app_main runs in an RTX thread (main.c); the SDS Stream component needs it too. + - component: CMSIS:RTOS2:Keil RTX5&Source + - component: CMSIS:OS Tick:SysTick + # SDS data streams over the SoC's USB (the "User USB" connector J1, a + # custom-class bulk device, MDK USB middleware on the pack's USB device + # driver), read and written by SDSIO-Server in its usb mode. The RTT + # channel moved 100 kB/s at best and the J-Link link broke off. + - component: SDS:Stream&CMSIS-RTOS2 + - component: SDS:IO:USB&MDK USB + - component: USB&MDK:CORE + - component: USB&MDK:Device + - component: USB&MDK:Device:Custom Class + - component: CMSIS Driver:USB Device + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:Custom + - component: CMSIS-Compiler:STDIN:Custom + - component: CMSIS-Compiler:STDOUT:Custom + + - component: Device:SOC Peripherals:MHU + - component: Device:SOC Peripherals:PINCONF + + # Display: CDC200 controller -> MIPI DSI -> ILI9806E panel (the pack's + # RTE_Device.h in this layer configures RGB888, 480x800, 60 fps). + - component: BSP:External peripherals:ILI9806E LCD panel + - component: Device:SOC Peripherals:CDC + - component: Device:SOC Peripherals:GPIO + - component: Device:SOC Peripherals:MIPI DSI + - component: Device:SOC Peripherals:MIPI DSI CSI2 DPHY + + # Camera: the kit's MT9M114 module (I2C1 for its registers, at 0x5D over + # MIPI) -> MIPI CSI-2 -> CPI -> SRAM1, 640x480 RGB565 from the sensor's ISP + # (RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 3 in RTE_Device.h; the pack's + # own AppKit-E7 layer uses this sensor). For an ARX3A0 module use the + # ARX3A0 component: traffic/camera.h follows the component. + - component: BSP:External peripherals:CAMERA Sensor MT9M114 + - component: CMSIS Driver:I2C + - component: Device:SOC Peripherals:CPI + - component: Device:SOC Peripherals:MIPI CSI2 + + - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + + - component: Services:Secure Enclave:core&Source + - component: Services:Secure Enclave:Initialization Helper&Source + + groups: + - group: Board + files: + - file: ./main.c + - file: ./main.h + - file: ./AppKit-E7.h + - file: ./ethos_setup.c + # The console is a log buffer in the DTCM (console_log) that the debugger reads. + - file: ./retarget_stdio_log.c + - file: ./board_display.c + - file: ./board_display.h + + - group: Ethos Interface + files: + - file: ./ethosu_cb_dcache.c + + # AC6 only: the MRAM layout of the traffic counter (linker_ac6_traffic.sct.src). + linker: + - regions: ./RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h + - script: ./linker_ac6_traffic.sct.src + for-compiler: AC6 diff --git a/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h new file mode 100644 index 0000000..9b452e7 --- /dev/null +++ b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h @@ -0,0 +1,2401 @@ +/* +* Copyright (C) 2026 Alif Semiconductor - All Rights Reserved. +* Use, distribution and modification of this code is permitted under the +* terms stated in the Alif Semiconductor Software License Agreement +* +* You should have received a copy of the Alif Semiconductor Software +* License Agreement with this file. If not, please write to: +* https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ +*/ +/****************************************************************************** +* @file board_defs.h +* @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ +* @version v1.0.1 +* @date 2026-2-19 +* @brief Board info/settings for "AI/ML AppKit Gen 2 (AK-E7-AIML)" project +* with AE722F80F55D5LS +* @bug None. +* @note To modify this file manually, take care to modify pins.h and gpios.h +* accordingly when required. +******************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + +// Board peripheral instances +// "ADC12A" ADC12 instance number <0-2> +#define BOARD_ADC12A_ADC12_INSTANCE 0 + +// "ADC12B" ADC12 instance number <0-2> +#define BOARD_ADC12B_ADC12_INSTANCE 1 + +// "ADC12C" ADC12 instance number <0-2> +#define BOARD_ADC12C_ADC12_INSTANCE 2 + +// ADC24 module enabled flag +#define BOARD_ADC24_ENABLED 1 +// + +// CANFD module enabled flag +#define BOARD_CANFD_ENABLED 1 +// "CAN Transceiver" on CANFD presence flag +#define BOARD_CANFD_CAN_TRANSCEIVER_PRESENT 1 +// +// + +// "CMPA" CMP instance number <0-4> +#define BOARD_CMPA_CMP_INSTANCE 0 + +// "CMPB" CMP instance number <0-4> +#define BOARD_CMPB_CMP_INSTANCE 1 + +// "CMPC" CMP instance number <0-4> +#define BOARD_CMPC_CMP_INSTANCE 2 + +// "CMPD" CMP instance number <0-4> +#define BOARD_CMPD_CMP_INSTANCE 3 + +// CSI module enabled flag +#define BOARD_CSI_ENABLED 1 +// "ARX3A0" on CSI presence flag +#define BOARD_CSI_ARX3A0_PRESENT 1 +// +// "AR0144" on CSI presence flag +#define BOARD_CSI_AR0144_PRESENT 1 +// +// + +// DSI module enabled flag +#define BOARD_DSI_ENABLED 1 +// "ILI9806" on DSI presence flag +#define BOARD_DSI_ILI9806_PRESENT 1 +// +// + +// ETH module enabled flag +#define BOARD_ETH_ENABLED 1 +// "RTL8201" on ETH presence flag +#define BOARD_ETH_RTL8201_PRESENT 1 +// +// + +// "Clickboard" I2C instance number <0-3> +#define BOARD_CLICKBOARD_I2C_INSTANCE 0 + +// "Slave" I2C instance number <0-3> +#define BOARD_SLAVE_I2C_INSTANCE 0 + +// "Camera" I2C instance number <0-3> +#define BOARD_CAMERA_I2C_INSTANCE 1 + +// "GT911 Touchscreen" I2C instance number <0-3> +#define BOARD_GT911_TOUCHSCREEN_I2C_INSTANCE 1 + +// "Master" I2C instance number <0-3> +#define BOARD_MASTER_I2C_INSTANCE 1 + +// LPI2C0 module enabled flag +#define BOARD_LPI2C0_ENABLED 1 + +// "FLEXIO" on LPI2C0 presence flag +#define BOARD_LPI2C0_USE_FLEXIO_PINS 0 + +// "MIC Input" I2S instance number <0-3> +#define BOARD_MIC_INPUT_I2S_INSTANCE 3 + +// LPSPI module enabled flag +#define BOARD_LPSPI_ENABLED 1 + +// SPI salve instance number <0-3> +#define BOARD_SLAVE_SPI_INSTANCE 1 + +// SPI master instance number <0-3> +#define BOARD_MASTER_SPI_INSTANCE 1 + +// LPUART module enabled flag +#define BOARD_LPUART_ENABLED 1 + +// I3C module enabled flag +#define BOARD_I3C_ENABLED 1 + +// "FLEXIO" on I3C presence flag +#define BOARD_I3C_FLEXIO_PRESENT 1 +// "ICM42670 IMU" on I3C presence flag +#define BOARD_I3C_ICM42670_IMU_PRESENT 1 +// +// "BMI323 IMU" on I3C presence flag +#define BOARD_I3C_BMI323_IMU_PRESENT 1 +// +// "pin header" on I3C presence flag +#define BOARD_I3C_PIN_HEADER_PRESENT 1 +// +// + +// JTAG module enabled flag +#define BOARD_JTAG_ENABLED 1 +// + +// LPCPI module enabled flag +#define BOARD_LPCPI_ENABLED 1 +// + +// LPGPIO module enabled flag +#define BOARD_LPGPIO_ENABLED 1 +// + +// LPI2S module enabled flag +#define BOARD_LPI2S_ENABLED 0 +// + +// LPPDM module enabled flag +#define BOARD_LPPDM_ENABLED 1 +// + +// MISC module enabled flag +#define BOARD_MISC_ENABLED 1 +// + +// "ISSI Flash" OSPI instance number <1> +#define BOARD_ISSI_FLASH_OSPI_INSTANCE 1 + +// PDM module enabled flag +#define BOARD_PDM_ENABLED 1 +// "PDM MIC" on PDM presence flag +#define BOARD_PDM_PDM_MIC_PRESENT 1 +// +// + +// "Encoder" UTIMER instance number <12-15> +#define BOARD_ENCODER_UTIMER_INSTANCE 12 + +// SDMMC module enabled flag +#define BOARD_SDMMC_ENABLED 1 +// "SDCARD" on SDMMC presence flag +#define BOARD_SDMMC_SDCARD_PRESENT 1 +// +// + +// SEUART module enabled flag +#define BOARD_SEUART_ENABLED 1 +// + +// "Clickboard" UART instance number <0-7> +#define BOARD_CLICKBOARD_UART_INSTANCE 0 + +// "UARTA" UART instance number <0-7> +#define BOARD_UARTA_UART_INSTANCE 2 + +// "UARTB" UART instance number <0-7> +#define BOARD_UARTB_UART_INSTANCE 4 + +// USB module enabled flag +#define BOARD_USB_ENABLED 1 +// "Device Role" on USB presence flag +#define BOARD_USB_DEVICE_ROLE_PRESENT 1 +// +// + +// "Basic Mode" UTIMER instance number <0-12> +#define BOARD_BASIC_MODE_UTIMER_INSTANCE 0 + +// "Buffer Mode" UTIMER instance number <0-12> +#define BOARD_BUFFER_MODE_UTIMER_INSTANCE 1 + +// "Capture Mode" UTIMER instance number <0-12> +#define BOARD_CAPTURE_MODE_UTIMER_INSTANCE 4 + +// "Compare Mode" UTIMER instance number <0-12> +#define BOARD_COMPARE_MODE_UTIMER_INSTANCE 5 + +// "Trigger Mode" UTIMER instance number <0-12> +#define BOARD_TRIGGER_MODE_UTIMER_INSTANCE 3 + +// "Clickboard PWM" UTIMER instance number <0-12> +#define BOARD_CLICKBOARD_PWM_UTIMER_INSTANCE 3 + +// Utimer 250ms counter value +#define BOARD_UTIMER_250_MILLI_SEC_COUNTER_VALUE 100000000 + +// Utimer 500ms counter value +#define BOARD_UTIMER_500_MILLI_SEC_COUNTER_VALUE 200000000 + +// Utimer 750ms counter value +#define BOARD_UTIMER_750_MILLI_SEC_COUNTER_VALUE 300000000 + +// Utimer 1000ms counter value +#define BOARD_UTIMER_1000_MILLI_SEC_COUNTER_VALUE 400000000 + +// Utimer 1500ms counter value +#define BOARD_UTIMER_1500_MILLI_SEC_COUNTER_VALUE 600000000 + +// LED PWM utimer max counter value +#define BOARD_LED_PWM_UT_MAX_COUNTER_VALUE 240000 + +// "RED_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_RED_LED_UTIMER_COUNTER_TYPE 1 + +// "GREEN_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_GREEN_LED_UTIMER_COUNTER_TYPE 0 + +// "BLUE_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_BLUE_LED_UTIMER_COUNTER_TYPE 0 + +// UTIMER channel red LED instance number <9> +#define BOARD_RED_LED_UTIMER_INSTANCE 9 + +// UTIMER channel green LED instance number <10> +#define BOARD_GREEN_LED_UTIMER_INSTANCE 10 + +// UTIMER channel blue LED instance number <8> +#define BOARD_BLUE_LED_UTIMER_INSTANCE 8 + +// CMP external trigger UTIMER channel instance number <0-12> +#define BOARD_CMP_EXT_TRIGGER_UTIMER_INSTANCE 0 + +// +// Miscellaneous +// Onboard LEDs +// Sets the #define BOARD_LED_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LED_COUNT 0 + +// Onboard RGB LEDs +// Sets the #define BOARD_LEDRGB_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LEDRGB_COUNT 2 + +// Onboard Push-buttons +// Sets the #define BOARD_BUTTON_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_BUTTON_COUNT 5 + +// Onboard Config Switches or Jumpers +// Sets the #define BOARD_CONFIG_JUMPER_COUNT in the board_def.h file exported from the +// Conductor tool. +#define BOARD_CONFIG_JUMPER_COUNT 0 + +// Onboard Switching Devices +// Sets the #define BOARD_SWITCH_OUTPUT_COUNT in the board_def.h file exported from the +// Conductor tool. These include relays, solid state relays, transistors, optocopulers, etc. +#define BOARD_SWITCH_OUTPUT_COUNT 0 + +// OSPI0 Bus Speed +// Selects OSPI0 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI0_BUS_SPEED 100000000 + +// OSPI1 Bus Speed +// Selects OSPI1 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI1_BUS_SPEED 100000000 + +// OSPI0 onboard memory size +#define BOARD_OSPI0_MEM_SIZE 33554432 + +// OSPI1 onboard memory size +#define BOARD_OSPI1_MEM_SIZE 67108864 + +// +// GPIO port/pin numbers, analog instance/input numbers, etc. +// FLEX IO pins supply voltage <0=> 3.3 V <1=> 1.8 V +// Make sure this setting corresponds to the VDD_IO_FLEX pin voltage. If the VDD_IO_FLEX pin is +// connected to a 3.3 V supply, do not change the value of the GPIO_CNTL register to command 1.8-V +// operation mode! +#define FLEX_IO_VOLTAGE_1V8 1 + +// "CLICKBOARD_ANA" ADC12 instance number <0=> ADC120 <1=> ADC121 <2=> ADC122 +#define BOARD_CLICKBOARD_ANA_ADC12_INSTANCE 1 +// "CLICKBOARD_ANA" ADC12 input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 <4=> IN4 <5=> IN5 +#define BOARD_CLICKBOARD_ANA_ADC12_INPUT 0 + +// "CLICKBOARD_ANA" ADC24 negative input number <0=> IN0_N <1=> IN1_N <2=> IN2_N <3=> IN3_N +// WARNING: This option does not change the positive input pin automatically! +#define BOARD_CLICKBOARD_ANA_ADC24_INPUT 2 + +// "CLICKBOARD_ANA" CMP instance number <0=> CMP0 <1=> CMP1 <2=> CMP2 <3=> CMP3 +#define BOARD_CLICKBOARD_ANA_CMP_INSTANCE 0 +// "CLICKBOARD_ANA" CMP input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 +#define BOARD_CLICKBOARD_ANA_CMP_INPUT 1 + +// "POTENTIOMETER" ADC12 instance number <0=> ADC120 <1=> ADC121 <2=> ADC122 +#define BOARD_POTENTIOMETER_ADC12_INSTANCE 1 +// "POTENTIOMETER" ADC12 input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 <4=> IN4 <5=> IN5 +#define BOARD_POTENTIOMETER_ADC12_INPUT 1 + +// "POTENTIOMETER" ADC24 negative input number <0=> IN0_N <1=> IN1_N <2=> IN2_N <3=> IN3_N +// WARNING: This option does not change the positive input pin automatically! +#define BOARD_POTENTIOMETER_ADC24_INPUT 3 + +// "POTENTIOMETER" CMP instance number <0=> CMP0 <1=> CMP1 <2=> CMP2 <3=> CMP3 +#define BOARD_POTENTIOMETER_CMP_INSTANCE 0 +// "POTENTIOMETER" CMP input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 +#define BOARD_POTENTIOMETER_CMP_INPUT 0 + +// "CMP0_POS_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP0_POS_INPUT_GPIO_PORT 0 +// "CMP0_POS_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CMP0_POS_INPUT_GPIO_PIN 0 +// "CMP0_POS_INPUT" GPIO pin alternate function <0-7> +#define BOARD_CMP0_POS_INPUT_ALTERNATE_FUNCTION 7 + +// "CMP_NEG_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP_NEG_INPUT_GPIO_PORT 2 +// "CMP_NEG_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CMP_NEG_INPUT_GPIO_PIN 0 +// "CMP_NEG_INPUT" GPIO pin alternate function <0-7> +#define BOARD_CMP_NEG_INPUT_ALTERNATE_FUNCTION 7 + +// "CMP1_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP1_OUT_GPIO_PORT 14 +// "CMP1_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP1_OUT_GPIO_PIN 6 +// "CMP1_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP1_OUT_ALTERNATE_FUNCTION 1 + +// "CMP0_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP0_OUT_GPIO_PORT 14 +// "CMP0_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP0_OUT_GPIO_PIN 7 +// "CMP0_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP0_OUT_ALTERNATE_FUNCTION 1 + +// "CMP3_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP3_OUT_GPIO_PORT 14 +// "CMP3_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP3_OUT_GPIO_PIN 4 +// "CMP3_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP3_OUT_ALTERNATE_FUNCTION 1 + +// "CMP2_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP2_OUT_GPIO_PORT 14 +// "CMP2_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP2_OUT_GPIO_PIN 5 +// "CMP2_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP2_OUT_ALTERNATE_FUNCTION 1 + +// "LPCMP_POS_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCMP_POS_INPUT_GPIO_PORT 2 +// "LPCMP_POS_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCMP_POS_INPUT_GPIO_PIN 4 +// "LPCMP_POS_INPUT" GPIO pin alternate function <0-7> +#define BOARD_LPCMP_POS_INPUT_ALTERNATE_FUNCTION 7 + +// "LPCMP_NEG_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCMP_NEG_INPUT_GPIO_PORT 2 +// "LPCMP_NEG_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCMP_NEG_INPUT_GPIO_PIN 0 +// "LPCMP_NEG_INPUT" GPIO pin alternate function <0-7> +#define BOARD_LPCMP_NEG_INPUT_ALTERNATE_FUNCTION 7 + +// ADC12 instance <0=>0 <0=>1 <0=>2 +#define BOARD_ADC12_INSTANCE 2 + +// "ADC12_CH0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH0_GPIO_PORT 1 +// "ADC12_CH0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH0_GPIO_PIN 4 + +// "ADC12_CH1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH1_GPIO_PORT 1 +// "ADC12_CH1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH1_GPIO_PIN 5 + +// "ADC12_CH2" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH2_GPIO_PORT 1 +// "ADC12_CH2" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH2_GPIO_PIN 6 + +// "ADC12_CH3" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH3_GPIO_PORT 1 +// "ADC12_CH3" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH3_GPIO_PIN 7 + +// "ADC12_CH4" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH4_GPIO_PORT 2 +// "ADC12_CH4" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH4_GPIO_PIN 0 + +// "ADC12_CH5" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH5_GPIO_PORT 2 +// "ADC12_CH5" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH5_GPIO_PIN 1 + +// "ADC24_CH0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH0_POS_GPIO_PORT 0 +// "ADC24_CH0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH0_POS_GPIO_PIN 0 + +// "ADC24_CH0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH0_NEG_GPIO_PORT 0 +// "ADC24_CH0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH0_NEG_GPIO_PIN 4 + +// "ADC24_CH1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH1_POS_GPIO_PORT 0 +// "ADC24_CH1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH1_POS_GPIO_PIN 1 + +// "ADC24_CH1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH1_NEG_GPIO_PORT 0 +// "ADC24_CH1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH1_NEG_GPIO_PIN 5 + +// "ADC24_CH2" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH2_POS_GPIO_PORT 0 +// "ADC24_CH2" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH2_POS_GPIO_PIN 2 + +// "ADC24_CH2" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH2_NEG_GPIO_PORT 0 +// "ADC24_CH2" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH2_NEG_GPIO_PIN 6 + +// "ADC24_CH3" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH3_POS_GPIO_PORT 0 +// "ADC24_CH3" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH3_POS_GPIO_PIN 3 + +// "ADC24_CH3" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH3_NEG_GPIO_PORT 0 +// "ADC24_CH3" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH3_NEG_GPIO_PIN 7 + +// "CLICKBOARD_ANA" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC_CLICKBOARD_ANA_GPIO_PORT 0 +// "CLICKBOARD_ANA" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_ADC_CLICKBOARD_ANA_GPIO_PIN 6 + +// "DAC120_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC120_OUT_GPIO_PORT 2 +// "DAC120_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_DAC120_OUT_GPIO_PIN 2 +// "DAC120_OUT" GPIO pin alternate function <0-7> +#define BOARD_DAC120_ALTERNATE_FUNCTION 7 + +// "DAC121_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC121_OUT_GPIO_PORT 2 +// "DAC121_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_DAC121_OUT_GPIO_PIN 3 +// "LPCMP_NEG_INPUT" GPIO pin alternate function <0-7> +#define BOARD_DAC121_ALTERNATE_FUNCTION 7 + +// "SD_CARD_DETECT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CARD_DETECT_GPIO_PORT 3 +// "SD_CARD_DETECT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SD_CARD_DETECT_GPIO_PIN 3 + +// "SD_CMD_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CMD_A_GPIO_PORT 7 +// "SD_CMD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CMD_A_GPIO_PIN 0 +// "SD_CMD_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CMD_ALTERNATE_FUNCTION 6 + +// "SD_CLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CLK_A_GPIO_PORT 7 +// "SD_CLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CLK_A_GPIO_PIN 1 +// "SD_CLK_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CLK_ALTERNATE_FUNCTION 6 + +// "SD_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D0_A_GPIO_PORT 5 +// "SD_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D0_A_GPIO_PIN 0 +// "SD_D0_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D0_ALTERNATE_FUNCTION 7 + +// "SD_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D1_A_GPIO_PORT 5 +// "SD_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D1_A_GPIO_PIN 1 +// "SD_D1_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D1_ALTERNATE_FUNCTION 7 + +// "SD_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D2_A_GPIO_PORT 5 +// "SD_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D2_A_GPIO_PIN 2 +// "SD_D2_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D2_ALTERNATE_FUNCTION 7 + +// "SD_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D3_A_GPIO_PORT 5 +// "SD_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D3_A_GPIO_PIN 3 +// "SD_D3_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D3_ALTERNATE_FUNCTION 6 + +// "SD_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D4_A_GPIO_PORT 5 +// "SD_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D4_A_GPIO_PIN 4 + +// "SD_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D5_A_GPIO_PORT 5 +// "SD_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D5_A_GPIO_PIN 5 + +// "SD_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D6_A_GPIO_PORT 5 +// "SD_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D6_A_GPIO_PIN 6 + +// "SD_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D7_A_GPIO_PORT 5 +// "SD_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D7_A_GPIO_PIN 7 + +// "I2C1_SDA_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C1_SDA_C_GPIO_PORT 7 +// "I2C1_SDA_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C1_SDA_C_GPIO_PIN 2 + +// "I2C1_SCL_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C1_SCL_C_GPIO_PORT 7 +// "I2C1_SCL_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C1_SCL_C_GPIO_PIN 3 + +// "LPI2S_SDO_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2S_SDO_C_GPIO_PORT 13 +// "LPI2S_SDO_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2S_SDO_C_GPIO_PIN 5 + +// "LPI2S_WS_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2S_WS_C_GPIO_PORT 13 +// "LPI2S_WS_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPI2S_WS_C_GPIO_PIN 7 + +// "LPI2S_SCLK_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2S_SCLK_C_GPIO_PORT 13 +// "LPI2S_SCLK_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2S_SCLK_C_GPIO_PIN 6 + +// "I2S3_WS_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S3_WS_B_GPIO_PORT 8 +// "I2S3_WS_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S3_WS_B_GPIO_PIN 7 + +// "I2S3_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S3_SCLK_B_GPIO_PORT 8 +// "I2S3_SCLK_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_I2S3_SCLK_B_GPIO_PIN 6 + +// "I2S3_SDI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S3_SDI_B_GPIO_PORT 9 +// "I2S3_SDI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S3_SDI_B_GPIO_PIN 0 + +// "I2S1_SDO_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S1_SDO_GPIO_PORT 3 +// "I2S1_SDO_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S1_SDO_GPIO_PIN 3 + +// "I2S1_WS_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S1_WS_GPIO_PORT 4 +// "I2S1_WS_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S1_WS_GPIO_PIN 0 + +// "I2S1_SCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S1_SCLK_GPIO_PORT 3 +// "I2S1_SCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_I2S1_SCLK_GPIO_PIN 4 + +// "LPPDM_TEST" LPPDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_LPPDM_TEST_LPPDM_INPUT 1 + +// "LPPDM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D0_GPIO_PORT 3 +// "LPPDM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D0_GPIO_PIN 5 +// "LPPDM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D0_ALTERNATE_FUNCTION 3 + +// "LPPDM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D1_GPIO_PORT 3 +// "LPPDM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D1_GPIO_PIN 7 +// "LPPDM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D1_ALTERNATE_FUNCTION 3 + +// "LPPDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D2_GPIO_PORT 11 +// "LPPDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D2_GPIO_PIN 6 +// "LPPDM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D2_ALTERNATE_FUNCTION 3 + +// "LPPDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D3_GPIO_PORT 7 +// "LPPDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D3_GPIO_PIN 7 +// "LPPDM_D3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D3_ALTERNATE_FUNCTION 4 + +// "LPPDM_C0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C0_GPIO_PORT 3 +// "LPPDM_C0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C0_GPIO_PIN 4 +// "LPPDM_C0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C0_ALTERNATE_FUNCTION 3 + +// "LPPDM_C1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C1_GPIO_PORT 3 +// "LPPDM_C1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C1_GPIO_PIN 6 +// "LPPDM_C1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C1_ALTERNATE_FUNCTION 3 + +// "LPPDM_C2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C2_GPIO_PORT 11 +// "LPPDM_C2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C2_GPIO_PIN 2 +// "LPPDM_C2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C2_ALTERNATE_FUNCTION 3 + +// "LPPDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C3_GPIO_PORT 7 +// "LPPDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C3_GPIO_PIN 6 +// "LPPDM_C3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C3_ALTERNATE_FUNCTION 4 + +// "PDM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D0_A_GPIO_PORT 0 +// "PDM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D0_A_GPIO_PIN 4 + +// "PDM_D1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D1_C_GPIO_PORT 6 +// "PDM_D1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D1_C_GPIO_PIN 2 + +// "PDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D2_B_GPIO_PORT 5 +// "PDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D2_B_GPIO_PIN 4 + +// "PDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D3_A_GPIO_PORT 5 +// "PDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D3_A_GPIO_PIN 1 + +// "PDM_C0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C0_A_GPIO_PORT 0 +// "PDM_C0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C0_A_GPIO_PIN 5 + +// "PDM_C1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C1_C_GPIO_PORT 6 +// "PDM_C1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C1_C_GPIO_PIN 3 + +// "PDM_C2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C2_A_GPIO_PORT 6 +// "PDM_C2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C2_A_GPIO_PIN 7 + +// "PDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C3_A_GPIO_PORT 5 +// "PDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C3_A_GPIO_PIN 2 + +// "TOUCH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_RESET_GPIO_PORT 4 +// "TOUCH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_TOUCH_RESET_GPIO_PIN 0 + +// "UT_TRIGGER_MODE_GPO0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_GPO0_GPIO_PORT 3 +// "UT_TRIGGER_MODE_GPO0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_GPO0_GPIO_PIN 5 + +// "UTIMER_GPO1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_GPO1_GPIO_PORT 3 +// "UTIMER_GPO1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_GPO1_GPIO_PIN 6 + +// "UT_CAPTURE_MODE_GPO0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_GPO0_GPIO_PORT 3 +// "UT_CAPTURE_MODE_GPO0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_GPO0_GPIO_PIN 3 + +// "UT_CAPTURE_MODE_GPO1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_GPO1_GPIO_PORT 3 +// "UT_CAPTURE_MODE_GPO1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_GPO1_GPIO_PIN 4 + +// "UT_TRIGGER_MODE_T0_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_T0_GPO_GPIO_PORT 0 +// "UT_TRIGGER_MODE_T0_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_T0_GPO_GPIO_PIN 6 +// "UT_TRIGGER_MODE_T0_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_TRIGGER_MODE_T0_GPO_ALTERNATE_FUNCTION 5 + +// "UT_TRIGGER_MODE_T1_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_T1_GPO_GPIO_PORT 0 +// "UT_TRIGGER_MODE_T1_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_T1_GPO_GPIO_PIN 7 +// "UT_TRIGGER_MODE_T1_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_TRIGGER_MODE_T1_GPO_ALTERNATE_FUNCTION 5 + +// "UT_CAPTURE_MODE_T0_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_T0_GPO_GPIO_PORT 1 +// "UT_CAPTURE_MODE_T0_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_T0_GPO_GPIO_PIN 0 +// "UT_CAPTURE_MODE_T0_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_CAPTURE_MODE_T0_GPO_ALTERNATE_FUNCTION 4 + +// "UT_CAPTURE_MODE_T1_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_T1_GPO_GPIO_PORT 1 +// "UT_CAPTURE_MODE_T1_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_T1_GPO_GPIO_PIN 1 +// "UT_CAPTURE_MODE_T1_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_CAPTURE_MODE_T1_GPO_ALTERNATE_FUNCTION 4 + +// "UT_COMPARE_MODE_T0_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_COMPARE_MODE_T0_GPO_GPIO_PORT 1 +// "UT_COMPARE_MODE_T0_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_COMPARE_MODE_T0_GPO_GPIO_PIN 2 +// "UT_COMPARE_MODE_T0_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_COMPARE_MODE_T0_GPO_ALTERNATE_FUNCTION 4 + +// "QEC0_X_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC0_X_B_GPIO_PORT 8 +// "QEC0_X_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC0_X_B_GPIO_PIN 4 + +// "QEC0_Y_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC0_Y_B_GPIO_PORT 8 +// "QEC0_Y_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC0_Y_B_GPIO_PIN 5 + +// "QEC0_Z_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC0_Z_B_GPIO_PORT 8 +// "QEC0_Z_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC0_Z_B_GPIO_PIN 6 + +// "QEC_X_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC_X_GPO_GPIO_PORT 1 +// "QEC0_X_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC_X_GPO_GPIO_PIN 0 + +// "QEC_Y_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC_Y_GPO_GPIO_PORT 1 +// "QEC_Y_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC_Y_GPO_GPIO_PIN 1 + +// "QEC_Z_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC_Z_GPO_GPIO_PORT 1 +// "QEC_Z_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC_Z_GPO_GPIO_PIN 2 + +// "PDM_MIC" PDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_PDM_MIC_PDM_INPUT 2 + +// "LCD_BACKLIGHT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_BACKLIGHT_GPIO_PORT 6 +// "LCD_BACKLIGHT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 1 + +// "LEDRGB1_R" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB1_R_GPIO_PORT 6 +// "LEDRGB1_R" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB1_R_GPIO_PIN 2 +// "LEDRGB1_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB1_R_ALTERNATE_FUNCTION 0 + +// "LEDRGB1_G" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB1_G_GPIO_PORT 6 +// "LEDRGB1_G" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB1_G_GPIO_PIN 5 +// "LEDRGB1_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB1_G_ALTERNATE_FUNCTION 0 + +// "LEDRGB1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB1_B_GPIO_PORT 6 +// "LEDRGB1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB1_B_GPIO_PIN 6 +// "LEDRGB1_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB1_B_ALTERNATE_FUNCTION 0 + +// "CAN_RXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_RXD_GPIO_PORT 7 +// "CAN_RXD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_RXD_GPIO_PIN 0 +// "CAN_RXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_RXD_ALTERNATE_FUNCTION 7 + +// "CAN_TXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_TXD_GPIO_PORT 7 +// "CAN_TXD" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_TXD_GPIO_PIN 1 +// "CAN_TXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_TXD_ALTERNATE_FUNCTION 7 + +// "CAN_STBY" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_STBY_GPIO_PORT 7 +// "CAN_STBY" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_STBY_GPIO_PIN 3 +// "CAN_STBY" GPIO pin alternate function <0-7> +#define BOARD_CAN_STBY_ALTERNATE_FUNCTION 7 + +// "CAM_XVCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_XVCLK_A_GPIO_PORT 0 +// "CAM_XVCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_XVCLK_A_GPIO_PIN 3 + +// "CAMERA_POWER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_POWER_GPIO_PORT 7 +// "CAMERA_POWER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_POWER_GPIO_PIN 5 + +// "I2C1_SDA_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SDA_GPIO_PORT 7 +// "I2C1_SDA_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SDA_GPIO_PIN 2 +// "I2C1_SDA_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SDA_ALTERNATE_FUNCTION 5 + +// "I2C1_SCL_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SCL_GPIO_PORT 7 +// "I2C1_SCL_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SCL_GPIO_PIN 3 +// "I2C1_SCL_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SCL_ALTERNATE_FUNCTION 5 + +// "CAM_HSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_HSYNC_GPIO_PORT 0 +// "CAM_HSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_HSYNC_GPIO_PIN 0 +// "CAM_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_HSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_VSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_VSYNC_GPIO_PORT 0 +// "CAM_VSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_VSYNC_GPIO_PIN 1 +// "CAM_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_VSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_PCLK_GPIO_PORT 0 +// "CAM_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_PCLK_GPIO_PIN 2 +// "CAM_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_PCLK_ALTERNATE_FUNCTION 6 + +// "CAM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D0_GPIO_PORT 8 +// "CAM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D0_GPIO_PIN 0 +// "CAM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D0_ALTERNATE_FUNCTION 7 + +// "CAM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D1_GPIO_PORT 8 +// "CAM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D1_GPIO_PIN 1 +// "CAM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D1_ALTERNATE_FUNCTION 6 + +// "CAM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D2_GPIO_PORT 8 +// "CAM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D2_GPIO_PIN 2 +// "CAM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D2_ALTERNATE_FUNCTION 7 + +// "CAM_D3_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D3_GPIO_PORT 8 +// "CAM_D3_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D3_GPIO_PIN 3 +// "CAM_D3_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D3_ALTERNATE_FUNCTION 7 + +// "CAM_D4_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D4_GPIO_PORT 8 +// "CAM_D4_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D4_GPIO_PIN 4 +// "CAM_D4_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D4_ALTERNATE_FUNCTION 7 + +// "CAM_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D5_GPIO_PORT 8 +// "CAM_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D5_GPIO_PIN 5 +// "CAM_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D5_ALTERNATE_FUNCTION 7 + +// "CAM_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D6_GPIO_PORT 8 +// "CAM_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D6_GPIO_PIN 6 +// "CAM_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D6_ALTERNATE_FUNCTION 7 + +// "CAM_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D7_GPIO_PORT 8 +// "CAM_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D7_GPIO_PIN 7 +// "CAM_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D7_ALTERNATE_FUNCTION 7 + +// "LPCAM_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_HSYNC_GPIO_PORT 0 +// "LPCAM_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_HSYNC_GPIO_PIN 0 +// "LPCAM_HSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_HSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_VSYNC_GPIO_PORT 0 +// "LPCAM_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_VSYNC_GPIO_PIN 1 +// "LPCAM_VSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_VSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_PCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_PCLK_GPIO_PORT 0 +// "LPCAM_PCLK_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_PCLK_GPIO_PIN 2 +// "LPCAM_PCLK_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_PCLK_ALTERNATE_FUNCTION 5 + +// "LPCAM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D0_GPIO_PORT 8 +// "LPCAM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D0_GPIO_PIN 0 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D0_ALTERNATE_FUNCTION 4 + +// "LPCAM_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D1_GPIO_PORT 8 +// "LPCAM_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D1_GPIO_PIN 1 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D1_ALTERNATE_FUNCTION 3 + +// "LPCAM_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D2_GPIO_PORT 8 +// "LPCAM_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D2_GPIO_PIN 2 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D2_ALTERNATE_FUNCTION 4 + +// "LPCAM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D3_GPIO_PORT 8 +// "LPCAM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D3_GPIO_PIN 3 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D3_ALTERNATE_FUNCTION 4 + +// "LPCAM_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D4_GPIO_PORT 8 +// "LPCAM_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D4_GPIO_PIN 4 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D4_ALTERNATE_FUNCTION 4 + +// "LPCAM_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D5_GPIO_PORT 8 +// "LPCAM_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D5_GPIO_PIN 5 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D5_ALTERNATE_FUNCTION 4 + +// "LPCAM_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D6_GPIO_PORT 8 +// "LPCAM_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D6_GPIO_PIN 6 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D6_ALTERNATE_FUNCTION 4 + +// "LPCAM_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D7_GPIO_PORT 8 +// "LPCAM_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D7_GPIO_PIN 7 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D7_ALTERNATE_FUNCTION 4 + +// "LPI2C0_SDA_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2C0_SDA_GPIO_PORT 5 +// "LPI2C0_SDA_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2C0_SDA_GPIO_PIN 3 +// "LPI2C0_SDA_B" GPIO pin alternate function <0-7> +#define BOARD_LPI2C0_SDA_ALTERNATE_FUNCTION 4 + +// "LPI2C0_SCL_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2C0_SCL_GPIO_PORT 5 +// "LPI2C0_SCL_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2C0_SCL_GPIO_PIN 2 +// "LPI2C0_SCL_B" GPIO pin alternate function <0-7> +#define BOARD_LPI2C0_SCL_ALTERNATE_FUNCTION 5 + +// "I2C0_SDA_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C0_SDA_GPIO_PORT 3 +// "I2C0_SDA_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C0_SDA_GPIO_PIN 5 +// "I2C0_SDA_B" GPIO pin alternate function <0-7> +#define BOARD_I2C0_SDA_ALTERNATE_FUNCTION 5 + +// "I2C0_SCL_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C0_SCL_GPIO_PORT 3 +// "I2C0_SCL_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C0_SCL_GPIO_PIN 4 +// "I2C0_SCL_B" GPIO pin alternate function <0-7> +#define BOARD_I2C0_SCL_ALTERNATE_FUNCTION 5 + +// "Master" MW SPI instance number <0-3> +#define BOARD_MW_SPI_MASTER_INSTANCE 2 + +// "Slave" MW SPI instance number <0-3> +#define BOARD_MW_SPI_SLAVE_INSTANCE 3 + +// baudrate for Microwire SPI +#define BOARD_MW_SPI_MASTER_BUS_SPEED 1000000 + +// "LPSPI_MISO_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_MISO_GPIO_PORT 7 +// "LPSPI_MISO_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_MISO_GPIO_PIN 4 +// "LPSPI_MISO_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_MISO_ALTERNATE_FUNCTION 4 + +// "LPSPI_MOSI_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_MOSI_GPIO_PORT 7 +// "LPSPI_MOSI_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_MOSI_GPIO_PIN 5 +// "LPSPI_MOSI_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_MOSI_ALTERNATE_FUNCTION 5 + +// "LPSPI_SCLK_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_SCLK_GPIO_PORT 7 +// "LPSPI_SCLK_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_SCLK_GPIO_PIN 6 +// "LPSPI_SCLK_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_SCLK_ALTERNATE_FUNCTION 5 + +// "LPSPI_SS_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_SS_GPIO_PORT 7 +// "LPSPI_SS_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_SS_GPIO_PIN 7 +// "LPSPI_SS_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_SS_ALTERNATE_FUNCTION 5 + +// "SPI0_MISO_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_MISO_GPIO_PORT 5 +// "SPI0_MISO_B"GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_MISO_GPIO_PIN 0 +// "SPI0_MISO_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_MISO_ALTERNATE_FUNCTION 4 + +// "SPI0_MOSI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_MOSI_GPIO_PORT 5 +// "SPI0_MOSI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_MOSI_GPIO_PIN 1 +// "SPI0_MOSI_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_MOSI_ALTERNATE_FUNCTION 4 + +// "SPI0_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_SCLK_GPIO_PORT 5 +// "SPI0_SCLK_B" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_SCLK_GPIO_PIN 3 +// "SPI0_SCLK_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_SCLK_ALTERNATE_FUNCTION 3 + +// "SPI0_SS0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_SS0_GPIO_PORT 5 +// "SPI0_SS0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_SS0_GPIO_PIN 2 +// "SPI0_SS0_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_SS0_ALTERNATE_FUNCTION 4 + +// "SPI1_MISO_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_MISO_GPIO_PORT 8 +// "SPI1_MISO_B"GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_MISO_GPIO_PIN 3 +// "SPI1_MISO_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_MISO_ALTERNATE_FUNCTION 2 + +// "SPI1_MOSI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_MOSI_GPIO_PORT 8 +// "SPI1_MOSI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_MOSI_GPIO_PIN 4 +// "SPI1_MOSI_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_MOSI_ALTERNATE_FUNCTION 2 + +// "SPI1_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_SCLK_GPIO_PORT 8 +// "SPI1_SCLK_B" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_SCLK_GPIO_PIN 5 +// "SPI1_SCLK_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_SCLK_ALTERNATE_FUNCTION 2 + +// "SPI1_SS0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_SS0_GPIO_PORT 6 +// "SPI1_SS0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_SS0_GPIO_PIN 4 +// "SPI1_SS0_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_SS0_ALTERNATE_FUNCTION 4 + +// "MW_SPI_MASTER_MISO_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_MISO_GPIO_PORT 9 +// "MW_SPI_MASTER_MISO_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_MISO_GPIO_PIN 2 +// "MW_SPI_MASTER_MISO_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_MISO_ALTERNATE_FUNCTION 3 + +// "MW_SPI_MASTER_MOSI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_MOSI_GPIO_PORT 9 +// "MW_SPI_MASTER_MOSI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_MOSI_GPIO_PIN 3 +// "MW_SPI_MASTER_MOSI_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_MOSI_ALTERNATE_FUNCTION 4 + +// "MW_SPI_MASTER_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_SCLK_GPIO_PORT 9 +// "MW_SPI_MASTER_SCLK_B" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> +// PIN4 <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_SCLK_GPIO_PIN 4 +// "MW_SPI_MASTER_SCLK_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_SCLK_ALTERNATE_FUNCTION 3 + +// "MW_SPI_MASTER_SS0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_SS0_GPIO_PORT 9 +// "MW_SPI_MASTER_SS0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_SS0_GPIO_PIN 5 +// "MW_SPI_MASTER_SS0_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_SS0_ALTERNATE_FUNCTION 3 + +// "MW_SPI_SLAVE_MISO_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_MISO_GPIO_PORT 12 +// "MW_SPI_SLAVE_MISO_A"GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_MISO_GPIO_PIN 4 +// "MW_SPI_SLAVE_MISO_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_MISO_ALTERNATE_FUNCTION 2 + +// "MW_SPI_SLAVE_MOSI_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_MOSI_GPIO_PORT 12 +// "MW_SPI_SLAVE_MOSI_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_MOSI_GPIO_PIN 5 +// "MW_SPI_SLAVE_MOSI_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_MOSI_ALTERNATE_FUNCTION 2 + +// "MW_SPI_SLAVE_SCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_SCLK_GPIO_PORT 12 +// "MW_SPI_SLAVE_SCLK_A" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> +// PIN4 <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_SCLK_GPIO_PIN 6 +// "MW_SPI_SLAVE_SCLK_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_SCLK_ALTERNATE_FUNCTION 2 + +// "MW_SPI_SLAVE_SS0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_SS0_GPIO_PORT 12 +// "MW_SPI_SLAVE_SS0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_SS0_GPIO_PIN 7 +// "MW_SPI_SLAVE_SS0_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_SS0_ALTERNATE_FUNCTION 3 + +// "LPUART_RX_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPUART_RX_GPIO_PORT 7 +// "LPUART_RX_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPUART_RX_GPIO_PIN 6 +// "LPUART_RX_A" GPIO pin alternate function <0-7> +#define BOARD_LPUART_RX_ALTERNATE_FUNCTION 2 + +// "LPUART_TX_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPUART_TX_GPIO_PORT 7 +// "LPUART_TX_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPUART_TX_GPIO_PIN 7 +// "LPUART_TX_A" GPIO pin alternate function <0-7> +#define BOARD_LPUART_TX_ALTERNATE_FUNCTION 2 + +// "CDC_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_PCLK_GPIO_PORT 5 +// "CDC_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_PCLK_GPIO_PIN 3 +// "CDC_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_PCLK_ALTERNATE_FUNCTION 7 + +// "CDC_DE_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_DE_GPIO_PORT 5 +// "CDC_DE_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_DE_GPIO_PIN 4 +// "CDC_DE_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_DE_ALTERNATE_FUNCTION 7 + +// "CDC_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_HSYNC_GPIO_PORT 4 +// "CDC_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_HSYNC_GPIO_PIN 1 +// "CDC_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_HSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_VSYNC_GPIO_PORT 4 +// "CDC_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_VSYNC_GPIO_PIN 0 +// "CDC_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_VSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D0_GPIO_PORT 11 +// "CDC_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D0_GPIO_PIN 0 +// "CDC_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D0_ALTERNATE_FUNCTION 7 + +// "CDC_D1_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D1_GPIO_PORT 8 +// "CDC_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D1_GPIO_PIN 1 +// "CDC_D1_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D1_ALTERNATE_FUNCTION 5 + +// "CDC_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D2_GPIO_PORT 8 +// "CDC_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D2_GPIO_PIN 2 +// "CDC_D2_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D2_ALTERNATE_FUNCTION 6 + +// "CDC_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D3_GPIO_PORT 8 +// "CDC_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D3_GPIO_PIN 3 +// "CDC_D3_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D3_ALTERNATE_FUNCTION 6 + +// "CDC_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D4_GPIO_PORT 8 +// "CDC_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D4_GPIO_PIN 4 +// "CDC_D4_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D4_ALTERNATE_FUNCTION 6 + +// "CDC_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D5_GPIO_PORT 11 +// "CDC_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D5_GPIO_PIN 5 +// "CDC_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D5_ALTERNATE_FUNCTION 7 + +// "CDC_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D6_GPIO_PORT 11 +// "CDC_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D6_GPIO_PIN 6 +// "CDC_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D6_ALTERNATE_FUNCTION 7 + +// "CDC_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D7_GPIO_PORT 11 +// "CDC_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D7_GPIO_PIN 7 +// "CDC_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D7_ALTERNATE_FUNCTION 7 + +// "CDC_D8_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D8_GPIO_PORT 9 +// "CDC_D8_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D8_GPIO_PIN 0 +// "CDC_D8_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D8_ALTERNATE_FUNCTION 5 + +// "CDC_D9_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D9_GPIO_PORT 9 +// "CDC_D9_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D9_GPIO_PIN 1 +// "CDC_D9_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D9_ALTERNATE_FUNCTION 6 + +// "CDC_D10_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D10_GPIO_PORT 9 +// "CDC_D10_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D10_GPIO_PIN 2 +// "CDC_D10_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D10_ALTERNATE_FUNCTION 6 + +// "CDC_D11_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D11_GPIO_PORT 9 +// "CDC_D11_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D11_GPIO_PIN 3 +// "CDC_D11_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D11_ALTERNATE_FUNCTION 6 + +// "CDC_D12_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D12_GPIO_PORT 9 +// "CDC_D12_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D12_GPIO_PIN 4 +// "CDC_D12_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D12_ALTERNATE_FUNCTION 6 + +// "CDC_D13_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D13_GPIO_PORT 12 +// "CDC_D13_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D13_GPIO_PIN 5 +// "CDC_D13_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D13_ALTERNATE_FUNCTION 5 + +// "CDC_D14_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D14_GPIO_PORT 12 +// "CDC_D14_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D14_GPIO_PIN 6 +// "CDC_D14_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D14_ALTERNATE_FUNCTION 5 + +// "CDC_D15_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D15_GPIO_PORT 12 +// "CDC_D15_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D15_GPIO_PIN 7 +// "CDC_D15_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D15_ALTERNATE_FUNCTION 5 + +// "CDC_D16_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D16_GPIO_PORT 13 +// "CDC_D16_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D16_GPIO_PIN 0 +// "CDC_D16_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D16_ALTERNATE_FUNCTION 6 + +// "CDC_D17_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D17_GPIO_PORT 13 +// "CDC_D17_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D17_GPIO_PIN 1 +// "CDC_D17_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D17_ALTERNATE_FUNCTION 5 + +// "CDC_D18_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D18_GPIO_PORT 13 +// "CDC_D18_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D18_GPIO_PIN 2 +// "CDC_D18_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D18_ALTERNATE_FUNCTION 5 + +// "CDC_D19_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D19_GPIO_PORT 13 +// "CDC_D19_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D19_GPIO_PIN 3 +// "CDC_D19_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D19_ALTERNATE_FUNCTION 5 + +// "CDC_D20_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D20_GPIO_PORT 13 +// "CDC_D20_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D20_GPIO_PIN 4 +// "CDC_D20_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D20_ALTERNATE_FUNCTION 5 + +// "CDC_D21_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D21_GPIO_PORT 13 +// "CDC_D21_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D21_GPIO_PIN 5 +// "CDC_D21_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D21_ALTERNATE_FUNCTION 5 + +// "CDC_D22_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D22_GPIO_PORT 13 +// "CDC_D22_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D22_GPIO_PIN 6 +// "CDC_D22_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D22_ALTERNATE_FUNCTION 5 + +// "CDC_D23_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D23_GPIO_PORT 13 +// "CDC_D23_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D23_GPIO_PIN 7 +// "CDC_D23_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D23_ALTERNATE_FUNCTION 5 + +// "CLICKBOARD_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_INT_GPIO_PORT 8 +// "CLICKBOARD_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_INT_GPIO_PIN 1 + +// "CLICKBOARD_RST" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_RST_GPIO_PORT 8 +// "CLICKBOARD_RST" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_RST_GPIO_PIN 3 + +// "ICM42670_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ICM42670_IMU_IRQ_GPIO_PORT 8 +// "ICM42670_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_ICM42670_IMU_IRQ_GPIO_PIN 5 + +// "BMI323_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_BMI323_IMU_IRQ_GPIO_PORT 8 +// "BMI323_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_BMI323_IMU_IRQ_GPIO_PIN 4 + +// "CAMERA_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_RESET_GPIO_PORT 9 +// "CAMERA_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_RESET_GPIO_PIN 1 + +// "CAMERA_FLASH" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_FLASH_GPIO_PORT 9 +// "CAMERA_FLASH" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_FLASH_GPIO_PIN 2 + +// "CAMERA_TRIGGER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_TRIGGER_GPIO_PORT 9 +// "CAMERA_TRIGGER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_TRIGGER_GPIO_PIN 3 + +// "TOUCH_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_INT_GPIO_PORT 9 +// "TOUCH_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_TOUCH_INT_GPIO_PIN 4 + +// "LEDRGB0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_B_GPIO_PORT 12 +// "LEDRGB0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_B_GPIO_PIN 0 +// "LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_R" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_R_GPIO_PORT 12 +// "LEDRGB0_R" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_R_GPIO_PIN 3 +// "LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_G" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_G_GPIO_PORT 7 +// "LEDRGB0_G" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_G_GPIO_PIN 4 +// "LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_UT_ALTERNATE_FUNCTION 6 + +// "JOY_SW_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_A_GPIO_PORT 15 +// "JOY_SW_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_A_GPIO_PIN 0 + +// "JOY_SW_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_B_GPIO_PORT 15 +// "JOY_SW_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_B_GPIO_PIN 1 + +// "JOY_SW_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_C_GPIO_PORT 15 +// "JOY_SW_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_C_GPIO_PIN 2 + +// "JOY_SW_D" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_D_GPIO_PORT 15 +// "JOY_SW_D" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_D_GPIO_PIN 3 + +// "JOY_SW_CENTER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_CENTER_GPIO_PORT 15 +// "JOY_SW_CENTER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_JOY_SW_CENTER_GPIO_PIN 4 + +// "LCD_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_RESET_GPIO_PORT 15 +// "LCD_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LCD_RESET_GPIO_PIN 5 + +// "IS66_HYPERRAM_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_IS66_HYPERRAM_RESET_GPIO_PORT 15 +// "IS66_HYPERRAM_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_IS66_HYPERRAM_RESET_GPIO_PIN 6 + +// "PSRAM" OSPI instance number <0> (Do Not Modify!) +#define BOARD_PSRAM_OSPI_INSTANCE 0 + +// OSPI Flash instance number (Do Not Modify!) +#define BOARD_OSPI_FLASH_INSTANCE 1 + +// "OSPI_FLASH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_OSPI_FLASH_RESET_GPIO_PORT 15 +// "OSPI_FLASH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_OSPI_FLASH_RESET_GPIO_PIN 7 + +// "OSPI1_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_OSPI1_RESET_GPIO_PORT 15 +// "OSPI1_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_OSPI1_RESET_GPIO_PIN 7 + +// P0_0 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_0_ADC12_INSTANCE 0 +// P0_0 ADC12 input number (Do Not Modify!) +#define BOARD_P0_0_ADC12_INPUT 0 + +// P0_0 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_0_ADC24_POSITIVE_INPUT 0 + +// P0_0 CMP instance number (Do Not Modify!) +#define BOARD_P0_0_CMP_INSTANCE 0 +// P0_0 CMP input number (Do Not Modify!) +#define BOARD_P0_0_CMP_INPUT 0 + +// P0_1 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_1_ADC12_INSTANCE 0 +// P0_1 ADC12 input number (Do Not Modify!) +#define BOARD_P0_1_ADC12_INPUT 1 + +// P0_1 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_1_ADC24_POSITIVE_INPUT 1 + +// P0_1 CMP instance number (Do Not Modify!) +#define BOARD_P0_1_CMP_INSTANCE 1 +// P0_1 CMP input number (Do Not Modify!) +#define BOARD_P0_1_CMP_INPUT 0 + +// P0_2 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_2_ADC12_INSTANCE 0 +// P0_2 ADC12 input number (Do Not Modify!) +#define BOARD_P0_2_ADC12_INPUT 2 + +// P0_2 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_2_ADC24_POSITIVE_INPUT 2 + +// P0_2 CMP instance number (Do Not Modify!) +#define BOARD_P0_2_CMP_INSTANCE 2 +// P0_2 CMP input number (Do Not Modify!) +#define BOARD_P0_2_CMP_INPUT 0 + +// P0_3 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_3_ADC12_INSTANCE 0 +// P0_3 ADC12 input number (Do Not Modify!) +#define BOARD_P0_3_ADC12_INPUT 3 + +// P0_3 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_3_ADC24_POSITIVE_INPUT 3 + +// P0_3 CMP instance number (Do Not Modify!) +#define BOARD_P0_3_CMP_INSTANCE 3 +// P0_3 CMP input number (Do Not Modify!) +#define BOARD_P0_3_CMP_INPUT 0 + +// P0_4 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_4_ADC12_INSTANCE 0 +// P0_4 ADC12 input number (Do Not Modify!) +#define BOARD_P0_4_ADC12_INPUT 4 + +// P0_4 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_4_ADC24_NEGATIVE_INPUT 0 + +// P0_4 CMP instance number (Do Not Modify!) +#define BOARD_P0_4_CMP_INSTANCE 0 +// P0_4 CMP input number (Do Not Modify!) +#define BOARD_P0_4_CMP_INPUT 3 + +// P0_5 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_5_ADC12_INSTANCE 0 +// P0_5 ADC12 input number (Do Not Modify!) +#define BOARD_P0_5_ADC12_INPUT 5 + +// P0_5 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_5_ADC24_NEGATIVE_INPUT 1 + +// P0_5 CMP instance number (Do Not Modify!) +#define BOARD_P0_5_CMP_INSTANCE 1 +// P0_5 CMP input number (Do Not Modify!) +#define BOARD_P0_5_CMP_INPUT 3 + +// P0_6 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_6_ADC12_INSTANCE 1 +// P0_6 ADC12 input number (Do Not Modify!) +#define BOARD_P0_6_ADC12_INPUT 0 + +// P0_6 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_6_ADC24_NEGATIVE_INPUT 2 + +// P0_6 CMP instance number (Do Not Modify!) +#define BOARD_P0_6_CMP_INSTANCE 0 +// P0_6 CMP input number (Do Not Modify!) +#define BOARD_P0_6_CMP_INPUT 1 + +// P0_7 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_7_ADC12_INSTANCE 1 +// P0_7 ADC12 input number (Do Not Modify!) +#define BOARD_P0_7_ADC12_INPUT 1 + +// P0_7 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_7_ADC24_NEGATIVE_INPUT 3 + +// P0_7 CMP instance number (Do Not Modify!) +#define BOARD_P0_7_CMP_INSTANCE 1 +// P0_7 CMP input number (Do Not Modify!) +#define BOARD_P0_7_CMP_INPUT 1 + +// P1_0 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_0_ADC12_INSTANCE 1 +// P1_0 ADC12 input number (Do Not Modify!) +#define BOARD_P1_0_ADC12_INPUT 2 + +// P1_0 CMP instance number (Do Not Modify!) +#define BOARD_P1_0_CMP_INSTANCE 2 +// P1_0 CMP input number (Do Not Modify!) +#define BOARD_P1_0_CMP_INPUT 1 + +// P1_1 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_1_ADC12_INSTANCE 1 +// P1_1 ADC12 input number (Do Not Modify!) +#define BOARD_P1_1_ADC12_INPUT 3 + +// P1_1 CMP instance number (Do Not Modify!) +#define BOARD_P1_1_CMP_INSTANCE 3 +// P1_1 CMP input number (Do Not Modify!) +#define BOARD_P1_1_CMP_INPUT 1 + +// P1_2 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_2_ADC12_INSTANCE 1 +// P1_2 ADC12 input number (Do Not Modify!) +#define BOARD_P1_2_ADC12_INPUT 4 + +// P1_2 CMP instance number (Do Not Modify!) +#define BOARD_P1_2_CMP_INSTANCE 2 +// P1_2 CMP input number (Do Not Modify!) +#define BOARD_P1_2_CMP_INPUT 3 + +// P1_3 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_3_ADC12_INSTANCE 1 +// P1_3 ADC12 input number (Do Not Modify!) +#define BOARD_P1_3_ADC12_INPUT 5 + +// P1_3 CMP instance number (Do Not Modify!) +#define BOARD_P1_3_CMP_INSTANCE 3 +// P1_3 CMP input number (Do Not Modify!) +#define BOARD_P1_3_CMP_INPUT 3 + +// P1_4 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_4_ADC12_INSTANCE 2 +// P1_4 ADC12 input number (Do Not Modify!) +#define BOARD_P1_4_ADC12_INPUT 0 + +// P1_4 CMP instance number (Do Not Modify!) +#define BOARD_P1_4_CMP_INSTANCE 0 +// P1_4 CMP input number (Do Not Modify!) +#define BOARD_P1_4_CMP_INPUT 2 + +// P1_5 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_5_ADC12_INSTANCE 2 +// P1_5 ADC12 input number (Do Not Modify!) +#define BOARD_P1_5_ADC12_INPUT 1 + +// P1_5 CMP instance number (Do Not Modify!) +#define BOARD_P1_5_CMP_INSTANCE 1 +// P1_5 CMP input number (Do Not Modify!) +#define BOARD_P1_5_CMP_INPUT 2 + +// P1_6 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_6_ADC12_INSTANCE 2 +// P1_6 ADC12 input number (Do Not Modify!) +#define BOARD_P1_6_ADC12_INPUT 2 + +// P1_6 CMP instance number (Do Not Modify!) +#define BOARD_P1_6_CMP_INSTANCE 2 +// P1_6 CMP input number (Do Not Modify!) +#define BOARD_P1_6_CMP_INPUT 2 + +// P1_7 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_7_ADC12_INSTANCE 2 +// P1_7 ADC12 input number (Do Not Modify!) +#define BOARD_P1_7_ADC12_INPUT 3 + +// P1_7 CMP instance number (Do Not Modify!) +#define BOARD_P1_7_CMP_INSTANCE 3 +// P1_7 CMP input number (Do Not Modify!) +#define BOARD_P1_7_CMP_INPUT 2 + +// P2_0 ADC12 instance number (Do Not Modify!) +#define BOARD_P2_0_ADC12_INSTANCE 2 +// P2_0 ADC12 input number (Do Not Modify!) +#define BOARD_P2_0_ADC12_INPUT 4 + +// P2_1 ADC12 instance number (Do Not Modify!) +#define BOARD_P2_1_ADC12_INSTANCE 2 +// P2_1 ADC12 input number (Do Not Modify!) +#define BOARD_P2_1_ADC12_INPUT 1 + +// P2_2 DAC12 instance number (Do Not Modify!) +#define BOARD_P2_2_DAC12_INSTANCE 0 +// P2_3 DAC12 instance number (Do Not Modify!) +#define BOARD_P2_3_DAC12_INSTANCE 1 + +#define BOARD_DAC12_INSTANCE BOARD_P2_2_DAC12_INSTANCE + +// P2_4 LPCMP input number (Do Not Modify!) +#define BOARD_P2_4_LPCMP_INPUT 0 + +// P2_5 LPCMP input number (Do Not Modify!) +#define BOARD_P2_5_LPCMP_INPUT 1 + +// P2_6 LPCMP input number (Do Not Modify!) +#define BOARD_P2_6_LPCMP_INPUT 2 + +// P2_7 LPCMP input number (Do Not Modify!) +#define BOARD_P2_7_LPCMP_INPUT 3 + +// "WM8904_CODEC" on I2S presence flag +#define BOARD_WM8904_CODEC_PRESENT 0 + +#if defined(RTSS_HE) +// "DAC Output" I2S instance number <0=> I2S0 <1=> I2S1 <2=> I2S2 <3=> I2S3 LPI2S +#define BOARD_DAC_OUTPUT_I2S_INSTANCE LP + +// "DAC_OUTPUT_SDO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SDO_GPIO_PORT 13 +// "DAC_OUTPUT_SDO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SDO_GPIO_PIN 5 +// "DAC_OUTPUT_SDO" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SDO_ALTERNATE_FUNCTION 2 + +// "DAC_OUTPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_WS_GPIO_PORT 13 +// "DAC_OUTPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_WS_GPIO_PIN 7 +// "DAC_OUTPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_WS_ALTERNATE_FUNCTION 2 + +// "DAC_OUTPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PORT 13 +// "DAC_OUTPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PIN 6 +// "DAC_OUTPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SCLK_ALTERNATE_FUNCTION 2 +#else +// "DAC Output" I2S instance number <0=> I2S0 <1=> I2S1 <2=> I2S2 <3=> I2S3 LPI2S +#define BOARD_DAC_OUTPUT_I2S_INSTANCE 1 + +// "DAC_OUTPUT_SDO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SDO_GPIO_PORT 3 +// "DAC_OUTPUT_SDO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SDO_GPIO_PIN 3 +// "DAC_OUTPUT_SDO" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SDO_ALTERNATE_FUNCTION 3 + +// "DAC_OUTPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_WS_GPIO_PORT 4 +// "DAC_OUTPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_WS_GPIO_PIN 0 +// "DAC_OUTPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_WS_ALTERNATE_FUNCTION 3 + +// "DAC_OUTPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PORT 3 +// "DAC_OUTPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PIN 4 +// "DAC_OUTPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SCLK_ALTERNATE_FUNCTION 4 +#endif + +// "MIC_INPUT_SDI" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MIC_INPUT_SDI_GPIO_PORT 9 +// "MIC_INPUT_SDI" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_MIC_INPUT_SDI_GPIO_PIN 0 +// "MIC_INPUT_SDI" GPIO pin alternate function <0-7> +#define BOARD_MIC_INPUT_SDI_ALTERNATE_FUNCTION 2 + +// "MIC_INPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MIC_INPUT_WS_GPIO_PORT 8 +// "MIC_INPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_MIC_INPUT_WS_GPIO_PIN 7 +// "MIC_INPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_MIC_INPUT_WS_ALTERNATE_FUNCTION 2 + +// "MIC_INPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MIC_INPUT_SCLK_GPIO_PORT 8 +// "MIC_INPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_MIC_INPUT_SCLK_GPIO_PIN 6 +// "MIC_INPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_MIC_INPUT_SCLK_ALTERNATE_FUNCTION 2 + +// diff --git a/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h.base@2.2.0 b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h.base@2.2.0 new file mode 100644 index 0000000..9b452e7 --- /dev/null +++ b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/board_defs.h.base@2.2.0 @@ -0,0 +1,2401 @@ +/* +* Copyright (C) 2026 Alif Semiconductor - All Rights Reserved. +* Use, distribution and modification of this code is permitted under the +* terms stated in the Alif Semiconductor Software License Agreement +* +* You should have received a copy of the Alif Semiconductor Software +* License Agreement with this file. If not, please write to: +* https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ +*/ +/****************************************************************************** +* @file board_defs.h +* @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ +* @version v1.0.1 +* @date 2026-2-19 +* @brief Board info/settings for "AI/ML AppKit Gen 2 (AK-E7-AIML)" project +* with AE722F80F55D5LS +* @bug None. +* @note To modify this file manually, take care to modify pins.h and gpios.h +* accordingly when required. +******************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + +// Board peripheral instances +// "ADC12A" ADC12 instance number <0-2> +#define BOARD_ADC12A_ADC12_INSTANCE 0 + +// "ADC12B" ADC12 instance number <0-2> +#define BOARD_ADC12B_ADC12_INSTANCE 1 + +// "ADC12C" ADC12 instance number <0-2> +#define BOARD_ADC12C_ADC12_INSTANCE 2 + +// ADC24 module enabled flag +#define BOARD_ADC24_ENABLED 1 +// + +// CANFD module enabled flag +#define BOARD_CANFD_ENABLED 1 +// "CAN Transceiver" on CANFD presence flag +#define BOARD_CANFD_CAN_TRANSCEIVER_PRESENT 1 +// +// + +// "CMPA" CMP instance number <0-4> +#define BOARD_CMPA_CMP_INSTANCE 0 + +// "CMPB" CMP instance number <0-4> +#define BOARD_CMPB_CMP_INSTANCE 1 + +// "CMPC" CMP instance number <0-4> +#define BOARD_CMPC_CMP_INSTANCE 2 + +// "CMPD" CMP instance number <0-4> +#define BOARD_CMPD_CMP_INSTANCE 3 + +// CSI module enabled flag +#define BOARD_CSI_ENABLED 1 +// "ARX3A0" on CSI presence flag +#define BOARD_CSI_ARX3A0_PRESENT 1 +// +// "AR0144" on CSI presence flag +#define BOARD_CSI_AR0144_PRESENT 1 +// +// + +// DSI module enabled flag +#define BOARD_DSI_ENABLED 1 +// "ILI9806" on DSI presence flag +#define BOARD_DSI_ILI9806_PRESENT 1 +// +// + +// ETH module enabled flag +#define BOARD_ETH_ENABLED 1 +// "RTL8201" on ETH presence flag +#define BOARD_ETH_RTL8201_PRESENT 1 +// +// + +// "Clickboard" I2C instance number <0-3> +#define BOARD_CLICKBOARD_I2C_INSTANCE 0 + +// "Slave" I2C instance number <0-3> +#define BOARD_SLAVE_I2C_INSTANCE 0 + +// "Camera" I2C instance number <0-3> +#define BOARD_CAMERA_I2C_INSTANCE 1 + +// "GT911 Touchscreen" I2C instance number <0-3> +#define BOARD_GT911_TOUCHSCREEN_I2C_INSTANCE 1 + +// "Master" I2C instance number <0-3> +#define BOARD_MASTER_I2C_INSTANCE 1 + +// LPI2C0 module enabled flag +#define BOARD_LPI2C0_ENABLED 1 + +// "FLEXIO" on LPI2C0 presence flag +#define BOARD_LPI2C0_USE_FLEXIO_PINS 0 + +// "MIC Input" I2S instance number <0-3> +#define BOARD_MIC_INPUT_I2S_INSTANCE 3 + +// LPSPI module enabled flag +#define BOARD_LPSPI_ENABLED 1 + +// SPI salve instance number <0-3> +#define BOARD_SLAVE_SPI_INSTANCE 1 + +// SPI master instance number <0-3> +#define BOARD_MASTER_SPI_INSTANCE 1 + +// LPUART module enabled flag +#define BOARD_LPUART_ENABLED 1 + +// I3C module enabled flag +#define BOARD_I3C_ENABLED 1 + +// "FLEXIO" on I3C presence flag +#define BOARD_I3C_FLEXIO_PRESENT 1 +// "ICM42670 IMU" on I3C presence flag +#define BOARD_I3C_ICM42670_IMU_PRESENT 1 +// +// "BMI323 IMU" on I3C presence flag +#define BOARD_I3C_BMI323_IMU_PRESENT 1 +// +// "pin header" on I3C presence flag +#define BOARD_I3C_PIN_HEADER_PRESENT 1 +// +// + +// JTAG module enabled flag +#define BOARD_JTAG_ENABLED 1 +// + +// LPCPI module enabled flag +#define BOARD_LPCPI_ENABLED 1 +// + +// LPGPIO module enabled flag +#define BOARD_LPGPIO_ENABLED 1 +// + +// LPI2S module enabled flag +#define BOARD_LPI2S_ENABLED 0 +// + +// LPPDM module enabled flag +#define BOARD_LPPDM_ENABLED 1 +// + +// MISC module enabled flag +#define BOARD_MISC_ENABLED 1 +// + +// "ISSI Flash" OSPI instance number <1> +#define BOARD_ISSI_FLASH_OSPI_INSTANCE 1 + +// PDM module enabled flag +#define BOARD_PDM_ENABLED 1 +// "PDM MIC" on PDM presence flag +#define BOARD_PDM_PDM_MIC_PRESENT 1 +// +// + +// "Encoder" UTIMER instance number <12-15> +#define BOARD_ENCODER_UTIMER_INSTANCE 12 + +// SDMMC module enabled flag +#define BOARD_SDMMC_ENABLED 1 +// "SDCARD" on SDMMC presence flag +#define BOARD_SDMMC_SDCARD_PRESENT 1 +// +// + +// SEUART module enabled flag +#define BOARD_SEUART_ENABLED 1 +// + +// "Clickboard" UART instance number <0-7> +#define BOARD_CLICKBOARD_UART_INSTANCE 0 + +// "UARTA" UART instance number <0-7> +#define BOARD_UARTA_UART_INSTANCE 2 + +// "UARTB" UART instance number <0-7> +#define BOARD_UARTB_UART_INSTANCE 4 + +// USB module enabled flag +#define BOARD_USB_ENABLED 1 +// "Device Role" on USB presence flag +#define BOARD_USB_DEVICE_ROLE_PRESENT 1 +// +// + +// "Basic Mode" UTIMER instance number <0-12> +#define BOARD_BASIC_MODE_UTIMER_INSTANCE 0 + +// "Buffer Mode" UTIMER instance number <0-12> +#define BOARD_BUFFER_MODE_UTIMER_INSTANCE 1 + +// "Capture Mode" UTIMER instance number <0-12> +#define BOARD_CAPTURE_MODE_UTIMER_INSTANCE 4 + +// "Compare Mode" UTIMER instance number <0-12> +#define BOARD_COMPARE_MODE_UTIMER_INSTANCE 5 + +// "Trigger Mode" UTIMER instance number <0-12> +#define BOARD_TRIGGER_MODE_UTIMER_INSTANCE 3 + +// "Clickboard PWM" UTIMER instance number <0-12> +#define BOARD_CLICKBOARD_PWM_UTIMER_INSTANCE 3 + +// Utimer 250ms counter value +#define BOARD_UTIMER_250_MILLI_SEC_COUNTER_VALUE 100000000 + +// Utimer 500ms counter value +#define BOARD_UTIMER_500_MILLI_SEC_COUNTER_VALUE 200000000 + +// Utimer 750ms counter value +#define BOARD_UTIMER_750_MILLI_SEC_COUNTER_VALUE 300000000 + +// Utimer 1000ms counter value +#define BOARD_UTIMER_1000_MILLI_SEC_COUNTER_VALUE 400000000 + +// Utimer 1500ms counter value +#define BOARD_UTIMER_1500_MILLI_SEC_COUNTER_VALUE 600000000 + +// LED PWM utimer max counter value +#define BOARD_LED_PWM_UT_MAX_COUNTER_VALUE 240000 + +// "RED_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_RED_LED_UTIMER_COUNTER_TYPE 1 + +// "GREEN_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_GREEN_LED_UTIMER_COUNTER_TYPE 0 + +// "BLUE_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_BLUE_LED_UTIMER_COUNTER_TYPE 0 + +// UTIMER channel red LED instance number <9> +#define BOARD_RED_LED_UTIMER_INSTANCE 9 + +// UTIMER channel green LED instance number <10> +#define BOARD_GREEN_LED_UTIMER_INSTANCE 10 + +// UTIMER channel blue LED instance number <8> +#define BOARD_BLUE_LED_UTIMER_INSTANCE 8 + +// CMP external trigger UTIMER channel instance number <0-12> +#define BOARD_CMP_EXT_TRIGGER_UTIMER_INSTANCE 0 + +// +// Miscellaneous +// Onboard LEDs +// Sets the #define BOARD_LED_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LED_COUNT 0 + +// Onboard RGB LEDs +// Sets the #define BOARD_LEDRGB_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LEDRGB_COUNT 2 + +// Onboard Push-buttons +// Sets the #define BOARD_BUTTON_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_BUTTON_COUNT 5 + +// Onboard Config Switches or Jumpers +// Sets the #define BOARD_CONFIG_JUMPER_COUNT in the board_def.h file exported from the +// Conductor tool. +#define BOARD_CONFIG_JUMPER_COUNT 0 + +// Onboard Switching Devices +// Sets the #define BOARD_SWITCH_OUTPUT_COUNT in the board_def.h file exported from the +// Conductor tool. These include relays, solid state relays, transistors, optocopulers, etc. +#define BOARD_SWITCH_OUTPUT_COUNT 0 + +// OSPI0 Bus Speed +// Selects OSPI0 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI0_BUS_SPEED 100000000 + +// OSPI1 Bus Speed +// Selects OSPI1 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI1_BUS_SPEED 100000000 + +// OSPI0 onboard memory size +#define BOARD_OSPI0_MEM_SIZE 33554432 + +// OSPI1 onboard memory size +#define BOARD_OSPI1_MEM_SIZE 67108864 + +// +// GPIO port/pin numbers, analog instance/input numbers, etc. +// FLEX IO pins supply voltage <0=> 3.3 V <1=> 1.8 V +// Make sure this setting corresponds to the VDD_IO_FLEX pin voltage. If the VDD_IO_FLEX pin is +// connected to a 3.3 V supply, do not change the value of the GPIO_CNTL register to command 1.8-V +// operation mode! +#define FLEX_IO_VOLTAGE_1V8 1 + +// "CLICKBOARD_ANA" ADC12 instance number <0=> ADC120 <1=> ADC121 <2=> ADC122 +#define BOARD_CLICKBOARD_ANA_ADC12_INSTANCE 1 +// "CLICKBOARD_ANA" ADC12 input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 <4=> IN4 <5=> IN5 +#define BOARD_CLICKBOARD_ANA_ADC12_INPUT 0 + +// "CLICKBOARD_ANA" ADC24 negative input number <0=> IN0_N <1=> IN1_N <2=> IN2_N <3=> IN3_N +// WARNING: This option does not change the positive input pin automatically! +#define BOARD_CLICKBOARD_ANA_ADC24_INPUT 2 + +// "CLICKBOARD_ANA" CMP instance number <0=> CMP0 <1=> CMP1 <2=> CMP2 <3=> CMP3 +#define BOARD_CLICKBOARD_ANA_CMP_INSTANCE 0 +// "CLICKBOARD_ANA" CMP input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 +#define BOARD_CLICKBOARD_ANA_CMP_INPUT 1 + +// "POTENTIOMETER" ADC12 instance number <0=> ADC120 <1=> ADC121 <2=> ADC122 +#define BOARD_POTENTIOMETER_ADC12_INSTANCE 1 +// "POTENTIOMETER" ADC12 input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 <4=> IN4 <5=> IN5 +#define BOARD_POTENTIOMETER_ADC12_INPUT 1 + +// "POTENTIOMETER" ADC24 negative input number <0=> IN0_N <1=> IN1_N <2=> IN2_N <3=> IN3_N +// WARNING: This option does not change the positive input pin automatically! +#define BOARD_POTENTIOMETER_ADC24_INPUT 3 + +// "POTENTIOMETER" CMP instance number <0=> CMP0 <1=> CMP1 <2=> CMP2 <3=> CMP3 +#define BOARD_POTENTIOMETER_CMP_INSTANCE 0 +// "POTENTIOMETER" CMP input number <0=> IN0 <1=> IN1 <2=> IN2 <3=> IN3 +#define BOARD_POTENTIOMETER_CMP_INPUT 0 + +// "CMP0_POS_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP0_POS_INPUT_GPIO_PORT 0 +// "CMP0_POS_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CMP0_POS_INPUT_GPIO_PIN 0 +// "CMP0_POS_INPUT" GPIO pin alternate function <0-7> +#define BOARD_CMP0_POS_INPUT_ALTERNATE_FUNCTION 7 + +// "CMP_NEG_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP_NEG_INPUT_GPIO_PORT 2 +// "CMP_NEG_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CMP_NEG_INPUT_GPIO_PIN 0 +// "CMP_NEG_INPUT" GPIO pin alternate function <0-7> +#define BOARD_CMP_NEG_INPUT_ALTERNATE_FUNCTION 7 + +// "CMP1_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP1_OUT_GPIO_PORT 14 +// "CMP1_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP1_OUT_GPIO_PIN 6 +// "CMP1_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP1_OUT_ALTERNATE_FUNCTION 1 + +// "CMP0_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP0_OUT_GPIO_PORT 14 +// "CMP0_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP0_OUT_GPIO_PIN 7 +// "CMP0_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP0_OUT_ALTERNATE_FUNCTION 1 + +// "CMP3_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP3_OUT_GPIO_PORT 14 +// "CMP3_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP3_OUT_GPIO_PIN 4 +// "CMP3_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP3_OUT_ALTERNATE_FUNCTION 1 + +// "CMP2_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CMP2_OUT_GPIO_PORT 14 +// "CMP2_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CMP2_OUT_GPIO_PIN 5 +// "CMP2_OUT" GPIO pin alternate function <0-7> +#define BOARD_CMP2_OUT_ALTERNATE_FUNCTION 1 + +// "LPCMP_POS_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCMP_POS_INPUT_GPIO_PORT 2 +// "LPCMP_POS_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCMP_POS_INPUT_GPIO_PIN 4 +// "LPCMP_POS_INPUT" GPIO pin alternate function <0-7> +#define BOARD_LPCMP_POS_INPUT_ALTERNATE_FUNCTION 7 + +// "LPCMP_NEG_INPUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCMP_NEG_INPUT_GPIO_PORT 2 +// "LPCMP_NEG_INPUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCMP_NEG_INPUT_GPIO_PIN 0 +// "LPCMP_NEG_INPUT" GPIO pin alternate function <0-7> +#define BOARD_LPCMP_NEG_INPUT_ALTERNATE_FUNCTION 7 + +// ADC12 instance <0=>0 <0=>1 <0=>2 +#define BOARD_ADC12_INSTANCE 2 + +// "ADC12_CH0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH0_GPIO_PORT 1 +// "ADC12_CH0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH0_GPIO_PIN 4 + +// "ADC12_CH1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH1_GPIO_PORT 1 +// "ADC12_CH1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH1_GPIO_PIN 5 + +// "ADC12_CH2" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH2_GPIO_PORT 1 +// "ADC12_CH2" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH2_GPIO_PIN 6 + +// "ADC12_CH3" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH3_GPIO_PORT 1 +// "ADC12_CH3" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH3_GPIO_PIN 7 + +// "ADC12_CH4" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH4_GPIO_PORT 2 +// "ADC12_CH4" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH4_GPIO_PIN 0 + +// "ADC12_CH5" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC12_CH5_GPIO_PORT 2 +// "ADC12_CH5" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC12_CH5_GPIO_PIN 1 + +// "ADC24_CH0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH0_POS_GPIO_PORT 0 +// "ADC24_CH0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH0_POS_GPIO_PIN 0 + +// "ADC24_CH0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH0_NEG_GPIO_PORT 0 +// "ADC24_CH0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH0_NEG_GPIO_PIN 4 + +// "ADC24_CH1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH1_POS_GPIO_PORT 0 +// "ADC24_CH1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH1_POS_GPIO_PIN 1 + +// "ADC24_CH1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH1_NEG_GPIO_PORT 0 +// "ADC24_CH1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH1_NEG_GPIO_PIN 5 + +// "ADC24_CH2" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH2_POS_GPIO_PORT 0 +// "ADC24_CH2" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH2_POS_GPIO_PIN 2 + +// "ADC24_CH2" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH2_NEG_GPIO_PORT 0 +// "ADC24_CH2" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH2_NEG_GPIO_PIN 6 + +// "ADC24_CH3" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH3_POS_GPIO_PORT 0 +// "ADC24_CH3" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH3_POS_GPIO_PIN 3 + +// "ADC24_CH3" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC24_CH3_NEG_GPIO_PORT 0 +// "ADC24_CH3" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_ADC24_CH3_NEG_GPIO_PIN 7 + +// "CLICKBOARD_ANA" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ADC_CLICKBOARD_ANA_GPIO_PORT 0 +// "CLICKBOARD_ANA" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_ADC_CLICKBOARD_ANA_GPIO_PIN 6 + +// "DAC120_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC120_OUT_GPIO_PORT 2 +// "DAC120_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_DAC120_OUT_GPIO_PIN 2 +// "DAC120_OUT" GPIO pin alternate function <0-7> +#define BOARD_DAC120_ALTERNATE_FUNCTION 7 + +// "DAC121_OUT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC121_OUT_GPIO_PORT 2 +// "DAC121_OUT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_DAC121_OUT_GPIO_PIN 3 +// "LPCMP_NEG_INPUT" GPIO pin alternate function <0-7> +#define BOARD_DAC121_ALTERNATE_FUNCTION 7 + +// "SD_CARD_DETECT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CARD_DETECT_GPIO_PORT 3 +// "SD_CARD_DETECT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SD_CARD_DETECT_GPIO_PIN 3 + +// "SD_CMD_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CMD_A_GPIO_PORT 7 +// "SD_CMD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CMD_A_GPIO_PIN 0 +// "SD_CMD_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CMD_ALTERNATE_FUNCTION 6 + +// "SD_CLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CLK_A_GPIO_PORT 7 +// "SD_CLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CLK_A_GPIO_PIN 1 +// "SD_CLK_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CLK_ALTERNATE_FUNCTION 6 + +// "SD_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D0_A_GPIO_PORT 5 +// "SD_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D0_A_GPIO_PIN 0 +// "SD_D0_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D0_ALTERNATE_FUNCTION 7 + +// "SD_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D1_A_GPIO_PORT 5 +// "SD_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D1_A_GPIO_PIN 1 +// "SD_D1_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D1_ALTERNATE_FUNCTION 7 + +// "SD_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D2_A_GPIO_PORT 5 +// "SD_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D2_A_GPIO_PIN 2 +// "SD_D2_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D2_ALTERNATE_FUNCTION 7 + +// "SD_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D3_A_GPIO_PORT 5 +// "SD_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D3_A_GPIO_PIN 3 +// "SD_D3_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D3_ALTERNATE_FUNCTION 6 + +// "SD_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D4_A_GPIO_PORT 5 +// "SD_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D4_A_GPIO_PIN 4 + +// "SD_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D5_A_GPIO_PORT 5 +// "SD_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D5_A_GPIO_PIN 5 + +// "SD_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D6_A_GPIO_PORT 5 +// "SD_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D6_A_GPIO_PIN 6 + +// "SD_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D7_A_GPIO_PORT 5 +// "SD_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D7_A_GPIO_PIN 7 + +// "I2C1_SDA_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C1_SDA_C_GPIO_PORT 7 +// "I2C1_SDA_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C1_SDA_C_GPIO_PIN 2 + +// "I2C1_SCL_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C1_SCL_C_GPIO_PORT 7 +// "I2C1_SCL_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C1_SCL_C_GPIO_PIN 3 + +// "LPI2S_SDO_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2S_SDO_C_GPIO_PORT 13 +// "LPI2S_SDO_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2S_SDO_C_GPIO_PIN 5 + +// "LPI2S_WS_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2S_WS_C_GPIO_PORT 13 +// "LPI2S_WS_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPI2S_WS_C_GPIO_PIN 7 + +// "LPI2S_SCLK_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2S_SCLK_C_GPIO_PORT 13 +// "LPI2S_SCLK_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2S_SCLK_C_GPIO_PIN 6 + +// "I2S3_WS_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S3_WS_B_GPIO_PORT 8 +// "I2S3_WS_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S3_WS_B_GPIO_PIN 7 + +// "I2S3_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S3_SCLK_B_GPIO_PORT 8 +// "I2S3_SCLK_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_I2S3_SCLK_B_GPIO_PIN 6 + +// "I2S3_SDI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S3_SDI_B_GPIO_PORT 9 +// "I2S3_SDI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S3_SDI_B_GPIO_PIN 0 + +// "I2S1_SDO_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S1_SDO_GPIO_PORT 3 +// "I2S1_SDO_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S1_SDO_GPIO_PIN 3 + +// "I2S1_WS_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S1_WS_GPIO_PORT 4 +// "I2S1_WS_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2S1_WS_GPIO_PIN 0 + +// "I2S1_SCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2S1_SCLK_GPIO_PORT 3 +// "I2S1_SCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_I2S1_SCLK_GPIO_PIN 4 + +// "LPPDM_TEST" LPPDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_LPPDM_TEST_LPPDM_INPUT 1 + +// "LPPDM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D0_GPIO_PORT 3 +// "LPPDM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D0_GPIO_PIN 5 +// "LPPDM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D0_ALTERNATE_FUNCTION 3 + +// "LPPDM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D1_GPIO_PORT 3 +// "LPPDM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D1_GPIO_PIN 7 +// "LPPDM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D1_ALTERNATE_FUNCTION 3 + +// "LPPDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D2_GPIO_PORT 11 +// "LPPDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D2_GPIO_PIN 6 +// "LPPDM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D2_ALTERNATE_FUNCTION 3 + +// "LPPDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D3_GPIO_PORT 7 +// "LPPDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D3_GPIO_PIN 7 +// "LPPDM_D3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D3_ALTERNATE_FUNCTION 4 + +// "LPPDM_C0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C0_GPIO_PORT 3 +// "LPPDM_C0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C0_GPIO_PIN 4 +// "LPPDM_C0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C0_ALTERNATE_FUNCTION 3 + +// "LPPDM_C1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C1_GPIO_PORT 3 +// "LPPDM_C1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C1_GPIO_PIN 6 +// "LPPDM_C1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C1_ALTERNATE_FUNCTION 3 + +// "LPPDM_C2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C2_GPIO_PORT 11 +// "LPPDM_C2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C2_GPIO_PIN 2 +// "LPPDM_C2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C2_ALTERNATE_FUNCTION 3 + +// "LPPDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C3_GPIO_PORT 7 +// "LPPDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C3_GPIO_PIN 6 +// "LPPDM_C3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C3_ALTERNATE_FUNCTION 4 + +// "PDM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D0_A_GPIO_PORT 0 +// "PDM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D0_A_GPIO_PIN 4 + +// "PDM_D1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D1_C_GPIO_PORT 6 +// "PDM_D1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D1_C_GPIO_PIN 2 + +// "PDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D2_B_GPIO_PORT 5 +// "PDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D2_B_GPIO_PIN 4 + +// "PDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D3_A_GPIO_PORT 5 +// "PDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D3_A_GPIO_PIN 1 + +// "PDM_C0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C0_A_GPIO_PORT 0 +// "PDM_C0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C0_A_GPIO_PIN 5 + +// "PDM_C1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C1_C_GPIO_PORT 6 +// "PDM_C1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C1_C_GPIO_PIN 3 + +// "PDM_C2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C2_A_GPIO_PORT 6 +// "PDM_C2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C2_A_GPIO_PIN 7 + +// "PDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C3_A_GPIO_PORT 5 +// "PDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C3_A_GPIO_PIN 2 + +// "TOUCH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_RESET_GPIO_PORT 4 +// "TOUCH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_TOUCH_RESET_GPIO_PIN 0 + +// "UT_TRIGGER_MODE_GPO0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_GPO0_GPIO_PORT 3 +// "UT_TRIGGER_MODE_GPO0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_GPO0_GPIO_PIN 5 + +// "UTIMER_GPO1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_GPO1_GPIO_PORT 3 +// "UTIMER_GPO1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_GPO1_GPIO_PIN 6 + +// "UT_CAPTURE_MODE_GPO0" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_GPO0_GPIO_PORT 3 +// "UT_CAPTURE_MODE_GPO0" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_GPO0_GPIO_PIN 3 + +// "UT_CAPTURE_MODE_GPO1" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_GPO1_GPIO_PORT 3 +// "UT_CAPTURE_MODE_GPO1" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_GPO1_GPIO_PIN 4 + +// "UT_TRIGGER_MODE_T0_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_T0_GPO_GPIO_PORT 0 +// "UT_TRIGGER_MODE_T0_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_T0_GPO_GPIO_PIN 6 +// "UT_TRIGGER_MODE_T0_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_TRIGGER_MODE_T0_GPO_ALTERNATE_FUNCTION 5 + +// "UT_TRIGGER_MODE_T1_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_TRIGGER_MODE_T1_GPO_GPIO_PORT 0 +// "UT_TRIGGER_MODE_T1_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_TRIGGER_MODE_T1_GPO_GPIO_PIN 7 +// "UT_TRIGGER_MODE_T1_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_TRIGGER_MODE_T1_GPO_ALTERNATE_FUNCTION 5 + +// "UT_CAPTURE_MODE_T0_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_T0_GPO_GPIO_PORT 1 +// "UT_CAPTURE_MODE_T0_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_T0_GPO_GPIO_PIN 0 +// "UT_CAPTURE_MODE_T0_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_CAPTURE_MODE_T0_GPO_ALTERNATE_FUNCTION 4 + +// "UT_CAPTURE_MODE_T1_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_CAPTURE_MODE_T1_GPO_GPIO_PORT 1 +// "UT_CAPTURE_MODE_T1_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_CAPTURE_MODE_T1_GPO_GPIO_PIN 1 +// "UT_CAPTURE_MODE_T1_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_CAPTURE_MODE_T1_GPO_ALTERNATE_FUNCTION 4 + +// "UT_COMPARE_MODE_T0_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_UT_COMPARE_MODE_T0_GPO_GPIO_PORT 1 +// "UT_COMPARE_MODE_T0_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_UT_COMPARE_MODE_T0_GPO_GPIO_PIN 2 +// "UT_COMPARE_MODE_T0_GPO" GPIO pin alternate function <0-7> +#define BOARD_UT_COMPARE_MODE_T0_GPO_ALTERNATE_FUNCTION 4 + +// "QEC0_X_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC0_X_B_GPIO_PORT 8 +// "QEC0_X_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC0_X_B_GPIO_PIN 4 + +// "QEC0_Y_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC0_Y_B_GPIO_PORT 8 +// "QEC0_Y_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC0_Y_B_GPIO_PIN 5 + +// "QEC0_Z_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC0_Z_B_GPIO_PORT 8 +// "QEC0_Z_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC0_Z_B_GPIO_PIN 6 + +// "QEC_X_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC_X_GPO_GPIO_PORT 1 +// "QEC0_X_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC_X_GPO_GPIO_PIN 0 + +// "QEC_Y_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC_Y_GPO_GPIO_PORT 1 +// "QEC_Y_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC_Y_GPO_GPIO_PIN 1 + +// "QEC_Z_GPO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_QEC_Z_GPO_GPIO_PORT 1 +// "QEC_Z_GPO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_QEC_Z_GPO_GPIO_PIN 2 + +// "PDM_MIC" PDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_PDM_MIC_PDM_INPUT 2 + +// "LCD_BACKLIGHT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_BACKLIGHT_GPIO_PORT 6 +// "LCD_BACKLIGHT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 1 + +// "LEDRGB1_R" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB1_R_GPIO_PORT 6 +// "LEDRGB1_R" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB1_R_GPIO_PIN 2 +// "LEDRGB1_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB1_R_ALTERNATE_FUNCTION 0 + +// "LEDRGB1_G" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB1_G_GPIO_PORT 6 +// "LEDRGB1_G" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB1_G_GPIO_PIN 5 +// "LEDRGB1_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB1_G_ALTERNATE_FUNCTION 0 + +// "LEDRGB1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB1_B_GPIO_PORT 6 +// "LEDRGB1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB1_B_GPIO_PIN 6 +// "LEDRGB1_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB1_B_ALTERNATE_FUNCTION 0 + +// "CAN_RXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_RXD_GPIO_PORT 7 +// "CAN_RXD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_RXD_GPIO_PIN 0 +// "CAN_RXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_RXD_ALTERNATE_FUNCTION 7 + +// "CAN_TXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_TXD_GPIO_PORT 7 +// "CAN_TXD" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_TXD_GPIO_PIN 1 +// "CAN_TXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_TXD_ALTERNATE_FUNCTION 7 + +// "CAN_STBY" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_STBY_GPIO_PORT 7 +// "CAN_STBY" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_STBY_GPIO_PIN 3 +// "CAN_STBY" GPIO pin alternate function <0-7> +#define BOARD_CAN_STBY_ALTERNATE_FUNCTION 7 + +// "CAM_XVCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_XVCLK_A_GPIO_PORT 0 +// "CAM_XVCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_XVCLK_A_GPIO_PIN 3 + +// "CAMERA_POWER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_POWER_GPIO_PORT 7 +// "CAMERA_POWER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_POWER_GPIO_PIN 5 + +// "I2C1_SDA_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SDA_GPIO_PORT 7 +// "I2C1_SDA_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SDA_GPIO_PIN 2 +// "I2C1_SDA_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SDA_ALTERNATE_FUNCTION 5 + +// "I2C1_SCL_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SCL_GPIO_PORT 7 +// "I2C1_SCL_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SCL_GPIO_PIN 3 +// "I2C1_SCL_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SCL_ALTERNATE_FUNCTION 5 + +// "CAM_HSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_HSYNC_GPIO_PORT 0 +// "CAM_HSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_HSYNC_GPIO_PIN 0 +// "CAM_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_HSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_VSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_VSYNC_GPIO_PORT 0 +// "CAM_VSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_VSYNC_GPIO_PIN 1 +// "CAM_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_VSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_PCLK_GPIO_PORT 0 +// "CAM_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_PCLK_GPIO_PIN 2 +// "CAM_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_PCLK_ALTERNATE_FUNCTION 6 + +// "CAM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D0_GPIO_PORT 8 +// "CAM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D0_GPIO_PIN 0 +// "CAM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D0_ALTERNATE_FUNCTION 7 + +// "CAM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D1_GPIO_PORT 8 +// "CAM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D1_GPIO_PIN 1 +// "CAM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D1_ALTERNATE_FUNCTION 6 + +// "CAM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D2_GPIO_PORT 8 +// "CAM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D2_GPIO_PIN 2 +// "CAM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D2_ALTERNATE_FUNCTION 7 + +// "CAM_D3_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D3_GPIO_PORT 8 +// "CAM_D3_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D3_GPIO_PIN 3 +// "CAM_D3_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D3_ALTERNATE_FUNCTION 7 + +// "CAM_D4_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D4_GPIO_PORT 8 +// "CAM_D4_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D4_GPIO_PIN 4 +// "CAM_D4_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D4_ALTERNATE_FUNCTION 7 + +// "CAM_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D5_GPIO_PORT 8 +// "CAM_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D5_GPIO_PIN 5 +// "CAM_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D5_ALTERNATE_FUNCTION 7 + +// "CAM_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D6_GPIO_PORT 8 +// "CAM_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D6_GPIO_PIN 6 +// "CAM_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D6_ALTERNATE_FUNCTION 7 + +// "CAM_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D7_GPIO_PORT 8 +// "CAM_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D7_GPIO_PIN 7 +// "CAM_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D7_ALTERNATE_FUNCTION 7 + +// "LPCAM_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_HSYNC_GPIO_PORT 0 +// "LPCAM_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_HSYNC_GPIO_PIN 0 +// "LPCAM_HSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_HSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_VSYNC_GPIO_PORT 0 +// "LPCAM_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_VSYNC_GPIO_PIN 1 +// "LPCAM_VSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_VSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_PCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_PCLK_GPIO_PORT 0 +// "LPCAM_PCLK_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_PCLK_GPIO_PIN 2 +// "LPCAM_PCLK_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_PCLK_ALTERNATE_FUNCTION 5 + +// "LPCAM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D0_GPIO_PORT 8 +// "LPCAM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D0_GPIO_PIN 0 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D0_ALTERNATE_FUNCTION 4 + +// "LPCAM_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D1_GPIO_PORT 8 +// "LPCAM_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D1_GPIO_PIN 1 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D1_ALTERNATE_FUNCTION 3 + +// "LPCAM_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D2_GPIO_PORT 8 +// "LPCAM_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D2_GPIO_PIN 2 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D2_ALTERNATE_FUNCTION 4 + +// "LPCAM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D3_GPIO_PORT 8 +// "LPCAM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D3_GPIO_PIN 3 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D3_ALTERNATE_FUNCTION 4 + +// "LPCAM_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D4_GPIO_PORT 8 +// "LPCAM_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D4_GPIO_PIN 4 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D4_ALTERNATE_FUNCTION 4 + +// "LPCAM_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D5_GPIO_PORT 8 +// "LPCAM_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D5_GPIO_PIN 5 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D5_ALTERNATE_FUNCTION 4 + +// "LPCAM_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D6_GPIO_PORT 8 +// "LPCAM_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D6_GPIO_PIN 6 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D6_ALTERNATE_FUNCTION 4 + +// "LPCAM_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D7_GPIO_PORT 8 +// "LPCAM_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D7_GPIO_PIN 7 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D7_ALTERNATE_FUNCTION 4 + +// "LPI2C0_SDA_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2C0_SDA_GPIO_PORT 5 +// "LPI2C0_SDA_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2C0_SDA_GPIO_PIN 3 +// "LPI2C0_SDA_B" GPIO pin alternate function <0-7> +#define BOARD_LPI2C0_SDA_ALTERNATE_FUNCTION 4 + +// "LPI2C0_SCL_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPI2C0_SCL_GPIO_PORT 5 +// "LPI2C0_SCL_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPI2C0_SCL_GPIO_PIN 2 +// "LPI2C0_SCL_B" GPIO pin alternate function <0-7> +#define BOARD_LPI2C0_SCL_ALTERNATE_FUNCTION 5 + +// "I2C0_SDA_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C0_SDA_GPIO_PORT 3 +// "I2C0_SDA_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C0_SDA_GPIO_PIN 5 +// "I2C0_SDA_B" GPIO pin alternate function <0-7> +#define BOARD_I2C0_SDA_ALTERNATE_FUNCTION 5 + +// "I2C0_SCL_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_I2C0_SCL_GPIO_PORT 3 +// "I2C0_SCL_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_I2C0_SCL_GPIO_PIN 4 +// "I2C0_SCL_B" GPIO pin alternate function <0-7> +#define BOARD_I2C0_SCL_ALTERNATE_FUNCTION 5 + +// "Master" MW SPI instance number <0-3> +#define BOARD_MW_SPI_MASTER_INSTANCE 2 + +// "Slave" MW SPI instance number <0-3> +#define BOARD_MW_SPI_SLAVE_INSTANCE 3 + +// baudrate for Microwire SPI +#define BOARD_MW_SPI_MASTER_BUS_SPEED 1000000 + +// "LPSPI_MISO_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_MISO_GPIO_PORT 7 +// "LPSPI_MISO_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_MISO_GPIO_PIN 4 +// "LPSPI_MISO_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_MISO_ALTERNATE_FUNCTION 4 + +// "LPSPI_MOSI_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_MOSI_GPIO_PORT 7 +// "LPSPI_MOSI_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_MOSI_GPIO_PIN 5 +// "LPSPI_MOSI_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_MOSI_ALTERNATE_FUNCTION 5 + +// "LPSPI_SCLK_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_SCLK_GPIO_PORT 7 +// "LPSPI_SCLK_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_SCLK_GPIO_PIN 6 +// "LPSPI_SCLK_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_SCLK_ALTERNATE_FUNCTION 5 + +// "LPSPI_SS_A" master GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPSPI_SS_GPIO_PORT 7 +// "LPSPI_SS_A" masterGPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_LPSPI_SS_GPIO_PIN 7 +// "LPSPI_SS_A" GPIO pin alternate function <0-7> +#define BOARD_LPSPI_SS_ALTERNATE_FUNCTION 5 + +// "SPI0_MISO_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_MISO_GPIO_PORT 5 +// "SPI0_MISO_B"GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_MISO_GPIO_PIN 0 +// "SPI0_MISO_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_MISO_ALTERNATE_FUNCTION 4 + +// "SPI0_MOSI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_MOSI_GPIO_PORT 5 +// "SPI0_MOSI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_MOSI_GPIO_PIN 1 +// "SPI0_MOSI_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_MOSI_ALTERNATE_FUNCTION 4 + +// "SPI0_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_SCLK_GPIO_PORT 5 +// "SPI0_SCLK_B" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_SCLK_GPIO_PIN 3 +// "SPI0_SCLK_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_SCLK_ALTERNATE_FUNCTION 3 + +// "SPI0_SS0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI0_SS0_GPIO_PORT 5 +// "SPI0_SS0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI0_SS0_GPIO_PIN 2 +// "SPI0_SS0_B" GPIO pin alternate function <0-7> +#define BOARD_SPI0_SS0_ALTERNATE_FUNCTION 4 + +// "SPI1_MISO_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_MISO_GPIO_PORT 8 +// "SPI1_MISO_B"GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_MISO_GPIO_PIN 3 +// "SPI1_MISO_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_MISO_ALTERNATE_FUNCTION 2 + +// "SPI1_MOSI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_MOSI_GPIO_PORT 8 +// "SPI1_MOSI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_MOSI_GPIO_PIN 4 +// "SPI1_MOSI_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_MOSI_ALTERNATE_FUNCTION 2 + +// "SPI1_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_SCLK_GPIO_PORT 8 +// "SPI1_SCLK_B" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_SCLK_GPIO_PIN 5 +// "SPI1_SCLK_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_SCLK_ALTERNATE_FUNCTION 2 + +// "SPI1_SS0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SPI1_SS0_GPIO_PORT 6 +// "SPI1_SS0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SPI1_SS0_GPIO_PIN 4 +// "SPI1_SS0_B" GPIO pin alternate function <0-7> +#define BOARD_SPI1_SS0_ALTERNATE_FUNCTION 4 + +// "MW_SPI_MASTER_MISO_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_MISO_GPIO_PORT 9 +// "MW_SPI_MASTER_MISO_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_MISO_GPIO_PIN 2 +// "MW_SPI_MASTER_MISO_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_MISO_ALTERNATE_FUNCTION 3 + +// "MW_SPI_MASTER_MOSI_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_MOSI_GPIO_PORT 9 +// "MW_SPI_MASTER_MOSI_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_MOSI_GPIO_PIN 3 +// "MW_SPI_MASTER_MOSI_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_MOSI_ALTERNATE_FUNCTION 4 + +// "MW_SPI_MASTER_SCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> +// GPIO12 <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_SCLK_GPIO_PORT 9 +// "MW_SPI_MASTER_SCLK_B" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> +// PIN4 <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_SCLK_GPIO_PIN 4 +// "MW_SPI_MASTER_SCLK_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_SCLK_ALTERNATE_FUNCTION 3 + +// "MW_SPI_MASTER_SS0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_MASTER_SS0_GPIO_PORT 9 +// "MW_SPI_MASTER_SS0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_MASTER_SS0_GPIO_PIN 5 +// "MW_SPI_MASTER_SS0_B" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_MASTER_SS0_ALTERNATE_FUNCTION 3 + +// "MW_SPI_SLAVE_MISO_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_MISO_GPIO_PORT 12 +// "MW_SPI_SLAVE_MISO_A"GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_MISO_GPIO_PIN 4 +// "MW_SPI_SLAVE_MISO_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_MISO_ALTERNATE_FUNCTION 2 + +// "MW_SPI_SLAVE_MOSI_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_MOSI_GPIO_PORT 12 +// "MW_SPI_SLAVE_MOSI_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_MOSI_GPIO_PIN 5 +// "MW_SPI_SLAVE_MOSI_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_MOSI_ALTERNATE_FUNCTION 2 + +// "MW_SPI_SLAVE_SCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_SCLK_GPIO_PORT 12 +// "MW_SPI_SLAVE_SCLK_A" SPI slave GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> +// PIN4 <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_SCLK_GPIO_PIN 6 +// "MW_SPI_SLAVE_SCLK_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_SCLK_ALTERNATE_FUNCTION 2 + +// "MW_SPI_SLAVE_SS0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MW_SPI_SLAVE_SS0_GPIO_PORT 12 +// "MW_SPI_SLAVE_SS0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_MW_SPI_SLAVE_SS0_GPIO_PIN 7 +// "MW_SPI_SLAVE_SS0_A" GPIO pin alternate function <0-7> +#define BOARD_MW_SPI_SLAVE_SS0_ALTERNATE_FUNCTION 3 + +// "LPUART_RX_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPUART_RX_GPIO_PORT 7 +// "LPUART_RX_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPUART_RX_GPIO_PIN 6 +// "LPUART_RX_A" GPIO pin alternate function <0-7> +#define BOARD_LPUART_RX_ALTERNATE_FUNCTION 2 + +// "LPUART_TX_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPUART_TX_GPIO_PORT 7 +// "LPUART_TX_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPUART_TX_GPIO_PIN 7 +// "LPUART_TX_A" GPIO pin alternate function <0-7> +#define BOARD_LPUART_TX_ALTERNATE_FUNCTION 2 + +// "CDC_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_PCLK_GPIO_PORT 5 +// "CDC_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_PCLK_GPIO_PIN 3 +// "CDC_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_PCLK_ALTERNATE_FUNCTION 7 + +// "CDC_DE_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_DE_GPIO_PORT 5 +// "CDC_DE_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_DE_GPIO_PIN 4 +// "CDC_DE_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_DE_ALTERNATE_FUNCTION 7 + +// "CDC_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_HSYNC_GPIO_PORT 4 +// "CDC_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_HSYNC_GPIO_PIN 1 +// "CDC_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_HSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_VSYNC_GPIO_PORT 4 +// "CDC_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_VSYNC_GPIO_PIN 0 +// "CDC_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_VSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D0_GPIO_PORT 11 +// "CDC_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D0_GPIO_PIN 0 +// "CDC_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D0_ALTERNATE_FUNCTION 7 + +// "CDC_D1_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D1_GPIO_PORT 8 +// "CDC_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D1_GPIO_PIN 1 +// "CDC_D1_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D1_ALTERNATE_FUNCTION 5 + +// "CDC_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D2_GPIO_PORT 8 +// "CDC_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D2_GPIO_PIN 2 +// "CDC_D2_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D2_ALTERNATE_FUNCTION 6 + +// "CDC_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D3_GPIO_PORT 8 +// "CDC_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D3_GPIO_PIN 3 +// "CDC_D3_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D3_ALTERNATE_FUNCTION 6 + +// "CDC_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D4_GPIO_PORT 8 +// "CDC_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D4_GPIO_PIN 4 +// "CDC_D4_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D4_ALTERNATE_FUNCTION 6 + +// "CDC_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D5_GPIO_PORT 11 +// "CDC_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D5_GPIO_PIN 5 +// "CDC_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D5_ALTERNATE_FUNCTION 7 + +// "CDC_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D6_GPIO_PORT 11 +// "CDC_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D6_GPIO_PIN 6 +// "CDC_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D6_ALTERNATE_FUNCTION 7 + +// "CDC_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D7_GPIO_PORT 11 +// "CDC_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D7_GPIO_PIN 7 +// "CDC_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D7_ALTERNATE_FUNCTION 7 + +// "CDC_D8_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D8_GPIO_PORT 9 +// "CDC_D8_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D8_GPIO_PIN 0 +// "CDC_D8_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D8_ALTERNATE_FUNCTION 5 + +// "CDC_D9_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D9_GPIO_PORT 9 +// "CDC_D9_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D9_GPIO_PIN 1 +// "CDC_D9_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D9_ALTERNATE_FUNCTION 6 + +// "CDC_D10_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D10_GPIO_PORT 9 +// "CDC_D10_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D10_GPIO_PIN 2 +// "CDC_D10_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D10_ALTERNATE_FUNCTION 6 + +// "CDC_D11_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D11_GPIO_PORT 9 +// "CDC_D11_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D11_GPIO_PIN 3 +// "CDC_D11_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D11_ALTERNATE_FUNCTION 6 + +// "CDC_D12_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D12_GPIO_PORT 9 +// "CDC_D12_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D12_GPIO_PIN 4 +// "CDC_D12_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D12_ALTERNATE_FUNCTION 6 + +// "CDC_D13_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D13_GPIO_PORT 12 +// "CDC_D13_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D13_GPIO_PIN 5 +// "CDC_D13_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D13_ALTERNATE_FUNCTION 5 + +// "CDC_D14_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D14_GPIO_PORT 12 +// "CDC_D14_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D14_GPIO_PIN 6 +// "CDC_D14_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D14_ALTERNATE_FUNCTION 5 + +// "CDC_D15_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D15_GPIO_PORT 12 +// "CDC_D15_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D15_GPIO_PIN 7 +// "CDC_D15_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D15_ALTERNATE_FUNCTION 5 + +// "CDC_D16_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D16_GPIO_PORT 13 +// "CDC_D16_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D16_GPIO_PIN 0 +// "CDC_D16_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D16_ALTERNATE_FUNCTION 6 + +// "CDC_D17_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D17_GPIO_PORT 13 +// "CDC_D17_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D17_GPIO_PIN 1 +// "CDC_D17_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D17_ALTERNATE_FUNCTION 5 + +// "CDC_D18_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D18_GPIO_PORT 13 +// "CDC_D18_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D18_GPIO_PIN 2 +// "CDC_D18_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D18_ALTERNATE_FUNCTION 5 + +// "CDC_D19_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D19_GPIO_PORT 13 +// "CDC_D19_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D19_GPIO_PIN 3 +// "CDC_D19_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D19_ALTERNATE_FUNCTION 5 + +// "CDC_D20_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D20_GPIO_PORT 13 +// "CDC_D20_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D20_GPIO_PIN 4 +// "CDC_D20_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D20_ALTERNATE_FUNCTION 5 + +// "CDC_D21_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D21_GPIO_PORT 13 +// "CDC_D21_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D21_GPIO_PIN 5 +// "CDC_D21_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D21_ALTERNATE_FUNCTION 5 + +// "CDC_D22_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D22_GPIO_PORT 13 +// "CDC_D22_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D22_GPIO_PIN 6 +// "CDC_D22_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D22_ALTERNATE_FUNCTION 5 + +// "CDC_D23_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D23_GPIO_PORT 13 +// "CDC_D23_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D23_GPIO_PIN 7 +// "CDC_D23_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D23_ALTERNATE_FUNCTION 5 + +// "CLICKBOARD_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_INT_GPIO_PORT 8 +// "CLICKBOARD_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_INT_GPIO_PIN 1 + +// "CLICKBOARD_RST" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_RST_GPIO_PORT 8 +// "CLICKBOARD_RST" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_RST_GPIO_PIN 3 + +// "ICM42670_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ICM42670_IMU_IRQ_GPIO_PORT 8 +// "ICM42670_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_ICM42670_IMU_IRQ_GPIO_PIN 5 + +// "BMI323_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_BMI323_IMU_IRQ_GPIO_PORT 8 +// "BMI323_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_BMI323_IMU_IRQ_GPIO_PIN 4 + +// "CAMERA_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_RESET_GPIO_PORT 9 +// "CAMERA_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_RESET_GPIO_PIN 1 + +// "CAMERA_FLASH" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_FLASH_GPIO_PORT 9 +// "CAMERA_FLASH" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_FLASH_GPIO_PIN 2 + +// "CAMERA_TRIGGER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_TRIGGER_GPIO_PORT 9 +// "CAMERA_TRIGGER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_TRIGGER_GPIO_PIN 3 + +// "TOUCH_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_INT_GPIO_PORT 9 +// "TOUCH_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_TOUCH_INT_GPIO_PIN 4 + +// "LEDRGB0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_B_GPIO_PORT 12 +// "LEDRGB0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_B_GPIO_PIN 0 +// "LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_R" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_R_GPIO_PORT 12 +// "LEDRGB0_R" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_R_GPIO_PIN 3 +// "LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_G" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_G_GPIO_PORT 7 +// "LEDRGB0_G" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_G_GPIO_PIN 4 +// "LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_UT_ALTERNATE_FUNCTION 6 + +// "JOY_SW_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_A_GPIO_PORT 15 +// "JOY_SW_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_A_GPIO_PIN 0 + +// "JOY_SW_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_B_GPIO_PORT 15 +// "JOY_SW_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_B_GPIO_PIN 1 + +// "JOY_SW_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_C_GPIO_PORT 15 +// "JOY_SW_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_C_GPIO_PIN 2 + +// "JOY_SW_D" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_D_GPIO_PORT 15 +// "JOY_SW_D" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_D_GPIO_PIN 3 + +// "JOY_SW_CENTER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_CENTER_GPIO_PORT 15 +// "JOY_SW_CENTER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_JOY_SW_CENTER_GPIO_PIN 4 + +// "LCD_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_RESET_GPIO_PORT 15 +// "LCD_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LCD_RESET_GPIO_PIN 5 + +// "IS66_HYPERRAM_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_IS66_HYPERRAM_RESET_GPIO_PORT 15 +// "IS66_HYPERRAM_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_IS66_HYPERRAM_RESET_GPIO_PIN 6 + +// "PSRAM" OSPI instance number <0> (Do Not Modify!) +#define BOARD_PSRAM_OSPI_INSTANCE 0 + +// OSPI Flash instance number (Do Not Modify!) +#define BOARD_OSPI_FLASH_INSTANCE 1 + +// "OSPI_FLASH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_OSPI_FLASH_RESET_GPIO_PORT 15 +// "OSPI_FLASH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_OSPI_FLASH_RESET_GPIO_PIN 7 + +// "OSPI1_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_OSPI1_RESET_GPIO_PORT 15 +// "OSPI1_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_OSPI1_RESET_GPIO_PIN 7 + +// P0_0 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_0_ADC12_INSTANCE 0 +// P0_0 ADC12 input number (Do Not Modify!) +#define BOARD_P0_0_ADC12_INPUT 0 + +// P0_0 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_0_ADC24_POSITIVE_INPUT 0 + +// P0_0 CMP instance number (Do Not Modify!) +#define BOARD_P0_0_CMP_INSTANCE 0 +// P0_0 CMP input number (Do Not Modify!) +#define BOARD_P0_0_CMP_INPUT 0 + +// P0_1 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_1_ADC12_INSTANCE 0 +// P0_1 ADC12 input number (Do Not Modify!) +#define BOARD_P0_1_ADC12_INPUT 1 + +// P0_1 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_1_ADC24_POSITIVE_INPUT 1 + +// P0_1 CMP instance number (Do Not Modify!) +#define BOARD_P0_1_CMP_INSTANCE 1 +// P0_1 CMP input number (Do Not Modify!) +#define BOARD_P0_1_CMP_INPUT 0 + +// P0_2 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_2_ADC12_INSTANCE 0 +// P0_2 ADC12 input number (Do Not Modify!) +#define BOARD_P0_2_ADC12_INPUT 2 + +// P0_2 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_2_ADC24_POSITIVE_INPUT 2 + +// P0_2 CMP instance number (Do Not Modify!) +#define BOARD_P0_2_CMP_INSTANCE 2 +// P0_2 CMP input number (Do Not Modify!) +#define BOARD_P0_2_CMP_INPUT 0 + +// P0_3 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_3_ADC12_INSTANCE 0 +// P0_3 ADC12 input number (Do Not Modify!) +#define BOARD_P0_3_ADC12_INPUT 3 + +// P0_3 ADC24 positive input number (Do Not Modify!) +#define BOARD_P0_3_ADC24_POSITIVE_INPUT 3 + +// P0_3 CMP instance number (Do Not Modify!) +#define BOARD_P0_3_CMP_INSTANCE 3 +// P0_3 CMP input number (Do Not Modify!) +#define BOARD_P0_3_CMP_INPUT 0 + +// P0_4 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_4_ADC12_INSTANCE 0 +// P0_4 ADC12 input number (Do Not Modify!) +#define BOARD_P0_4_ADC12_INPUT 4 + +// P0_4 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_4_ADC24_NEGATIVE_INPUT 0 + +// P0_4 CMP instance number (Do Not Modify!) +#define BOARD_P0_4_CMP_INSTANCE 0 +// P0_4 CMP input number (Do Not Modify!) +#define BOARD_P0_4_CMP_INPUT 3 + +// P0_5 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_5_ADC12_INSTANCE 0 +// P0_5 ADC12 input number (Do Not Modify!) +#define BOARD_P0_5_ADC12_INPUT 5 + +// P0_5 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_5_ADC24_NEGATIVE_INPUT 1 + +// P0_5 CMP instance number (Do Not Modify!) +#define BOARD_P0_5_CMP_INSTANCE 1 +// P0_5 CMP input number (Do Not Modify!) +#define BOARD_P0_5_CMP_INPUT 3 + +// P0_6 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_6_ADC12_INSTANCE 1 +// P0_6 ADC12 input number (Do Not Modify!) +#define BOARD_P0_6_ADC12_INPUT 0 + +// P0_6 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_6_ADC24_NEGATIVE_INPUT 2 + +// P0_6 CMP instance number (Do Not Modify!) +#define BOARD_P0_6_CMP_INSTANCE 0 +// P0_6 CMP input number (Do Not Modify!) +#define BOARD_P0_6_CMP_INPUT 1 + +// P0_7 ADC12 instance number (Do Not Modify!) +#define BOARD_P0_7_ADC12_INSTANCE 1 +// P0_7 ADC12 input number (Do Not Modify!) +#define BOARD_P0_7_ADC12_INPUT 1 + +// P0_7 ADC24 negative input number (Do Not Modify!) +#define BOARD_P0_7_ADC24_NEGATIVE_INPUT 3 + +// P0_7 CMP instance number (Do Not Modify!) +#define BOARD_P0_7_CMP_INSTANCE 1 +// P0_7 CMP input number (Do Not Modify!) +#define BOARD_P0_7_CMP_INPUT 1 + +// P1_0 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_0_ADC12_INSTANCE 1 +// P1_0 ADC12 input number (Do Not Modify!) +#define BOARD_P1_0_ADC12_INPUT 2 + +// P1_0 CMP instance number (Do Not Modify!) +#define BOARD_P1_0_CMP_INSTANCE 2 +// P1_0 CMP input number (Do Not Modify!) +#define BOARD_P1_0_CMP_INPUT 1 + +// P1_1 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_1_ADC12_INSTANCE 1 +// P1_1 ADC12 input number (Do Not Modify!) +#define BOARD_P1_1_ADC12_INPUT 3 + +// P1_1 CMP instance number (Do Not Modify!) +#define BOARD_P1_1_CMP_INSTANCE 3 +// P1_1 CMP input number (Do Not Modify!) +#define BOARD_P1_1_CMP_INPUT 1 + +// P1_2 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_2_ADC12_INSTANCE 1 +// P1_2 ADC12 input number (Do Not Modify!) +#define BOARD_P1_2_ADC12_INPUT 4 + +// P1_2 CMP instance number (Do Not Modify!) +#define BOARD_P1_2_CMP_INSTANCE 2 +// P1_2 CMP input number (Do Not Modify!) +#define BOARD_P1_2_CMP_INPUT 3 + +// P1_3 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_3_ADC12_INSTANCE 1 +// P1_3 ADC12 input number (Do Not Modify!) +#define BOARD_P1_3_ADC12_INPUT 5 + +// P1_3 CMP instance number (Do Not Modify!) +#define BOARD_P1_3_CMP_INSTANCE 3 +// P1_3 CMP input number (Do Not Modify!) +#define BOARD_P1_3_CMP_INPUT 3 + +// P1_4 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_4_ADC12_INSTANCE 2 +// P1_4 ADC12 input number (Do Not Modify!) +#define BOARD_P1_4_ADC12_INPUT 0 + +// P1_4 CMP instance number (Do Not Modify!) +#define BOARD_P1_4_CMP_INSTANCE 0 +// P1_4 CMP input number (Do Not Modify!) +#define BOARD_P1_4_CMP_INPUT 2 + +// P1_5 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_5_ADC12_INSTANCE 2 +// P1_5 ADC12 input number (Do Not Modify!) +#define BOARD_P1_5_ADC12_INPUT 1 + +// P1_5 CMP instance number (Do Not Modify!) +#define BOARD_P1_5_CMP_INSTANCE 1 +// P1_5 CMP input number (Do Not Modify!) +#define BOARD_P1_5_CMP_INPUT 2 + +// P1_6 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_6_ADC12_INSTANCE 2 +// P1_6 ADC12 input number (Do Not Modify!) +#define BOARD_P1_6_ADC12_INPUT 2 + +// P1_6 CMP instance number (Do Not Modify!) +#define BOARD_P1_6_CMP_INSTANCE 2 +// P1_6 CMP input number (Do Not Modify!) +#define BOARD_P1_6_CMP_INPUT 2 + +// P1_7 ADC12 instance number (Do Not Modify!) +#define BOARD_P1_7_ADC12_INSTANCE 2 +// P1_7 ADC12 input number (Do Not Modify!) +#define BOARD_P1_7_ADC12_INPUT 3 + +// P1_7 CMP instance number (Do Not Modify!) +#define BOARD_P1_7_CMP_INSTANCE 3 +// P1_7 CMP input number (Do Not Modify!) +#define BOARD_P1_7_CMP_INPUT 2 + +// P2_0 ADC12 instance number (Do Not Modify!) +#define BOARD_P2_0_ADC12_INSTANCE 2 +// P2_0 ADC12 input number (Do Not Modify!) +#define BOARD_P2_0_ADC12_INPUT 4 + +// P2_1 ADC12 instance number (Do Not Modify!) +#define BOARD_P2_1_ADC12_INSTANCE 2 +// P2_1 ADC12 input number (Do Not Modify!) +#define BOARD_P2_1_ADC12_INPUT 1 + +// P2_2 DAC12 instance number (Do Not Modify!) +#define BOARD_P2_2_DAC12_INSTANCE 0 +// P2_3 DAC12 instance number (Do Not Modify!) +#define BOARD_P2_3_DAC12_INSTANCE 1 + +#define BOARD_DAC12_INSTANCE BOARD_P2_2_DAC12_INSTANCE + +// P2_4 LPCMP input number (Do Not Modify!) +#define BOARD_P2_4_LPCMP_INPUT 0 + +// P2_5 LPCMP input number (Do Not Modify!) +#define BOARD_P2_5_LPCMP_INPUT 1 + +// P2_6 LPCMP input number (Do Not Modify!) +#define BOARD_P2_6_LPCMP_INPUT 2 + +// P2_7 LPCMP input number (Do Not Modify!) +#define BOARD_P2_7_LPCMP_INPUT 3 + +// "WM8904_CODEC" on I2S presence flag +#define BOARD_WM8904_CODEC_PRESENT 0 + +#if defined(RTSS_HE) +// "DAC Output" I2S instance number <0=> I2S0 <1=> I2S1 <2=> I2S2 <3=> I2S3 LPI2S +#define BOARD_DAC_OUTPUT_I2S_INSTANCE LP + +// "DAC_OUTPUT_SDO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SDO_GPIO_PORT 13 +// "DAC_OUTPUT_SDO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SDO_GPIO_PIN 5 +// "DAC_OUTPUT_SDO" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SDO_ALTERNATE_FUNCTION 2 + +// "DAC_OUTPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_WS_GPIO_PORT 13 +// "DAC_OUTPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_WS_GPIO_PIN 7 +// "DAC_OUTPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_WS_ALTERNATE_FUNCTION 2 + +// "DAC_OUTPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PORT 13 +// "DAC_OUTPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PIN 6 +// "DAC_OUTPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SCLK_ALTERNATE_FUNCTION 2 +#else +// "DAC Output" I2S instance number <0=> I2S0 <1=> I2S1 <2=> I2S2 <3=> I2S3 LPI2S +#define BOARD_DAC_OUTPUT_I2S_INSTANCE 1 + +// "DAC_OUTPUT_SDO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SDO_GPIO_PORT 3 +// "DAC_OUTPUT_SDO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SDO_GPIO_PIN 3 +// "DAC_OUTPUT_SDO" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SDO_ALTERNATE_FUNCTION 3 + +// "DAC_OUTPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_WS_GPIO_PORT 4 +// "DAC_OUTPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_WS_GPIO_PIN 0 +// "DAC_OUTPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_WS_ALTERNATE_FUNCTION 3 + +// "DAC_OUTPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PORT 3 +// "DAC_OUTPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PIN 4 +// "DAC_OUTPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SCLK_ALTERNATE_FUNCTION 4 +#endif + +// "MIC_INPUT_SDI" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MIC_INPUT_SDI_GPIO_PORT 9 +// "MIC_INPUT_SDI" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_MIC_INPUT_SDI_GPIO_PIN 0 +// "MIC_INPUT_SDI" GPIO pin alternate function <0-7> +#define BOARD_MIC_INPUT_SDI_ALTERNATE_FUNCTION 2 + +// "MIC_INPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MIC_INPUT_WS_GPIO_PORT 8 +// "MIC_INPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_MIC_INPUT_WS_GPIO_PIN 7 +// "MIC_INPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_MIC_INPUT_WS_ALTERNATE_FUNCTION 2 + +// "MIC_INPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_MIC_INPUT_SCLK_GPIO_PORT 8 +// "MIC_INPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_MIC_INPUT_SCLK_GPIO_PIN 6 +// "MIC_INPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_MIC_INPUT_SCLK_ALTERNATE_FUNCTION 2 + +// diff --git a/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h new file mode 100644 index 0000000..d4ee83a --- /dev/null +++ b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h @@ -0,0 +1,241 @@ +/* +* Copyright (C) 2026 Alif Semiconductor - All Rights Reserved. +* Use, distribution and modification of this code is permitted under the +* terms stated in the Alif Semiconductor Software License Agreement +* +* You should have received a copy of the Alif Semiconductor Software +* License Agreement with this file. If not, please write to: +* https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ +*/ +/****************************************************************************** +* @file gpios.h +* @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ +* @version v1.0.0 +* @date 2026-2-19 +* @brief Pseudo-static GPIO pin settings for "AI/ML AppKit Gen 2 (AK-E7-AIML)" +* project with AE722F80F55D5LS. +* @bug None. +* @note None. +******************************************************************************/ + +#ifndef __GPIOS_H__ +#define __GPIOS_H__ + +#include +#include "pinconf.h" + +struct gpioconf { + uint8_t port_num; + uint8_t hardware_mode_lptimer_on_lpgpio; + uint8_t initial_state_high; + uint8_t direction_output; + uint8_t debounce_enable; + uint8_t interrupt_enable; + uint8_t interrupt_edge; + uint8_t interrupt_polarity_high_edge_rising; + uint8_t interrupt_both_edge; +}; + +/* GPIO pseudo-static settings generated by Conductor Tool */ + +const struct gpioconf board_gpioconf[] = { + + /* Pin settings (8-bit, 1 bit per pin) for GPIO3 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_3, + 0, + 0, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + 0, + (1 << PIN_3), + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO4 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_4, + 0, + 0, + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO6 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_6, + 0, + 0, + (1 << PIN_6) | (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO7 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_7, + 0, + 0, + (1 << PIN_5) | (1 << PIN_4), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO8 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_8, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + (1 << PIN_5) | (1 << PIN_1), + (1 << PIN_5) | (1 << PIN_1), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO9 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_9, + 0, + (1 << PIN_1), + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + (1 << PIN_4), + (1 << PIN_4), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO12 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_12, + 0, + 0, + (1 << PIN_3) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO14 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_14, + 0, + 0, + (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO15 + 1 - LPGPIO pins driven by LPTIMER + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_15, + 0, + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + }}; + +#endif /* __GPIOS_H__ */ diff --git a/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h.base@2.2.0 b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h.base@2.2.0 new file mode 100644 index 0000000..d4ee83a --- /dev/null +++ b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/gpios.h.base@2.2.0 @@ -0,0 +1,241 @@ +/* +* Copyright (C) 2026 Alif Semiconductor - All Rights Reserved. +* Use, distribution and modification of this code is permitted under the +* terms stated in the Alif Semiconductor Software License Agreement +* +* You should have received a copy of the Alif Semiconductor Software +* License Agreement with this file. If not, please write to: +* https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ +*/ +/****************************************************************************** +* @file gpios.h +* @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ +* @version v1.0.0 +* @date 2026-2-19 +* @brief Pseudo-static GPIO pin settings for "AI/ML AppKit Gen 2 (AK-E7-AIML)" +* project with AE722F80F55D5LS. +* @bug None. +* @note None. +******************************************************************************/ + +#ifndef __GPIOS_H__ +#define __GPIOS_H__ + +#include +#include "pinconf.h" + +struct gpioconf { + uint8_t port_num; + uint8_t hardware_mode_lptimer_on_lpgpio; + uint8_t initial_state_high; + uint8_t direction_output; + uint8_t debounce_enable; + uint8_t interrupt_enable; + uint8_t interrupt_edge; + uint8_t interrupt_polarity_high_edge_rising; + uint8_t interrupt_both_edge; +}; + +/* GPIO pseudo-static settings generated by Conductor Tool */ + +const struct gpioconf board_gpioconf[] = { + + /* Pin settings (8-bit, 1 bit per pin) for GPIO3 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_3, + 0, + 0, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + 0, + (1 << PIN_3), + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO4 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_4, + 0, + 0, + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO6 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_6, + 0, + 0, + (1 << PIN_6) | (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO7 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_7, + 0, + 0, + (1 << PIN_5) | (1 << PIN_4), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO8 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_8, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + (1 << PIN_5) | (1 << PIN_1), + (1 << PIN_5) | (1 << PIN_1), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO9 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_9, + 0, + (1 << PIN_1), + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + (1 << PIN_4), + (1 << PIN_4), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO12 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_12, + 0, + 0, + (1 << PIN_3) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO14 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_14, + 0, + 0, + (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO15 + 1 - LPGPIO pins driven by LPTIMER + 2 - Output pins that will drive logic '1' after startup. Other output pins will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on previous setting. + Other pins are low level/falling edge sensitive 8 - Interrupts generated on both edges. Other + pins behavior is based on previous 2 settings */ + { + PORT_15, + 0, + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + }}; + +#endif /* __GPIOS_H__ */ diff --git a/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h new file mode 100644 index 0000000..a57b664 --- /dev/null +++ b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h @@ -0,0 +1,934 @@ +/* +* Copyright (C) 2026 Alif Semiconductor - All Rights Reserved. +* Use, distribution and modification of this code is permitted under the +* terms stated in the Alif Semiconductor Software License Agreement +* +* You should have received a copy of the Alif Semiconductor Software +* License Agreement with this file. If not, please write to: +* https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ +*/ +/****************************************************************************** +* @file pins.h +* @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ +* @version v1.0.0 +* @date 2026-2-19 +* @brief Pin MUX and Pin Config settings for "AI/ML AppKit Gen 2 (AK-E7-AIML)" +* project with AE722F80F55D5LS. +* @bug None. +* @note None. +******************************************************************************/ + +#ifndef __PINS_H__ +#define __PINS_H__ + +#include +#include "pinconf.h" + +struct pinconf { + uint8_t port; + uint8_t pin; + uint8_t alternate_function; + uint8_t pad_control; +}; + +/* Pin Mux and Config Values generated by Conductor Tool */ + +const struct pinconf board_pinconf[] = { + /* P0_0 on pin R19. Functions: [0]: GPIO0_0, [1]: OSPI0_D0_A, [2]: >>>UART0_RX_A<<<,, [3]: + I3C_SDA_A, [4]: UT0_T0_A [5]: LPCAM_HSYNC_B, [6]: CAM_HSYNC_A, [7]: ANA_S0 */ + /* Selected: UART0_RX_A */ + {PORT_0, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P0_1 on pin R13. Functions: [0]: GPIO0_1, [1]: OSPI0_D1_A, [2]: >>>UART0_TX_A<<<,, [3]: + I3C_SCL_A, [4]: UT0_T1_A [5]: LPCAM_VSYNC_B, [6]: CAM_VSYNC_A, [7]: ANA_S1 */ + /* Selected: UART0_TX_A */ + {PORT_0, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_2 on pin R12. Functions: [0]: >>>GPIO0_2<<<, [1]: OSPI0_D2_A, [2]: UART0_CTS_A, [3]: + I2C0_SDA_A, [4]: UT1_T0_A, [5]: LPCAM_PCLK_B, [6]: CAM_PCLK_A, [7]: ANA_S2 */ + /* Selected: GPIO0_2 */ + {PORT_0, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_3 on pin R11. Functions: [0]: GPIO0_3, [1]: OSPI0_D3_A, [2]: UART0_RTS_A, [3]: I2C0_SCL_A, + [4]: UT1_T1_A, [5]: LPCAM_XVCLK_B, [6]: >>>CAM_XVCLK_A<<<, [7]: ANA_S3 */ + /* Selected: CAM_XVCLK_A. The pack's default is LPCAM_XVCLK_B, the clock of + the HE core's LPCPI; the traffic counter runs the camera on the HP core's + CPI, whose ARX3A0 driver enables CAMERA_PIXCLK (set_cpi_pixel_clk), so the + pin has to carry that clock or the sensor never answers on I2C. */ + {PORT_0, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_4 on pin R10. Functions: [0]: GPIO0_4, [1]: OSPI0_D4_A, [2]: UART1_RX_A, [3]: PDM_D0_A, + [4]: I2C1_SDA_A, [5]: UT2_T0_A [6]: >>>CAN_RXD_B<<<,, [7]: ANA_S4 */ + /* Selected: CAN_RXD_B */ + {PORT_0, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_5 on pin N15. Functions: [0]: GPIO0_5, [1]: OSPI0_D5_A, [2]: UART1_TX_A, [3]: PDM_C0_A, + [4]: I2C1_SCL_A, [5]: UT2_T1_A [6]: >>>CAN_TXD_B<<<,, [7]: ANA_S5 */ + /* Selected: CAN_TXD_B */ + {PORT_0, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_6 on pin P15. Functions: [0]: GPIO0_6, [1]: OSPI0_D6_A, [2]: UART1_CTS_A, [3]: PDM_D1_A, + [4]: I2C2_SCL_A, [5]: UT3_T0_A, [6]: CAN_STBY_B, [7]: >>>ANA_S6<<< */ + /* Selected: ANA_S6 for "CLICKBOARD_ANA". Can be used with ADC121_IN0 (ADC121 input 0); + ADC24_IN2_N (ADC24 differential input 2 negative); CMP0_IN1 (CMP0 input 1) */ + {PORT_0, PIN_6, PINMUX_ALTERNATE_FUNCTION_7, PADCTRL_READ_ENABLE}, + + /* P0_7 on pin R15. Functions: [0]: GPIO0_7, [1]: OSPI0_D7_A, [2]: UART1_RTS_A, [3]: PDM_C1_A, + [4]: I2C2_SDA_A, [5]: UT3_T1_A, [6]: CDC_DE_B, [7]: >>>ANA_S7<<< */ + /* Selected: ANA_S7 for "POTENTIOMETER". Can be used with ADC121_IN1 (ADC121 input 1); + ADC24_IN3_N (ADC24 differential input 3 negative); CMP1_IN1 (CMP1 input 1) */ + {PORT_0, PIN_7, PINMUX_ALTERNATE_FUNCTION_7, PADCTRL_READ_ENABLE}, + + /* P1_0 on pin R14. Functions: [0]: GPIO1_0, [1]: >>>UART2_RX_A<<<, [2]: SPI0_MISO_A, [3]: + I2C3_SDA_A, [4]: UT4_T0_A, [5]: LPCAM_HSYNC_C, [6]: ETH_RXD0_C, [7]: ANA_S8 */ + /* Selected: UART2_RX_A for "UARTA" */ + {PORT_1, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_1 on pin M15. Functions: [0]: GPIO1_1, [1]: >>>UART2_TX_A<<<, [2]: SPI0_MOSI_A, [3]: + I2C3_SCL_A, [4]: UT4_T1_A, [5]: LPCAM_VSYNC_C, [6]: ETH_RXD1_C, [7]: ANA_S9 */ + /* Selected: UART2_TX_A for "UARTA" */ + {PORT_1, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_2 on pin L15. Functions: [0]: GPIO1_2, [1]: >>>UART3_RX_A<<<, [2]: SPI0_SCLK_A, [3]: + I3C_SDA_B, [4]: UT5_T0_A, [5]: LPCAM_PCLK_C, [6]: ETH_RST_C, [7]: ANA_S10 */ + /* Selected: UART3_RX_A for "UARTD" */ + {PORT_1, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_3 on pin K15. Functions: [0]: GPIO1_3, [1]: >>>UART3_TX_A<<<, [2]: SPI0_SS0_A, [3]: + I3C_SCL_B, [4]: UT5_T1_A, [5]: LPCAM_XVCLK_C, [6]: ETH_TXD0_C, [7]: ANA_S11 */ + /* Selected: UART3_TX_A for "UARTD" */ + {PORT_1, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_4 on pin M19. Functions: [0]: GPIO1_4, [1]: OSPI0_SS0_A, [2]: >>>UART0_RX_B<<<, [3]: + SPI0_SS1_A, [4]: UT6_T0_A, [5]: LPCAM_D0_C, [6]: ETH_TXD1_C, [7]: ANA_S12 */ + /* Selected: GPIO1_4 */ + {PORT_1, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_5 on pin L18. Functions: [0]: GPIO1_5, [1]: OSPI0_SS1_A, [2]: >>>UART0_TX_B<<<, [3]: + SPI0_SS2_A, [4]: UT6_T1_A, [5]: LPCAM_D1_C, [6]: ETH_TXEN_C, [7]: ANA_S13 */ + /* Selected: GPIO1_5 */ + {PORT_1, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_6 on pin L19. Functions: [0]: GPIO1_6, [1]: >>>OSPI0_RXDS_B<<<, [2]: UART1_RX_B, [3]: + I2S0_SDI_A, [4]: UT7_T0_A, [5]: LPCAM_D2_C, [6]: ETH_IRQ_C, [7]: ANA_S14 */ + /* Selected: OSPI0_RXDS_B for "ISSI RAM" */ + {PORT_1, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_0 on pin K19. Functions: [0]: GPIO2_0, [1]: >>>OSPI0_D0_B<<<, [2]: UART2_RX_B, [3]: + LPPDM_D0_A, [4]: UT8_T0_A, [5]: LPCAM_D4_C, [6]: ETH_MDIO_C, [7]: ANA_S16 */ + /* Selected: OSPI0_D0_B for "ISSI RAM" */ + {PORT_2, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_1 on pin K18. Functions: [0]: GPIO2_1, [1]: >>>OSPI0_D1_B<<<, [2]: UART2_TX_B, [3]: + LPPDM_C0_A, [4]: UT8_T1_A, [5]: LPCAM_D5_C, [6]: ETH_MDC_C, [7]: ANA_S17 */ + /* Selected: OSPI0_D1_B for "ISSI RAM" */ + {PORT_2, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_2 on pin J15. Functions: [0]: GPIO2_2, [1]: >>>OSPI0_D2_B<<<, [2]: UART3_RX_B, [3]: + LPPDM_D1_A, [4]: UT9_T0_A, [5]: LPCAM_D6_C, [6]: ETH_CRS_DV_C, [7]: ANA_S18 */ + /* Selected: OSPI0_D2_B for "ISSI RAM" */ + {PORT_2, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_3 on pin H15. Functions: [0]: GPIO2_3, [1]: >>>OSPI0_D3_B<<<, [2]: UART3_TX_B, [3]: + LPPDM_C1_A, [4]: UT9_T1_A, [5]: LPCAM_D7_C, [6]: CDC_PCLK_B, [7]: ANA_S19 */ + /* Selected: OSPI0_D3_B for "ISSI RAM" */ + {PORT_2, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_4 on pin G19. Functions: [0]: GPIO2_4, [1]: >>>OSPI0_D4_B<<<, [2]: LPI2S_SDI_A, [3]: + SPI1_MISO_A, [4]: UT10_T0_A, [5]: LPCAM_D0_B, [6]: CAM_D0_A, [7]: ANA_S20 */ + /* Selected: OSPI0_D4_B for "ISSI RAM" */ + {PORT_2, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_5 on pin H19. Functions: [0]: GPIO2_5, [1]: >>>OSPI0_D5_B<<<, [2]: LPI2S_SDO_A, [3]: + SPI1_MOSI_A, [4]: UT10_T1_A, [5]: LPCAM_D1_B, [6]: CAM_D1_A, [7]: ANA_S21 */ + /* Selected: OSPI0_D5_B for "ISSI RAM" */ + {PORT_2, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_6 on pin H18. Functions: [0]: GPIO2_6, [1]: >>>OSPI0_D6_B<<<, [2]: LPI2S_SCLK_A, [3]: + SPI1_SCLK_A, [4]: UT11_T0_A, [5]: LPCAM_D2_B, [6]: CAM_D2_A, [7]: ANA_S22 */ + /* Selected: OSPI0_D6_B for "ISSI RAM" */ + {PORT_2, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_7 on pin J19. Functions: [0]: GPIO2_7, [1]: >>>OSPI0_D7_B<<<, [2]: LPI2S_WS_A, [3]: + SPI1_SS0_A, [4]: UT11_T1_A, [5]: LPCAM_D3_B, [6]: CAM_D3_A, [7]: ANA_S23 */ + /* Selected: OSPI0_D7_B for "ISSI RAM" */ + {PORT_2, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_0 on pin B6. Functions: [0]: GPIO3_0, [1]: >>>OSPI0_SCLK_B<<<, [2]: UART4_RX_A, [3]: + PDM_D0_B, [4]: I2S0_SCLK_A, [5]: QEC0_X_A, [6]: LPCAM_D4_B, [7]: CAM_D4_A */ + /* Selected: OSPI0_SCLK_B for "ISSI RAM" */ + {PORT_3, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_1 on pin A6. Functions: [0]: GPIO3_1, [1]: >>>OSPI0_SCLKN_B<<<, [2]: UART4_TX_A, [3]: + PDM_C0_B, [4]: I2S0_WS_A, [5]: QEC0_Y_A, [6]: LPCAM_D5_B, [7]: CAM_D5_A */ + /* Selected: OSPI0_SCLKN_B for "ISSI RAM" */ + {PORT_3, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_2 on pin E2. Functions: [0]: GPIO3_2, [1]: >>>OSPI0_SS0_B<<<, [2]: PDM_D1_B, [3]: + I2S1_SDI_A, [4]: I3C_SDA_C, [5]: QEC0_Z_A, [6]: LPCAM_D6_B, [7]: CAM_D6_A */ + /* Selected: OSPI0_SS0_B for "ISSI RAM" */ + {PORT_3, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_3 on pin G2. Functions: [0]: >>>GPIO3_3<<<, [1]: OSPI0_SS1_B, [2]: PDM_C1_B, [3]: + I2S1_SDO_A, [4]: I3C_SCL_C, [5]: QEC1_X_A, [6]: LPCAM_D7_B, [7]: CAM_D7_A */ + /* Selected: GPIO3_3 for "SD_CARD_DETECT" */ + {PORT_3, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_4 on pin F2. Functions: [0]: GPIO3_4, [1]: OSPI0_RXDS_A, [2]: UART5_RX_A, [3]: LPPDM_C0_B, + [4]: I2S1_SCLK_A, [5]: >>>I2C0_SCL_B<<<, [6]: QEC1_Y_A, [7]: CAM_D8_A */ + /* Selected: I2C0_SCL_B for "Clickboard,Slave" */ + {PORT_3, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_5 on pin F1. Functions: [0]: GPIO3_5, [1]: OSPI0_SCLKN_A, [2]: UART5_TX_A, [3]: + LPPDM_D0_B, [4]: SPI0_SS1_B, [5]: >>>I2C0_SDA_B<<<, [6]: QEC1_Z_A, [7]: CAM_D9_A */ + /* Selected: I2C0_SDA_B for "Clickboard,Slave" */ + {PORT_3, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_6 on pin V5. Functions: [0]: GPIO3_6, [1]: Reserved, [2]: LPUART_CTS_B, [3]: + >>>LPPDM_C1_B<<<, [4]: SPI0_SS2_B, [5]: I2C1_SDA_B, [6]: QEC2_X_A, [7]: CAM_D10_A */ + /* Selected: LPPDM_C1_B for "My LPPDM" */ + {PORT_3, PIN_6, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_7 on pin L8. Functions: [0]: GPIO3_7, [1]: Reserved, [2]: LPUART_RTS_B, [3]: + >>>LPPDM_D1_B<<<, [4]: SPI1_SS1_A, [5]: I2C1_SCL_B, [6]: QEC2_Y_A, [7]: CAM_D11_A */ + /* Selected: LPPDM_D1_B for "My LPPDM" */ + {PORT_3, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_0 on pin F18. Functions: [0]: >>>GPIO4_0<<<, [1]: Reserved, [2]: Reserved, [3]: I2S1_WS_A, + [4]: SPI1_SS2_A, [5]: QEC2_Z_A, [6]: CDC_VSYNC_B, [7]: CAM_D12_A */ + /* Selected: GPIO4_0 for "TOUCH_RESET" */ + {PORT_4, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_1 on pin B19. Functions: [0]: >>>GPIO4_1<<<, [1]: Reserved, [2]: I2S0_SDI_B, [3]: + SPI1_SS3_A, [4]: QEC3_X_A, [5]: SD_CLK_D, [6]: CDC_HSYNC_B, [7]: CAM_D13_A */ + /* Selected: GPIO4_1 for "UTIMER_GPO0" */ + {PORT_4, PIN_1, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_2 on pin C19. Functions: [0]: >>>GPIO4_2<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SDO_B, [4]: SPI2_MISO_A, [5]: QEC3_Y_A, [6]: SD_CMD_D, [7]: CAM_D14_A */ + /* Selected: GPIO4_2 for "UTIMER_GPO1" */ + {PORT_4, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_3 on pin B18. Functions: [0]: >>>GPIO4_3<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SCLK_B, [4]: SPI2_MOSI_A, [5]: QEC3_Z_A, [6]: SD_RST_D, [7]: CAM_D15_A */ + /* Selected: GPIO4_3 for "UTIMER_GPO2" */ + {PORT_4, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_4 on pin B17. Functions: [0]: GPIO4_4, [1]: >>>JTAG_TCK<<<, [2]: I2S0_WS_B, [3]: + SPI2_SCLK_A, [4]: FAULT0_A */ + /* Selected: JTAG_TCK for "My JTAG" */ + {PORT_4, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_5 on pin A19. Functions: [0]: GPIO4_5, [1]: >>>JTAG_TMS<<<, [2]: SPI2_SS0_A, [3]: FAULT1_A + */ + /* Selected: JTAG_TMS for "My JTAG" */ + {PORT_4, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_6 on pin A18. Functions: [0]: GPIO4_6, [1]: >>>JTAG_TDI<<<, [2]: SPI2_SS1_A, [3]: FAULT2_A + */ + /* Selected: JTAG_TDI for "My JTAG" */ + {PORT_4, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_7 on pin B16. Functions: [0]: GPIO4_7, [1]: >>>JTAG_TDO<<<, [2]: SPI2_SS2_A, [3]: FAULT3_A + */ + /* Selected: JTAG_TDO for "My JTAG" */ + {PORT_4, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_0 on pin A16. Functions: [0]: GPIO5_0, [1]: OSPI1_RXDS_A, [2]: UART4_RX_C, [3]: PDM_D2_A, + [4]: SPI0_MISO_B, [5]: I2C2_SDA_B, [6]: UT0_T0_B, [7]: >>>SD_D0_A<<< */ + /* Selected: SD_D0_A for "SDCARD" */ + {PORT_5, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_1 on pin B14. Functions: [0]: GPIO5_1, [1]: OSPI1_SS0_A, [2]: UART4_TX_C, [3]: PDM_D3_A, + [4]: SPI0_MOSI_B, [5]: I2C2_SCL_B, [6]: UT0_T1_B, [7]: >>>SD_D1_A<<< */ + /* Selected: SD_D1_A for "SDCARD" */ + {PORT_5, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_2 on pin E12. Functions: [0]: GPIO5_2, [1]: OSPI1_SCLKN_A, [2]: UART5_RX_C, [3]: PDM_C3_A, + [4]: SPI0_SS0_B, [5]: LPI2C_SCL_B, [6]: UT1_T0_B, [7]: >>>SD_D2_A<<< */ + /* Selected: SD_D2_A for "SDCARD" */ + {PORT_5, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_3 on pin B13. Functions: [0]: GPIO5_3, [1]: OSPI1_SCLK_A, [2]: UART5_TX_C, [3]: + SPI0_SCLK_B, [4]: LPI2C_SDA_B, [5]: UT1_T1_B, [6]: >>>SD_D3_A<<<, [7]: CDC_PCLK_A */ + /* Selected: SD_D3_A for "SDCARD" */ + {PORT_5, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_4 on pin E11. Functions: [0]: GPIO5_4, [1]: OSPI1_SS1_A, [2]: UART3_CTS_A, [3]: + >>>PDM_D2_B<<<, [4]: SPI0_SS3_A, [5]: UT2_T0_B, [6]: SD_D4_A, [7]: CDC_DE_A */ + /* Selected: PDM_D2_B for "PDM MIC" */ + {PORT_5, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_5 on pin E10. Functions: [0]: GPIO5_5, [1]: >>>OSPI1_SCLK_C<<<, [2]: UART3_RTS_A, [3]: + PDM_D3_B, [4]: UT2_T1_B, [5]: SD_D5_A, [6]: ETH_RXD0_A, [7]: CDC_HSYNC_A */ + /* Selected: OSPI1_SCLK_C for "ISSI Flash" */ + {PORT_5, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_6 on pin B12. Functions: [0]: GPIO5_6, [1]: UART1_CTS_B, [2]: I2C2_SCL_C, [3]: + >>>UT3_T0_B<<<, [4]: SD_D6_A, [5]: ETH_RXD1_A, [6]: CDC_VSYNC_A */ + /* Selected: UT3_T0_B for "Clickboard PWM" */ + {PORT_5, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_7 on pin B11. Functions: [0]: GPIO5_7, [1]: >>>OSPI1_SS0_C<<<, [2]: UART1_RTS_B, [3]: + I2C2_SDA_C, [4]: UT3_T1_B, [5]: SD_D7_A, [6]: ETH_RST_A */ + /* Selected: OSPI1_SS0_C for "ISSI Flash" */ + {PORT_5, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P6_0 on pin A12. Functions: [0]: GPIO6_0, [1]: OSPI0_D0_C, [2]: UART4_DE_A, [3]: PDM_D0_C, + [4]: UT4_T0_B, [5]: SD_D0_D, [6]: >>>ETH_TXD0_A<<< */ + /* Selected: ETH_TXD0_A for "RTL8201" */ + {PORT_6, PIN_0, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_1 on pin E9. Functions: [0]: >>>GPIO6_1<<<, [1]: OSPI0_D1_C, [2]: UART5_DE_A, [3]: + PDM_C0_C, [4]: UT4_T1_B, [5]: SD_D1_D, [6]: ETH_TXD1_A */ + /* Selected: GPIO6_1 for "LCD_BACKLIGHT" */ + {PORT_6, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_2 on pin A11. Functions: [0]: >>>GPIO6_2<<<, [1]: OSPI0_D2_C, [2]: UART2_CTS_A, [3]: + Reserved, [4]: PDM_D1_C, [5]: UT5_T0_B, [6]: SD_D2_D, [7]: ETH_TXEN_A */ + /* Selected: GPIO6_2 for "LEDRGB1_R" */ + {PORT_6, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_3 on pin B10. Functions: [0]: >>>GPIO6_3<<<, [1]: OSPI0_D3_C, [2]: UART2_RTS_A, [3]: + Reserved, [4]: PDM_C1_C, [5]: UT5_T1_B, [6]: SD_D3_D, [7]: ETH_IRQ_A */ + /* Selected: GPIO6_3 for "UTIMER_GPO3" */ + {PORT_6, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_5 on pin E8. Functions: [0]: >>>GPIO6_5<<<, [1]: OSPI0_D4_C, [2]: UART2_CTS_B, [3]: + Reserved, [4]: SPI1_SS0_B, [5]: UT6_T0_B, [6]: SD_D4_D, [7]: ETH_REFCLK_A */ + /* Selected: GPIO6_5 for "LEDRGB1_G" */ + {PORT_6, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_6 on pin E6. Functions: [0]: >>>GPIO6_6<<<, [1]: OSPI0_D6_C, [2]: UART0_CTS_B, [3]: + Reserved, [4]: SPI1_SS2_B, [5]: UT7_T0_B, [6]: SD_D6_D, [7]: ETH_MDC_A */ + /* Selected: GPIO6_6 for "LEDRGB1_B" */ + {PORT_6, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_7 on pin A9. Functions: [0]: GPIO6_7, [1]: OSPI0_D7_C, [2]: UART0_RTS_B, [3]: + >>>PDM_C2_A<<<, [4]: SPI1_SS3_B, [5]: UT7_T1_B, [6]: SD_D7_D, [7]: ETH_CRS_DV_A */ + /* Selected: PDM_C2_A for "PDM MIC" */ + {PORT_6, PIN_7, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_0 on pin B8. Functions: [0]: GPIO7_0, [1]: Reserved, [2]: CMP3_OUT_A, [3]: SPI0_MISO_C, + [4]: I2C0_SDA_C, [5]: UT8_T0_B, [6]: >>>SD_CMD_A<<<, [7]: CAN_RXD_A */ + /* Selected: SD_CMD_A for "SDCARD" */ + {PORT_7, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_1 on pin B3. Functions: [0]: GPIO7_1, [1]: Reserved, [2]: CMP2_OUT_A, [3]: SPI0_MOSI_C, + [4]: I2C0_SCL_C, [5]: UT8_T1_B, [6]: >>>SD_CLK_A<<<, [7]: CAN_TXD_A */ + /* Selected: SD_CLK_A for "SDCARD" */ + {PORT_7, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_2 on pin D1. Functions: [0]: GPIO7_2, [1]: Reserved, [2]: UART3_CTS_B, [3]: CMP1_OUT_A, + [4]: SPI0_SCLK_C, [5]: >>>I2C1_SDA_C<<<, [6]: UT9_T0_B, [7]: SD_RST_A */ + /* Selected: I2C1_SDA_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_3 on pin A8. Functions: [0]: GPIO7_3, [1]: Reserved, [2]: UART3_RTS_B, [3]: CMP0_OUT_A, + [4]: SPI0_SS0_C, [5]: >>>I2C1_SCL_C<<<, [6]: UT9_T1_B, [7]: CAN_STBY_A */ + /* Selected: I2C1_SCL_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_4 on pin T1 {FLEX IO}. Functions: [0]: >>>GPIO7_4<<<, [1]: Reserved, [2]: LPUART_CTS_A, + [3]: LPPDM_C2_A, [4]: LPSPI_MISO_A, [5]: LPI2C_SCL_A, [6]: UT10_T0_B */ + /* Selected: GPIO7_4 for "LEDRGB0_G" */ + {PORT_7, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_5 on pin T2 {FLEX IO}. Functions: [0]: >>>GPIO7_5<<<, [1]: Reserved, [2]: LPUART_RTS_A, + [3]: Reserved, [4]: LPPDM_D2_A, [5]: LPSPI_MOSI_A, [6]: LPI2C_SDA_A, [7]: UT10_T1_B */ + /* Selected: GPIO7_5 for "CAMERA_POWER" */ + {PORT_7, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_6 on pin U3 {FLEX IO}. Functions: [0]: GPIO7_6, [1]: Reserved, [2]: LPUART_RX_A, [3]: + Reserved, [4]: LPPDM_C3_A, [5]: LPSPI_SCLK_A, [6]: >>>I3C_SDA_D<<<, [7]: UT11_T0_B */ + /* Selected: I3C_SDA_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_7 on pin U1 {FLEX IO}. Functions: [0]: GPIO7_7, [1]: Reserved, [2]: LPUART_TX_A, [3]: + Reserved, [4]: LPPDM_D3_A, [5]: LPSPI_SS_A, [6]: >>>I3C_SCL_D<<<, [7]: UT11_T1_B */ + /* Selected: I3C_SCL_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_0 on pin B7. Functions: [0]: GPIO8_0, [1]: >>>OSPI1_SCLKN_C<<<, [2]: AUDIO_CLK_A, [3]: + FAULT0_B, [4]: LPCAM_D0_A, [5]: SD_D0_C, [6]: CDC_D0_A, [7]: CAM_D0_B */ + /* Selected: OSPI1_SCLKN_C for "ISSI Flash" */ + {PORT_8, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P8_1 on pin C2. Functions: [0]: >>>GPIO8_1<<<, [1]: I2S2_SDI_A, [2]: FAULT1_B, [3]: + LPCAM_D1_A, [4]: SD_D1_C, [5]: CDC_D1_A, [6]: CAM_D1_B */ + /* Selected: GPIO8_1 for "CLICKBOARD_INT" */ + {PORT_8, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_3 on pin A7. Functions: [0]: >>>GPIO8_3<<<, [1]: I2S2_SCLK_A, [2]: SPI1_MISO_B, [3]: + FAULT3_B, [4]: LPCAM_D3_A, [5]: SD_D3_C, [6]: CDC_D3_A, [7]: CAM_D3_B */ + /* Selected: GPIO8_3 for "CLICKBOARD_RST" */ + {PORT_8, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_4 on pin B4. Functions: [0]: >>>GPIO8_4<<<, [1]: I2S2_WS_A, [2]: SPI1_MOSI_B, [3]: + QEC0_X_B, [4]: LPCAM_D4_A, [5]: SD_D4_C, [6]: CDC_D4_A, [7]: CAM_D4_B */ + /* Selected: GPIO8_4 for "ICM_IMU_IRQ" */ + {PORT_8, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_5 on pin H1. Functions: [0]: >>>GPIO8_5<<<, [1]: Reserved, [2]: SPI1_SCLK_B, [3]: + QEC0_Y_B, [4]: LPCAM_D5_A, [5]: SD_D5_C, [6]: CDC_D5_A, [7]: CAM_D5_B */ + /* Selected: GPIO8_5 for "BMI_IMU_IRQ" */ + {PORT_8, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_6 on pin J2. Functions: [0]: GPIO8_6, [1]: Reserved, [2]: >>>I2S3_SCLK_B<<<, [3]: + QEC0_Z_B, [4]: LPCAM_D6_A, [5]: SD_D6_C, [6]: CDC_D6_A, [7]: CAM_D6_B */ + /* Selected: I2S3_SCLK_B for "MIC Input" */ + {PORT_8, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_7 on pin J1. Functions: [0]: GPIO8_7, [1]: Reserved, [2]: >>>I2S3_WS_B<<<, [3]: QEC1_X_B, + [4]: LPCAM_D7_A, [5]: SD_D7_C, [6]: CDC_D7_A, [7]: CAM_D7_B */ + /* Selected: I2S3_WS_B for "MIC Input" */ + {PORT_8, PIN_7, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_0 on pin K2. Functions: [0]: GPIO9_0, [1]: Reserved, [2]: >>>I2S3_SDI_B<<<, [3]: QEC1_Y_B, + [4]: SD_CMD_C, [5]: CDC_D8_A, [6]: CAM_D8_B */ + /* Selected: I2S3_SDI_B for "MIC Input" */ + {PORT_9, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_BUS_REPEATER | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_1 on pin K1. Functions: [0]: >>>GPIO9_1<<<, [1]: LPUART_RX_B, [2]: I2S3_SDO_B, [3]: + QEC1_Z_B, [4]: SD_CLK_C, [5]: CDC_D9_A, [6]: CAM_D9_B */ + /* Selected: GPIO9_1 for "CAMERA_RESET" */ + {PORT_9, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_2 on pin G5. Functions: [0]: >>>GPIO9_2<<<, [1]: LPUART_TX_B, [2]: I2S3_SDI_A, [3]: + SPI2_MISO_B, [4]: QEC2_X_B, [5]: SD_RST_C, [6]: CDC_D10_A, [7]: CAM_D10_B */ + /* Selected: GPIO9_2 for "CAMERA_FLASH" */ + {PORT_9, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_3 on pin H5. Functions: [0]: >>>GPIO9_3<<<, [1]: Reserved, [2]: UART7_RX_B, [3]: + I2S3_SDO_A, [4]: SPI2_MOSI_B, [5]: QEC2_Y_B, [6]: CDC_D11_A, [7]: CAM_D11_B */ + /* Selected: GPIO9_3 for "CAMERA_TRIGGER" */ + {PORT_9, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_4 on pin J5. Functions: [0]: >>>GPIO9_4<<<, [1]: UART7_TX_B, [2]: I2S3_SCLK_A, [3]: + SPI2_SCLK_B, [4]: I2C3_SDA_C, [5]: QEC2_Z_B, [6]: CDC_D12_A, [7]: CAM_D12_B */ + /* Selected: GPIO9_4 for "TOUCH_INT" */ + {PORT_9, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_5 on pin L1. Functions: [0]: GPIO9_5, [1]: >>>OSPI1_D0_C<<<, [2]: I2S3_WS_A, [3]: + SPI2_SS0_B, [4]: I2C3_SCL_C, [5]: QEC3_X_B, [6]: CDC_D13_A, [7]: CAM_D13_B */ + /* Selected: OSPI1_D0_C for "ISSI Flash" */ + {PORT_9, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_6 on pin K5. Functions: [0]: GPIO9_6, [1]: >>>OSPI1_D1_C<<<, [2]: AUDIO_CLK_B, [3]: + SPI2_SS1_B, [4]: I2C3_SDA_B, [5]: QEC3_Y_B, [6]: CDC_D14_A, [7]: CAM_D14_B */ + /* Selected: OSPI1_D1_C for "ISSI Flash" */ + {PORT_9, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_7 on pin L5. Functions: [0]: GPIO9_7, [1]: >>>OSPI1_D2_C<<<, [2]: UART7_DE_B, [3]: + SPI2_SS2_B, [4]: I2C3_SCL_B, [5]: QEC3_Z_B, [6]: CDC_D15_A, [7]: CAM_D15_B */ + /* Selected: OSPI1_D2_C for "ISSI Flash" */ + {PORT_9, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_0 on pin M2. Functions: [0]: GPIO10_0, [1]: >>>OSPI1_D3_C<<<, [2]: UART6_DE_B, [3]: + SPI2_SS3_B, [4]: UT0_T0_C, [5]: LPCAM_HSYNC_A, [6]: CDC_D16_A, [7]: CAM_HSYNC_B */ + /* Selected: OSPI1_D3_C for "ISSI Flash" */ + {PORT_10, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_1 on pin M1. Functions: [0]: GPIO10_1, [1]: >>>OSPI1_D4_C<<<, [2]: Reserved, [3]: + LPI2S_SDI_B, [4]: UT0_T1_C, [5]: LPCAM_VSYNC_A, [6]: CDC_D17_A, [7]: CAM_VSYNC_B */ + /* Selected: OSPI1_D4_C for "ISSI Flash" */ + {PORT_10, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_2 on pin N1. Functions: [0]: GPIO10_2, [1]: >>>OSPI1_D5_C<<<, [2]: Reserved, [3]: + LPI2S_SDO_B, [4]: UT1_T0_C, [5]: LPCAM_PCLK_A, [6]: CDC_D18_A, [7]: CAM_PCLK_B */ + /* Selected: OSPI1_D5_C for "ISSI Flash" */ + {PORT_10, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_3 on pin N2. Functions: [0]: GPIO10_3, [1]: >>>OSPI1_D6_C<<<, [2]: Reserved, [3]: + LPI2S_SCLK_B, [4]: UT1_T1_C, [5]: LPCAM_XVCLK_A, [6]: CDC_D19_A, [7]: CAM_XVCLK_B */ + /* Selected: OSPI1_D6_C for "ISSI Flash" */ + {PORT_10, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_4 on pin M5. Functions: [0]: GPIO10_4, [1]: >>>OSPI1_D7_C<<<, [2]: Reserved, [3]: + LPI2S_WS_B, [4]: I2C0_SDA_D, [5]: UT2_T0_C, [6]: ETH_TXD0_B, [7]: CDC_D20_A */ + /* Selected: OSPI1_D7_C for "ISSI Flash" */ + {PORT_10, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_5 on pin N5. Functions: [0]: GPIO10_5, [1]: UART6_RX_A, [2]: I2S2_SDI_B, [3]: + SPI3_MISO_B, [4]: I2C0_SCL_D, [5]: UT2_T1_C, [6]: >>>ETH_TXD1_B<<<, [7]: CDC_D21_A */ + /* Selected: ETH_TXD1_B for "RTL8201" */ + {PORT_10, PIN_5, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_6 on pin P5. Functions: [0]: GPIO10_6, [1]: UART6_TX_A, [2]: I2S2_SDO_B, [3]: + SPI3_MOSI_B, [4]: I2C1_SDA_D, [5]: UT3_T0_C, [6]: >>>ETH_TXEN_B<<<, [7]: CDC_D22_A */ + /* Selected: ETH_TXEN_B for "RTL8201" */ + {PORT_10, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_7 on pin P1. Functions: [0]: GPIO10_7, [1]: UART7_RX_A, [2]: I2S2_SCLK_B, [3]: + SPI3_SCLK_B, [4]: I2C1_SCL_D, [5]: UT3_T1_C, [6]: CDC_D23_A, [7]: >>>OSPI1_RXDS_C<<< */ + /* Selected: OSPI1_RXDS_C for "ISSI Flash" */ + {PORT_10, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P11_0 on pin P2. Functions: [0]: GPIO11_0, [1]: OSPI1_D0_A, [2]: UART7_TX_A, [3]: I2S2_WS_B, + [4]: SPI3_SS0_B, [5]: UT4_T0_C, [6]: >>>ETH_REFCLK_B<<<, [7]: CDC_D0_B */ + /* Selected: ETH_REFCLK_B for "RTL8201" */ + {PORT_11, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_1 on pin R1. Functions: [0]: GPIO11_1, [1]: OSPI1_D1_A, [2]: UART7_DE_A, [3]: SPI3_SS1_B, + [4]: UT4_T1_C, [5]: >>>ETH_MDIO_B<<<, [6]: CDC_D1_B */ + /* Selected: ETH_MDIO_B for "RTL8201" */ + {PORT_11, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_2 on pin R2. Functions: [0]: GPIO11_2, [1]: OSPI1_D2_A, [2]: UART6_DE_A, [3]: LPPDM_C2_B, + [4]: SPI3_SS2_B, [5]: UT5_T0_C, [6]: >>>ETH_MDC_B<<<, [7]: CDC_D2_B */ + /* Selected: ETH_MDC_B for "RTL8201" */ + {PORT_11, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_3 on pin R5. Functions: [0]: GPIO11_3, [1]: OSPI1_D3_A, [2]: UART5_RX_B, [3]: LPPDM_C3_B, + [4]: SPI3_SS3_B, [5]: UT5_T1_C, [6]: >>>ETH_RXD0_B<<<, [7]: CDC_D3_B */ + /* Selected: ETH_RXD0_B for "RTL8201" */ + {PORT_11, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_4 on pin K8. Functions: [0]: GPIO11_4, [1]: OSPI1_D4_A, [2]: UART5_TX_B, [3]: PDM_C2_B, + [4]: LPSPI_MISO_B, [5]: UT6_T0_C, [6]: >>>ETH_RXD1_B<<<, [7]: CDC_D4_B */ + /* Selected: ETH_RXD1_B for "RTL8201" */ + {PORT_11, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_5 on pin J9. Functions: [0]: GPIO11_5, [1]: OSPI1_D5_A, [2]: UART6_RX_B, [3]: PDM_C3_B, + [4]: LPSPI_MOSI_B, [5]: UT6_T1_C, [6]: >>>ETH_CRS_DV_B<<<, [7]: CDC_D5_B */ + /* Selected: ETH_CRS_DV_B for "RTL8201" */ + {PORT_11, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_6 on pin R6. Functions: [0]: GPIO11_6, [1]: OSPI1_D6_A, [2]: UART6_TX_B, [3]: LPPDM_D2_B, + [4]: LPSPI_SCLK_B, [5]: UT7_T0_C, [6]: >>>ETH_RST_B<<<, [7]: CDC_D6_B */ + /* Selected: ETH_RST_B for "RTL8201" */ + {PORT_11, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_7 on pin L9. Functions: [0]: GPIO11_7, [1]: OSPI1_D7_A, [2]: UART5_DE_B, [3]: LPPDM_D3_B, + [4]: LPSPI_SS_B, [5]: UT7_T1_C, [6]: >>>ETH_IRQ_B<<<, [7]: CDC_D7_B */ + /* Selected: ETH_IRQ_B for "RTL8201" */ + {PORT_11, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_0 on pin F19. Functions: [0]: >>>GPIO12_0<<<, [1]: OSPI0_SCLK_C, [2]: AUDIO_CLK_C, [3]: + I2S1_SDI_B, [4]: UT8_T0_C, [5]: CDC_D8_B */ + /* Selected: GPIO12_0 for "LEDRGB0_B" */ + {PORT_12, PIN_0, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_1 on pin E18. Functions: [0]: GPIO12_1, [1]: OSPI0_SCLKN_C, [2]: >>>UART4_RX_B<<<, [3]: + I2S1_SDO_B, [4]: UT8_T1_C, [5]: CDC_D9_B */ + /* Selected: UART4_RX_B for "UARTB" */ + {PORT_12, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_2 on pin E15. Functions: [0]: GPIO12_2, [1]: OSPI0_RXDS_C, [2]: >>>UART4_TX_B<<<, [3]: + I2S1_SCLK_B, [4]: UT9_T0_C, [5]: CDC_D10_B */ + /* Selected: UART4_TX_B for "UARTB" */ + {PORT_12, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_3 on pin D18. Functions: [0]: >>>GPIO12_3<<<, [1]: OSPI0_SS0_C, [2]: UART4_DE_B, [3]: + I2S1_WS_B, [4]: UT9_T1_C, [5]: CDC_D11_B */ + /* Selected: GPIO12_3 for "LEDRGB0_R" */ + {PORT_12, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_4 on pin F5. Functions: [0]: GPIO12_4, [1]: OSPI0_SS1_C, [2]: SPI3_MISO_A, [3]: + UT10_T0_C, [4]: >>>CAN_RXD_C<<<, [5]: CDC_D12_B */ + /* Selected: CAN_RXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_5 on pin A10. Functions: [0]: GPIO12_5, [1]: Reserved, [2]: SPI3_MOSI_A, [3]: UT10_T1_C, + [4]: >>>CAN_TXD_C<<<, [5]: CDC_D13_B */ + /* Selected: CAN_TXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_6 on pin E5. Functions: [0]: GPIO12_6, [1]: Reserved, [2]: SPI3_SCLK_A, [3]: UT11_T0_C, + [4]: >>>CAN_STBY_C<<<, [5]: CDC_D14_B */ + /* Selected: CAN_STBY_C for "CAN Transceiver" */ + {PORT_12, PIN_6, PINMUX_ALTERNATE_FUNCTION_4, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_0 on pin G18. Functions: [0]: GPIO13_0, [1]: OSPI1_D0_B, [2]: Reserved, [3]: SPI3_SS1_A, + [4]: >>>QEC0_X_C<<<, [5]: SD_D0_B, [6]: CDC_D16_B */ + /* Selected: QEC0_X_C for "Encoder" */ + {PORT_13, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_1 on pin G15. Functions: [0]: GPIO13_1, [1]: OSPI1_D1_B, [2]: SPI3_SS2_A, [3]: + >>>QEC0_Y_C<<<, [4]: SD_D1_B, [5]: CDC_D17_B */ + /* Selected: QEC0_Y_C for "Encoder" */ + {PORT_13, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_2 on pin F15. Functions: [0]: GPIO13_2, [1]: OSPI1_D2_B, [2]: SPI3_SS3_A, [3]: + >>>QEC0_Z_C<<<, [4]: SD_D2_B, [5]: CDC_D18_B */ + /* Selected: QEC0_Z_C for "Encoder" */ + {PORT_13, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_4 on pin E14. Functions: [0]: GPIO13_4, [1]: OSPI1_D4_B, [2]: >>>LPI2S_SDI_C<<<, [3]: + QEC1_Y_C, [4]: SD_D4_B, [5]: CDC_D20_B */ + /* Selected: LPI2S_SDI_C for "My LPI2S" */ + {PORT_13, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_5 on pin A17. Functions: [0]: GPIO13_5, [1]: OSPI1_D5_B, [2]: >>>LPI2S_SDO_C<<<, [3]: + QEC1_Z_C, [4]: SD_D5_B, [5]: CDC_D21_B */ + /* Selected: LPI2S_SDO_C for "My LPI2S" */ + {PORT_13, PIN_5, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_6 on pin B15. Functions: [0]: GPIO13_6, [1]: OSPI1_D6_B, [2]: >>>LPI2S_SCLK_C<<<, [3]: + QEC2_X_C, [4]: SD_D6_B, [5]: CDC_D22_B */ + /* Selected: LPI2S_SCLK_C for "My LPI2S" */ + {PORT_13, PIN_6, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_7 on pin A15. Functions: [0]: GPIO13_7, [1]: OSPI1_D7_B, [2]: >>>LPI2S_WS_C<<<, [3]: + QEC2_Y_C, [4]: SD_D7_B, [5]: CDC_D23_B */ + /* Selected: LPI2S_WS_C for "My LPI2S" */ + {PORT_13, PIN_7, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_0 on pin B9. Functions: [0]: GPIO14_0 [1]: OSPI1_SCLK_B, [2]: >>>UART6_RX_C<<<,, [3]: + QEC2_Z_C, [4]: SD_CMD_B, [5]: LFRC_OUT_B */ + /* Selected: UART6_RX_C */ + {PORT_14, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P14_1 on pin H2. Functions: [0]: GPIO14_1 [1]: OSPI1_SCLKN_B, [2]: >>>UART6_TX_C<<<,, [3]: + Reserved, [4]: QEC3_X_C, [5]: SD_CLK_B, [6]: LFXO_OUT_B */ + /* Selected: UART6_TX_C */ + {PORT_14, PIN_1, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_2 on pin G1. Functions: [0]: >>>GPIO14_2<<<, [1]: OSPI1_SS0_B, [2]: UART7_RX_C, [3]: + Reserved, [4]: QEC3_Y_C, [5]: SD_RST_B */ + /* Selected: GPIO14_2 for "QEC_Z_GPO" */ + {PORT_14, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_4 on pin R8. Functions: [0]: GPIO14_4, [1]: >>>CMP3_OUT_B<<<, [2]: SPI1_MISO_C, [3]: + FAULT0_C */ + /* Selected: CMP3_OUT_B for "CMP3_OUT" */ + {PORT_14, PIN_4, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_5 on pin L11. Functions: [0]: GPIO14_5, [1]: >>>CMP2_OUT_B<<<, [2]: SPI1_MOSI_C, [3]: + FAULT1_C */ + /* Selected: CMP2_OUT_B for "CMP2_OUT" */ + {PORT_14, PIN_5, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_6 on pin K12. Functions: [0]: GPIO14_6, [1]: >>>CMP1_OUT_B<<<, [2]: SPI1_SCLK_C, [3]: + FAULT2_C */ + /* Selected: CMP1_OUT_B for "CMP1_OUT" */ + {PORT_14, PIN_6, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_7 on pin L12. Functions: [0]: GPIO14_7, [1]: >>>CMP0_OUT_B<<<, [2]: SPI1_SS0_C, [3]: + FAULT3_C */ + /* Selected: CMP0_OUT_B for "CMP0_OUT" */ + {PORT_14, PIN_7, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_0 on pin V2 {FLEX IO}. Functions: [0]: >>>GPIOV_0<<<, [1]: LPTMR0_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_0 for "JOY_SW_A" */ + {PORT_15, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_1 on pin W2 {FLEX IO}. Functions: [0]: >>>GPIOV_1<<<, [1]: LPTMR1_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_1 for "JOY_SW_B" */ + {PORT_15, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_2 on pin U2 {FLEX IO}. Functions: [0]: >>>GPIOV_2<<<, [1]: LPTMR2_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_2 for "JOY_SW_C" */ + {PORT_15, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_3 on pin V1 {FLEX IO}. Functions: [0]: >>>GPIOV_3<<<, [1]: LPTMR3_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_3 for "JOY_SW_D" */ + {PORT_15, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_4 on pin V3. Functions: [0]: >>>GPIOV_4<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_4 for "JOY_SW_CENTER" */ + {PORT_15, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_5 on pin W4. Functions: [0]: >>>GPIOV_5<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_5 for "LCD_RESET" */ + {PORT_15, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_6 on pin V4. Functions: [0]: >>>GPIOV_6<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_6 for "OSPI0_RESET" */ + {PORT_15, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_7 on pin W5. Functions: [0]: >>>GPIOV_7<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_7 for "OSPI1_RESET" */ + {PORT_15, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA} + +}; + +#endif /* __PINS_H__ */ diff --git a/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h.base@2.2.0 b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h.base@2.2.0 new file mode 100644 index 0000000..259ddda --- /dev/null +++ b/board/AppKit-E7/RTE/BSP/AE722F80F55D5LS_M55_HP/pins.h.base@2.2.0 @@ -0,0 +1,931 @@ +/* +* Copyright (C) 2026 Alif Semiconductor - All Rights Reserved. +* Use, distribution and modification of this code is permitted under the +* terms stated in the Alif Semiconductor Software License Agreement +* +* You should have received a copy of the Alif Semiconductor Software +* License Agreement with this file. If not, please write to: +* https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ +*/ +/****************************************************************************** +* @file pins.h +* @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ +* @version v1.0.0 +* @date 2026-2-19 +* @brief Pin MUX and Pin Config settings for "AI/ML AppKit Gen 2 (AK-E7-AIML)" +* project with AE722F80F55D5LS. +* @bug None. +* @note None. +******************************************************************************/ + +#ifndef __PINS_H__ +#define __PINS_H__ + +#include +#include "pinconf.h" + +struct pinconf { + uint8_t port; + uint8_t pin; + uint8_t alternate_function; + uint8_t pad_control; +}; + +/* Pin Mux and Config Values generated by Conductor Tool */ + +const struct pinconf board_pinconf[] = { + /* P0_0 on pin R19. Functions: [0]: GPIO0_0, [1]: OSPI0_D0_A, [2]: >>>UART0_RX_A<<<,, [3]: + I3C_SDA_A, [4]: UT0_T0_A [5]: LPCAM_HSYNC_B, [6]: CAM_HSYNC_A, [7]: ANA_S0 */ + /* Selected: UART0_RX_A */ + {PORT_0, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P0_1 on pin R13. Functions: [0]: GPIO0_1, [1]: OSPI0_D1_A, [2]: >>>UART0_TX_A<<<,, [3]: + I3C_SCL_A, [4]: UT0_T1_A [5]: LPCAM_VSYNC_B, [6]: CAM_VSYNC_A, [7]: ANA_S1 */ + /* Selected: UART0_TX_A */ + {PORT_0, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_2 on pin R12. Functions: [0]: >>>GPIO0_2<<<, [1]: OSPI0_D2_A, [2]: UART0_CTS_A, [3]: + I2C0_SDA_A, [4]: UT1_T0_A, [5]: LPCAM_PCLK_B, [6]: CAM_PCLK_A, [7]: ANA_S2 */ + /* Selected: GPIO0_2 */ + {PORT_0, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_3 on pin R11. Functions: [0]: GPIO0_3, [1]: OSPI0_D3_A, [2]: UART0_RTS_A, [3]: I2C0_SCL_A, + [4]: UT1_T1_A, [5]: >>>LPCAM_XVCLK_B<<<, [6]: CAM_XVCLK_A, [7]: ANA_S3 */ + /* Selected: LPCAM_XVCLK_B */ + {PORT_0, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_4 on pin R10. Functions: [0]: GPIO0_4, [1]: OSPI0_D4_A, [2]: UART1_RX_A, [3]: PDM_D0_A, + [4]: I2C1_SDA_A, [5]: UT2_T0_A [6]: >>>CAN_RXD_B<<<,, [7]: ANA_S4 */ + /* Selected: CAN_RXD_B */ + {PORT_0, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_5 on pin N15. Functions: [0]: GPIO0_5, [1]: OSPI0_D5_A, [2]: UART1_TX_A, [3]: PDM_C0_A, + [4]: I2C1_SCL_A, [5]: UT2_T1_A [6]: >>>CAN_TXD_B<<<,, [7]: ANA_S5 */ + /* Selected: CAN_TXD_B */ + {PORT_0, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_6 on pin P15. Functions: [0]: GPIO0_6, [1]: OSPI0_D6_A, [2]: UART1_CTS_A, [3]: PDM_D1_A, + [4]: I2C2_SCL_A, [5]: UT3_T0_A, [6]: CAN_STBY_B, [7]: >>>ANA_S6<<< */ + /* Selected: ANA_S6 for "CLICKBOARD_ANA". Can be used with ADC121_IN0 (ADC121 input 0); + ADC24_IN2_N (ADC24 differential input 2 negative); CMP0_IN1 (CMP0 input 1) */ + {PORT_0, PIN_6, PINMUX_ALTERNATE_FUNCTION_7, PADCTRL_READ_ENABLE}, + + /* P0_7 on pin R15. Functions: [0]: GPIO0_7, [1]: OSPI0_D7_A, [2]: UART1_RTS_A, [3]: PDM_C1_A, + [4]: I2C2_SDA_A, [5]: UT3_T1_A, [6]: CDC_DE_B, [7]: >>>ANA_S7<<< */ + /* Selected: ANA_S7 for "POTENTIOMETER". Can be used with ADC121_IN1 (ADC121 input 1); + ADC24_IN3_N (ADC24 differential input 3 negative); CMP1_IN1 (CMP1 input 1) */ + {PORT_0, PIN_7, PINMUX_ALTERNATE_FUNCTION_7, PADCTRL_READ_ENABLE}, + + /* P1_0 on pin R14. Functions: [0]: GPIO1_0, [1]: >>>UART2_RX_A<<<, [2]: SPI0_MISO_A, [3]: + I2C3_SDA_A, [4]: UT4_T0_A, [5]: LPCAM_HSYNC_C, [6]: ETH_RXD0_C, [7]: ANA_S8 */ + /* Selected: UART2_RX_A for "UARTA" */ + {PORT_1, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_1 on pin M15. Functions: [0]: GPIO1_1, [1]: >>>UART2_TX_A<<<, [2]: SPI0_MOSI_A, [3]: + I2C3_SCL_A, [4]: UT4_T1_A, [5]: LPCAM_VSYNC_C, [6]: ETH_RXD1_C, [7]: ANA_S9 */ + /* Selected: UART2_TX_A for "UARTA" */ + {PORT_1, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_2 on pin L15. Functions: [0]: GPIO1_2, [1]: >>>UART3_RX_A<<<, [2]: SPI0_SCLK_A, [3]: + I3C_SDA_B, [4]: UT5_T0_A, [5]: LPCAM_PCLK_C, [6]: ETH_RST_C, [7]: ANA_S10 */ + /* Selected: UART3_RX_A for "UARTD" */ + {PORT_1, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_3 on pin K15. Functions: [0]: GPIO1_3, [1]: >>>UART3_TX_A<<<, [2]: SPI0_SS0_A, [3]: + I3C_SCL_B, [4]: UT5_T1_A, [5]: LPCAM_XVCLK_C, [6]: ETH_TXD0_C, [7]: ANA_S11 */ + /* Selected: UART3_TX_A for "UARTD" */ + {PORT_1, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_4 on pin M19. Functions: [0]: GPIO1_4, [1]: OSPI0_SS0_A, [2]: >>>UART0_RX_B<<<, [3]: + SPI0_SS1_A, [4]: UT6_T0_A, [5]: LPCAM_D0_C, [6]: ETH_TXD1_C, [7]: ANA_S12 */ + /* Selected: GPIO1_4 */ + {PORT_1, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_5 on pin L18. Functions: [0]: GPIO1_5, [1]: OSPI0_SS1_A, [2]: >>>UART0_TX_B<<<, [3]: + SPI0_SS2_A, [4]: UT6_T1_A, [5]: LPCAM_D1_C, [6]: ETH_TXEN_C, [7]: ANA_S13 */ + /* Selected: GPIO1_5 */ + {PORT_1, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_6 on pin L19. Functions: [0]: GPIO1_6, [1]: >>>OSPI0_RXDS_B<<<, [2]: UART1_RX_B, [3]: + I2S0_SDI_A, [4]: UT7_T0_A, [5]: LPCAM_D2_C, [6]: ETH_IRQ_C, [7]: ANA_S14 */ + /* Selected: OSPI0_RXDS_B for "ISSI RAM" */ + {PORT_1, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_0 on pin K19. Functions: [0]: GPIO2_0, [1]: >>>OSPI0_D0_B<<<, [2]: UART2_RX_B, [3]: + LPPDM_D0_A, [4]: UT8_T0_A, [5]: LPCAM_D4_C, [6]: ETH_MDIO_C, [7]: ANA_S16 */ + /* Selected: OSPI0_D0_B for "ISSI RAM" */ + {PORT_2, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_1 on pin K18. Functions: [0]: GPIO2_1, [1]: >>>OSPI0_D1_B<<<, [2]: UART2_TX_B, [3]: + LPPDM_C0_A, [4]: UT8_T1_A, [5]: LPCAM_D5_C, [6]: ETH_MDC_C, [7]: ANA_S17 */ + /* Selected: OSPI0_D1_B for "ISSI RAM" */ + {PORT_2, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_2 on pin J15. Functions: [0]: GPIO2_2, [1]: >>>OSPI0_D2_B<<<, [2]: UART3_RX_B, [3]: + LPPDM_D1_A, [4]: UT9_T0_A, [5]: LPCAM_D6_C, [6]: ETH_CRS_DV_C, [7]: ANA_S18 */ + /* Selected: OSPI0_D2_B for "ISSI RAM" */ + {PORT_2, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_3 on pin H15. Functions: [0]: GPIO2_3, [1]: >>>OSPI0_D3_B<<<, [2]: UART3_TX_B, [3]: + LPPDM_C1_A, [4]: UT9_T1_A, [5]: LPCAM_D7_C, [6]: CDC_PCLK_B, [7]: ANA_S19 */ + /* Selected: OSPI0_D3_B for "ISSI RAM" */ + {PORT_2, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_4 on pin G19. Functions: [0]: GPIO2_4, [1]: >>>OSPI0_D4_B<<<, [2]: LPI2S_SDI_A, [3]: + SPI1_MISO_A, [4]: UT10_T0_A, [5]: LPCAM_D0_B, [6]: CAM_D0_A, [7]: ANA_S20 */ + /* Selected: OSPI0_D4_B for "ISSI RAM" */ + {PORT_2, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_5 on pin H19. Functions: [0]: GPIO2_5, [1]: >>>OSPI0_D5_B<<<, [2]: LPI2S_SDO_A, [3]: + SPI1_MOSI_A, [4]: UT10_T1_A, [5]: LPCAM_D1_B, [6]: CAM_D1_A, [7]: ANA_S21 */ + /* Selected: OSPI0_D5_B for "ISSI RAM" */ + {PORT_2, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_6 on pin H18. Functions: [0]: GPIO2_6, [1]: >>>OSPI0_D6_B<<<, [2]: LPI2S_SCLK_A, [3]: + SPI1_SCLK_A, [4]: UT11_T0_A, [5]: LPCAM_D2_B, [6]: CAM_D2_A, [7]: ANA_S22 */ + /* Selected: OSPI0_D6_B for "ISSI RAM" */ + {PORT_2, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_7 on pin J19. Functions: [0]: GPIO2_7, [1]: >>>OSPI0_D7_B<<<, [2]: LPI2S_WS_A, [3]: + SPI1_SS0_A, [4]: UT11_T1_A, [5]: LPCAM_D3_B, [6]: CAM_D3_A, [7]: ANA_S23 */ + /* Selected: OSPI0_D7_B for "ISSI RAM" */ + {PORT_2, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_0 on pin B6. Functions: [0]: GPIO3_0, [1]: >>>OSPI0_SCLK_B<<<, [2]: UART4_RX_A, [3]: + PDM_D0_B, [4]: I2S0_SCLK_A, [5]: QEC0_X_A, [6]: LPCAM_D4_B, [7]: CAM_D4_A */ + /* Selected: OSPI0_SCLK_B for "ISSI RAM" */ + {PORT_3, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_1 on pin A6. Functions: [0]: GPIO3_1, [1]: >>>OSPI0_SCLKN_B<<<, [2]: UART4_TX_A, [3]: + PDM_C0_B, [4]: I2S0_WS_A, [5]: QEC0_Y_A, [6]: LPCAM_D5_B, [7]: CAM_D5_A */ + /* Selected: OSPI0_SCLKN_B for "ISSI RAM" */ + {PORT_3, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_2 on pin E2. Functions: [0]: GPIO3_2, [1]: >>>OSPI0_SS0_B<<<, [2]: PDM_D1_B, [3]: + I2S1_SDI_A, [4]: I3C_SDA_C, [5]: QEC0_Z_A, [6]: LPCAM_D6_B, [7]: CAM_D6_A */ + /* Selected: OSPI0_SS0_B for "ISSI RAM" */ + {PORT_3, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_3 on pin G2. Functions: [0]: >>>GPIO3_3<<<, [1]: OSPI0_SS1_B, [2]: PDM_C1_B, [3]: + I2S1_SDO_A, [4]: I3C_SCL_C, [5]: QEC1_X_A, [6]: LPCAM_D7_B, [7]: CAM_D7_A */ + /* Selected: GPIO3_3 for "SD_CARD_DETECT" */ + {PORT_3, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_4 on pin F2. Functions: [0]: GPIO3_4, [1]: OSPI0_RXDS_A, [2]: UART5_RX_A, [3]: LPPDM_C0_B, + [4]: I2S1_SCLK_A, [5]: >>>I2C0_SCL_B<<<, [6]: QEC1_Y_A, [7]: CAM_D8_A */ + /* Selected: I2C0_SCL_B for "Clickboard,Slave" */ + {PORT_3, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_5 on pin F1. Functions: [0]: GPIO3_5, [1]: OSPI0_SCLKN_A, [2]: UART5_TX_A, [3]: + LPPDM_D0_B, [4]: SPI0_SS1_B, [5]: >>>I2C0_SDA_B<<<, [6]: QEC1_Z_A, [7]: CAM_D9_A */ + /* Selected: I2C0_SDA_B for "Clickboard,Slave" */ + {PORT_3, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_6 on pin V5. Functions: [0]: GPIO3_6, [1]: Reserved, [2]: LPUART_CTS_B, [3]: + >>>LPPDM_C1_B<<<, [4]: SPI0_SS2_B, [5]: I2C1_SDA_B, [6]: QEC2_X_A, [7]: CAM_D10_A */ + /* Selected: LPPDM_C1_B for "My LPPDM" */ + {PORT_3, PIN_6, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_7 on pin L8. Functions: [0]: GPIO3_7, [1]: Reserved, [2]: LPUART_RTS_B, [3]: + >>>LPPDM_D1_B<<<, [4]: SPI1_SS1_A, [5]: I2C1_SCL_B, [6]: QEC2_Y_A, [7]: CAM_D11_A */ + /* Selected: LPPDM_D1_B for "My LPPDM" */ + {PORT_3, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_0 on pin F18. Functions: [0]: >>>GPIO4_0<<<, [1]: Reserved, [2]: Reserved, [3]: I2S1_WS_A, + [4]: SPI1_SS2_A, [5]: QEC2_Z_A, [6]: CDC_VSYNC_B, [7]: CAM_D12_A */ + /* Selected: GPIO4_0 for "TOUCH_RESET" */ + {PORT_4, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_1 on pin B19. Functions: [0]: >>>GPIO4_1<<<, [1]: Reserved, [2]: I2S0_SDI_B, [3]: + SPI1_SS3_A, [4]: QEC3_X_A, [5]: SD_CLK_D, [6]: CDC_HSYNC_B, [7]: CAM_D13_A */ + /* Selected: GPIO4_1 for "UTIMER_GPO0" */ + {PORT_4, PIN_1, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_2 on pin C19. Functions: [0]: >>>GPIO4_2<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SDO_B, [4]: SPI2_MISO_A, [5]: QEC3_Y_A, [6]: SD_CMD_D, [7]: CAM_D14_A */ + /* Selected: GPIO4_2 for "UTIMER_GPO1" */ + {PORT_4, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_3 on pin B18. Functions: [0]: >>>GPIO4_3<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SCLK_B, [4]: SPI2_MOSI_A, [5]: QEC3_Z_A, [6]: SD_RST_D, [7]: CAM_D15_A */ + /* Selected: GPIO4_3 for "UTIMER_GPO2" */ + {PORT_4, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_4 on pin B17. Functions: [0]: GPIO4_4, [1]: >>>JTAG_TCK<<<, [2]: I2S0_WS_B, [3]: + SPI2_SCLK_A, [4]: FAULT0_A */ + /* Selected: JTAG_TCK for "My JTAG" */ + {PORT_4, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_5 on pin A19. Functions: [0]: GPIO4_5, [1]: >>>JTAG_TMS<<<, [2]: SPI2_SS0_A, [3]: FAULT1_A + */ + /* Selected: JTAG_TMS for "My JTAG" */ + {PORT_4, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_6 on pin A18. Functions: [0]: GPIO4_6, [1]: >>>JTAG_TDI<<<, [2]: SPI2_SS1_A, [3]: FAULT2_A + */ + /* Selected: JTAG_TDI for "My JTAG" */ + {PORT_4, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_7 on pin B16. Functions: [0]: GPIO4_7, [1]: >>>JTAG_TDO<<<, [2]: SPI2_SS2_A, [3]: FAULT3_A + */ + /* Selected: JTAG_TDO for "My JTAG" */ + {PORT_4, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_0 on pin A16. Functions: [0]: GPIO5_0, [1]: OSPI1_RXDS_A, [2]: UART4_RX_C, [3]: PDM_D2_A, + [4]: SPI0_MISO_B, [5]: I2C2_SDA_B, [6]: UT0_T0_B, [7]: >>>SD_D0_A<<< */ + /* Selected: SD_D0_A for "SDCARD" */ + {PORT_5, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_1 on pin B14. Functions: [0]: GPIO5_1, [1]: OSPI1_SS0_A, [2]: UART4_TX_C, [3]: PDM_D3_A, + [4]: SPI0_MOSI_B, [5]: I2C2_SCL_B, [6]: UT0_T1_B, [7]: >>>SD_D1_A<<< */ + /* Selected: SD_D1_A for "SDCARD" */ + {PORT_5, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_2 on pin E12. Functions: [0]: GPIO5_2, [1]: OSPI1_SCLKN_A, [2]: UART5_RX_C, [3]: PDM_C3_A, + [4]: SPI0_SS0_B, [5]: LPI2C_SCL_B, [6]: UT1_T0_B, [7]: >>>SD_D2_A<<< */ + /* Selected: SD_D2_A for "SDCARD" */ + {PORT_5, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_3 on pin B13. Functions: [0]: GPIO5_3, [1]: OSPI1_SCLK_A, [2]: UART5_TX_C, [3]: + SPI0_SCLK_B, [4]: LPI2C_SDA_B, [5]: UT1_T1_B, [6]: >>>SD_D3_A<<<, [7]: CDC_PCLK_A */ + /* Selected: SD_D3_A for "SDCARD" */ + {PORT_5, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_4 on pin E11. Functions: [0]: GPIO5_4, [1]: OSPI1_SS1_A, [2]: UART3_CTS_A, [3]: + >>>PDM_D2_B<<<, [4]: SPI0_SS3_A, [5]: UT2_T0_B, [6]: SD_D4_A, [7]: CDC_DE_A */ + /* Selected: PDM_D2_B for "PDM MIC" */ + {PORT_5, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_5 on pin E10. Functions: [0]: GPIO5_5, [1]: >>>OSPI1_SCLK_C<<<, [2]: UART3_RTS_A, [3]: + PDM_D3_B, [4]: UT2_T1_B, [5]: SD_D5_A, [6]: ETH_RXD0_A, [7]: CDC_HSYNC_A */ + /* Selected: OSPI1_SCLK_C for "ISSI Flash" */ + {PORT_5, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_6 on pin B12. Functions: [0]: GPIO5_6, [1]: UART1_CTS_B, [2]: I2C2_SCL_C, [3]: + >>>UT3_T0_B<<<, [4]: SD_D6_A, [5]: ETH_RXD1_A, [6]: CDC_VSYNC_A */ + /* Selected: UT3_T0_B for "Clickboard PWM" */ + {PORT_5, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_7 on pin B11. Functions: [0]: GPIO5_7, [1]: >>>OSPI1_SS0_C<<<, [2]: UART1_RTS_B, [3]: + I2C2_SDA_C, [4]: UT3_T1_B, [5]: SD_D7_A, [6]: ETH_RST_A */ + /* Selected: OSPI1_SS0_C for "ISSI Flash" */ + {PORT_5, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P6_0 on pin A12. Functions: [0]: GPIO6_0, [1]: OSPI0_D0_C, [2]: UART4_DE_A, [3]: PDM_D0_C, + [4]: UT4_T0_B, [5]: SD_D0_D, [6]: >>>ETH_TXD0_A<<< */ + /* Selected: ETH_TXD0_A for "RTL8201" */ + {PORT_6, PIN_0, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_1 on pin E9. Functions: [0]: >>>GPIO6_1<<<, [1]: OSPI0_D1_C, [2]: UART5_DE_A, [3]: + PDM_C0_C, [4]: UT4_T1_B, [5]: SD_D1_D, [6]: ETH_TXD1_A */ + /* Selected: GPIO6_1 for "LCD_BACKLIGHT" */ + {PORT_6, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_2 on pin A11. Functions: [0]: >>>GPIO6_2<<<, [1]: OSPI0_D2_C, [2]: UART2_CTS_A, [3]: + Reserved, [4]: PDM_D1_C, [5]: UT5_T0_B, [6]: SD_D2_D, [7]: ETH_TXEN_A */ + /* Selected: GPIO6_2 for "LEDRGB1_R" */ + {PORT_6, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_3 on pin B10. Functions: [0]: >>>GPIO6_3<<<, [1]: OSPI0_D3_C, [2]: UART2_RTS_A, [3]: + Reserved, [4]: PDM_C1_C, [5]: UT5_T1_B, [6]: SD_D3_D, [7]: ETH_IRQ_A */ + /* Selected: GPIO6_3 for "UTIMER_GPO3" */ + {PORT_6, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_5 on pin E8. Functions: [0]: >>>GPIO6_5<<<, [1]: OSPI0_D4_C, [2]: UART2_CTS_B, [3]: + Reserved, [4]: SPI1_SS0_B, [5]: UT6_T0_B, [6]: SD_D4_D, [7]: ETH_REFCLK_A */ + /* Selected: GPIO6_5 for "LEDRGB1_G" */ + {PORT_6, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_6 on pin E6. Functions: [0]: >>>GPIO6_6<<<, [1]: OSPI0_D6_C, [2]: UART0_CTS_B, [3]: + Reserved, [4]: SPI1_SS2_B, [5]: UT7_T0_B, [6]: SD_D6_D, [7]: ETH_MDC_A */ + /* Selected: GPIO6_6 for "LEDRGB1_B" */ + {PORT_6, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_7 on pin A9. Functions: [0]: GPIO6_7, [1]: OSPI0_D7_C, [2]: UART0_RTS_B, [3]: + >>>PDM_C2_A<<<, [4]: SPI1_SS3_B, [5]: UT7_T1_B, [6]: SD_D7_D, [7]: ETH_CRS_DV_A */ + /* Selected: PDM_C2_A for "PDM MIC" */ + {PORT_6, PIN_7, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_0 on pin B8. Functions: [0]: GPIO7_0, [1]: Reserved, [2]: CMP3_OUT_A, [3]: SPI0_MISO_C, + [4]: I2C0_SDA_C, [5]: UT8_T0_B, [6]: >>>SD_CMD_A<<<, [7]: CAN_RXD_A */ + /* Selected: SD_CMD_A for "SDCARD" */ + {PORT_7, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_1 on pin B3. Functions: [0]: GPIO7_1, [1]: Reserved, [2]: CMP2_OUT_A, [3]: SPI0_MOSI_C, + [4]: I2C0_SCL_C, [5]: UT8_T1_B, [6]: >>>SD_CLK_A<<<, [7]: CAN_TXD_A */ + /* Selected: SD_CLK_A for "SDCARD" */ + {PORT_7, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_2 on pin D1. Functions: [0]: GPIO7_2, [1]: Reserved, [2]: UART3_CTS_B, [3]: CMP1_OUT_A, + [4]: SPI0_SCLK_C, [5]: >>>I2C1_SDA_C<<<, [6]: UT9_T0_B, [7]: SD_RST_A */ + /* Selected: I2C1_SDA_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_3 on pin A8. Functions: [0]: GPIO7_3, [1]: Reserved, [2]: UART3_RTS_B, [3]: CMP0_OUT_A, + [4]: SPI0_SS0_C, [5]: >>>I2C1_SCL_C<<<, [6]: UT9_T1_B, [7]: CAN_STBY_A */ + /* Selected: I2C1_SCL_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_4 on pin T1 {FLEX IO}. Functions: [0]: >>>GPIO7_4<<<, [1]: Reserved, [2]: LPUART_CTS_A, + [3]: LPPDM_C2_A, [4]: LPSPI_MISO_A, [5]: LPI2C_SCL_A, [6]: UT10_T0_B */ + /* Selected: GPIO7_4 for "LEDRGB0_G" */ + {PORT_7, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_5 on pin T2 {FLEX IO}. Functions: [0]: >>>GPIO7_5<<<, [1]: Reserved, [2]: LPUART_RTS_A, + [3]: Reserved, [4]: LPPDM_D2_A, [5]: LPSPI_MOSI_A, [6]: LPI2C_SDA_A, [7]: UT10_T1_B */ + /* Selected: GPIO7_5 for "CAMERA_POWER" */ + {PORT_7, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_6 on pin U3 {FLEX IO}. Functions: [0]: GPIO7_6, [1]: Reserved, [2]: LPUART_RX_A, [3]: + Reserved, [4]: LPPDM_C3_A, [5]: LPSPI_SCLK_A, [6]: >>>I3C_SDA_D<<<, [7]: UT11_T0_B */ + /* Selected: I3C_SDA_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_7 on pin U1 {FLEX IO}. Functions: [0]: GPIO7_7, [1]: Reserved, [2]: LPUART_TX_A, [3]: + Reserved, [4]: LPPDM_D3_A, [5]: LPSPI_SS_A, [6]: >>>I3C_SCL_D<<<, [7]: UT11_T1_B */ + /* Selected: I3C_SCL_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_0 on pin B7. Functions: [0]: GPIO8_0, [1]: >>>OSPI1_SCLKN_C<<<, [2]: AUDIO_CLK_A, [3]: + FAULT0_B, [4]: LPCAM_D0_A, [5]: SD_D0_C, [6]: CDC_D0_A, [7]: CAM_D0_B */ + /* Selected: OSPI1_SCLKN_C for "ISSI Flash" */ + {PORT_8, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P8_1 on pin C2. Functions: [0]: >>>GPIO8_1<<<, [1]: I2S2_SDI_A, [2]: FAULT1_B, [3]: + LPCAM_D1_A, [4]: SD_D1_C, [5]: CDC_D1_A, [6]: CAM_D1_B */ + /* Selected: GPIO8_1 for "CLICKBOARD_INT" */ + {PORT_8, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_3 on pin A7. Functions: [0]: >>>GPIO8_3<<<, [1]: I2S2_SCLK_A, [2]: SPI1_MISO_B, [3]: + FAULT3_B, [4]: LPCAM_D3_A, [5]: SD_D3_C, [6]: CDC_D3_A, [7]: CAM_D3_B */ + /* Selected: GPIO8_3 for "CLICKBOARD_RST" */ + {PORT_8, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_4 on pin B4. Functions: [0]: >>>GPIO8_4<<<, [1]: I2S2_WS_A, [2]: SPI1_MOSI_B, [3]: + QEC0_X_B, [4]: LPCAM_D4_A, [5]: SD_D4_C, [6]: CDC_D4_A, [7]: CAM_D4_B */ + /* Selected: GPIO8_4 for "ICM_IMU_IRQ" */ + {PORT_8, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_5 on pin H1. Functions: [0]: >>>GPIO8_5<<<, [1]: Reserved, [2]: SPI1_SCLK_B, [3]: + QEC0_Y_B, [4]: LPCAM_D5_A, [5]: SD_D5_C, [6]: CDC_D5_A, [7]: CAM_D5_B */ + /* Selected: GPIO8_5 for "BMI_IMU_IRQ" */ + {PORT_8, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_6 on pin J2. Functions: [0]: GPIO8_6, [1]: Reserved, [2]: >>>I2S3_SCLK_B<<<, [3]: + QEC0_Z_B, [4]: LPCAM_D6_A, [5]: SD_D6_C, [6]: CDC_D6_A, [7]: CAM_D6_B */ + /* Selected: I2S3_SCLK_B for "MIC Input" */ + {PORT_8, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_7 on pin J1. Functions: [0]: GPIO8_7, [1]: Reserved, [2]: >>>I2S3_WS_B<<<, [3]: QEC1_X_B, + [4]: LPCAM_D7_A, [5]: SD_D7_C, [6]: CDC_D7_A, [7]: CAM_D7_B */ + /* Selected: I2S3_WS_B for "MIC Input" */ + {PORT_8, PIN_7, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_0 on pin K2. Functions: [0]: GPIO9_0, [1]: Reserved, [2]: >>>I2S3_SDI_B<<<, [3]: QEC1_Y_B, + [4]: SD_CMD_C, [5]: CDC_D8_A, [6]: CAM_D8_B */ + /* Selected: I2S3_SDI_B for "MIC Input" */ + {PORT_9, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_BUS_REPEATER | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_1 on pin K1. Functions: [0]: >>>GPIO9_1<<<, [1]: LPUART_RX_B, [2]: I2S3_SDO_B, [3]: + QEC1_Z_B, [4]: SD_CLK_C, [5]: CDC_D9_A, [6]: CAM_D9_B */ + /* Selected: GPIO9_1 for "CAMERA_RESET" */ + {PORT_9, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_2 on pin G5. Functions: [0]: >>>GPIO9_2<<<, [1]: LPUART_TX_B, [2]: I2S3_SDI_A, [3]: + SPI2_MISO_B, [4]: QEC2_X_B, [5]: SD_RST_C, [6]: CDC_D10_A, [7]: CAM_D10_B */ + /* Selected: GPIO9_2 for "CAMERA_FLASH" */ + {PORT_9, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_3 on pin H5. Functions: [0]: >>>GPIO9_3<<<, [1]: Reserved, [2]: UART7_RX_B, [3]: + I2S3_SDO_A, [4]: SPI2_MOSI_B, [5]: QEC2_Y_B, [6]: CDC_D11_A, [7]: CAM_D11_B */ + /* Selected: GPIO9_3 for "CAMERA_TRIGGER" */ + {PORT_9, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_4 on pin J5. Functions: [0]: >>>GPIO9_4<<<, [1]: UART7_TX_B, [2]: I2S3_SCLK_A, [3]: + SPI2_SCLK_B, [4]: I2C3_SDA_C, [5]: QEC2_Z_B, [6]: CDC_D12_A, [7]: CAM_D12_B */ + /* Selected: GPIO9_4 for "TOUCH_INT" */ + {PORT_9, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_5 on pin L1. Functions: [0]: GPIO9_5, [1]: >>>OSPI1_D0_C<<<, [2]: I2S3_WS_A, [3]: + SPI2_SS0_B, [4]: I2C3_SCL_C, [5]: QEC3_X_B, [6]: CDC_D13_A, [7]: CAM_D13_B */ + /* Selected: OSPI1_D0_C for "ISSI Flash" */ + {PORT_9, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_6 on pin K5. Functions: [0]: GPIO9_6, [1]: >>>OSPI1_D1_C<<<, [2]: AUDIO_CLK_B, [3]: + SPI2_SS1_B, [4]: I2C3_SDA_B, [5]: QEC3_Y_B, [6]: CDC_D14_A, [7]: CAM_D14_B */ + /* Selected: OSPI1_D1_C for "ISSI Flash" */ + {PORT_9, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_7 on pin L5. Functions: [0]: GPIO9_7, [1]: >>>OSPI1_D2_C<<<, [2]: UART7_DE_B, [3]: + SPI2_SS2_B, [4]: I2C3_SCL_B, [5]: QEC3_Z_B, [6]: CDC_D15_A, [7]: CAM_D15_B */ + /* Selected: OSPI1_D2_C for "ISSI Flash" */ + {PORT_9, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_0 on pin M2. Functions: [0]: GPIO10_0, [1]: >>>OSPI1_D3_C<<<, [2]: UART6_DE_B, [3]: + SPI2_SS3_B, [4]: UT0_T0_C, [5]: LPCAM_HSYNC_A, [6]: CDC_D16_A, [7]: CAM_HSYNC_B */ + /* Selected: OSPI1_D3_C for "ISSI Flash" */ + {PORT_10, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_1 on pin M1. Functions: [0]: GPIO10_1, [1]: >>>OSPI1_D4_C<<<, [2]: Reserved, [3]: + LPI2S_SDI_B, [4]: UT0_T1_C, [5]: LPCAM_VSYNC_A, [6]: CDC_D17_A, [7]: CAM_VSYNC_B */ + /* Selected: OSPI1_D4_C for "ISSI Flash" */ + {PORT_10, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_2 on pin N1. Functions: [0]: GPIO10_2, [1]: >>>OSPI1_D5_C<<<, [2]: Reserved, [3]: + LPI2S_SDO_B, [4]: UT1_T0_C, [5]: LPCAM_PCLK_A, [6]: CDC_D18_A, [7]: CAM_PCLK_B */ + /* Selected: OSPI1_D5_C for "ISSI Flash" */ + {PORT_10, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_3 on pin N2. Functions: [0]: GPIO10_3, [1]: >>>OSPI1_D6_C<<<, [2]: Reserved, [3]: + LPI2S_SCLK_B, [4]: UT1_T1_C, [5]: LPCAM_XVCLK_A, [6]: CDC_D19_A, [7]: CAM_XVCLK_B */ + /* Selected: OSPI1_D6_C for "ISSI Flash" */ + {PORT_10, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_4 on pin M5. Functions: [0]: GPIO10_4, [1]: >>>OSPI1_D7_C<<<, [2]: Reserved, [3]: + LPI2S_WS_B, [4]: I2C0_SDA_D, [5]: UT2_T0_C, [6]: ETH_TXD0_B, [7]: CDC_D20_A */ + /* Selected: OSPI1_D7_C for "ISSI Flash" */ + {PORT_10, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_5 on pin N5. Functions: [0]: GPIO10_5, [1]: UART6_RX_A, [2]: I2S2_SDI_B, [3]: + SPI3_MISO_B, [4]: I2C0_SCL_D, [5]: UT2_T1_C, [6]: >>>ETH_TXD1_B<<<, [7]: CDC_D21_A */ + /* Selected: ETH_TXD1_B for "RTL8201" */ + {PORT_10, PIN_5, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_6 on pin P5. Functions: [0]: GPIO10_6, [1]: UART6_TX_A, [2]: I2S2_SDO_B, [3]: + SPI3_MOSI_B, [4]: I2C1_SDA_D, [5]: UT3_T0_C, [6]: >>>ETH_TXEN_B<<<, [7]: CDC_D22_A */ + /* Selected: ETH_TXEN_B for "RTL8201" */ + {PORT_10, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_7 on pin P1. Functions: [0]: GPIO10_7, [1]: UART7_RX_A, [2]: I2S2_SCLK_B, [3]: + SPI3_SCLK_B, [4]: I2C1_SCL_D, [5]: UT3_T1_C, [6]: CDC_D23_A, [7]: >>>OSPI1_RXDS_C<<< */ + /* Selected: OSPI1_RXDS_C for "ISSI Flash" */ + {PORT_10, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P11_0 on pin P2. Functions: [0]: GPIO11_0, [1]: OSPI1_D0_A, [2]: UART7_TX_A, [3]: I2S2_WS_B, + [4]: SPI3_SS0_B, [5]: UT4_T0_C, [6]: >>>ETH_REFCLK_B<<<, [7]: CDC_D0_B */ + /* Selected: ETH_REFCLK_B for "RTL8201" */ + {PORT_11, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_1 on pin R1. Functions: [0]: GPIO11_1, [1]: OSPI1_D1_A, [2]: UART7_DE_A, [3]: SPI3_SS1_B, + [4]: UT4_T1_C, [5]: >>>ETH_MDIO_B<<<, [6]: CDC_D1_B */ + /* Selected: ETH_MDIO_B for "RTL8201" */ + {PORT_11, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_2 on pin R2. Functions: [0]: GPIO11_2, [1]: OSPI1_D2_A, [2]: UART6_DE_A, [3]: LPPDM_C2_B, + [4]: SPI3_SS2_B, [5]: UT5_T0_C, [6]: >>>ETH_MDC_B<<<, [7]: CDC_D2_B */ + /* Selected: ETH_MDC_B for "RTL8201" */ + {PORT_11, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_3 on pin R5. Functions: [0]: GPIO11_3, [1]: OSPI1_D3_A, [2]: UART5_RX_B, [3]: LPPDM_C3_B, + [4]: SPI3_SS3_B, [5]: UT5_T1_C, [6]: >>>ETH_RXD0_B<<<, [7]: CDC_D3_B */ + /* Selected: ETH_RXD0_B for "RTL8201" */ + {PORT_11, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_4 on pin K8. Functions: [0]: GPIO11_4, [1]: OSPI1_D4_A, [2]: UART5_TX_B, [3]: PDM_C2_B, + [4]: LPSPI_MISO_B, [5]: UT6_T0_C, [6]: >>>ETH_RXD1_B<<<, [7]: CDC_D4_B */ + /* Selected: ETH_RXD1_B for "RTL8201" */ + {PORT_11, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_5 on pin J9. Functions: [0]: GPIO11_5, [1]: OSPI1_D5_A, [2]: UART6_RX_B, [3]: PDM_C3_B, + [4]: LPSPI_MOSI_B, [5]: UT6_T1_C, [6]: >>>ETH_CRS_DV_B<<<, [7]: CDC_D5_B */ + /* Selected: ETH_CRS_DV_B for "RTL8201" */ + {PORT_11, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_6 on pin R6. Functions: [0]: GPIO11_6, [1]: OSPI1_D6_A, [2]: UART6_TX_B, [3]: LPPDM_D2_B, + [4]: LPSPI_SCLK_B, [5]: UT7_T0_C, [6]: >>>ETH_RST_B<<<, [7]: CDC_D6_B */ + /* Selected: ETH_RST_B for "RTL8201" */ + {PORT_11, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_7 on pin L9. Functions: [0]: GPIO11_7, [1]: OSPI1_D7_A, [2]: UART5_DE_B, [3]: LPPDM_D3_B, + [4]: LPSPI_SS_B, [5]: UT7_T1_C, [6]: >>>ETH_IRQ_B<<<, [7]: CDC_D7_B */ + /* Selected: ETH_IRQ_B for "RTL8201" */ + {PORT_11, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_0 on pin F19. Functions: [0]: >>>GPIO12_0<<<, [1]: OSPI0_SCLK_C, [2]: AUDIO_CLK_C, [3]: + I2S1_SDI_B, [4]: UT8_T0_C, [5]: CDC_D8_B */ + /* Selected: GPIO12_0 for "LEDRGB0_B" */ + {PORT_12, PIN_0, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_1 on pin E18. Functions: [0]: GPIO12_1, [1]: OSPI0_SCLKN_C, [2]: >>>UART4_RX_B<<<, [3]: + I2S1_SDO_B, [4]: UT8_T1_C, [5]: CDC_D9_B */ + /* Selected: UART4_RX_B for "UARTB" */ + {PORT_12, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_2 on pin E15. Functions: [0]: GPIO12_2, [1]: OSPI0_RXDS_C, [2]: >>>UART4_TX_B<<<, [3]: + I2S1_SCLK_B, [4]: UT9_T0_C, [5]: CDC_D10_B */ + /* Selected: UART4_TX_B for "UARTB" */ + {PORT_12, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_3 on pin D18. Functions: [0]: >>>GPIO12_3<<<, [1]: OSPI0_SS0_C, [2]: UART4_DE_B, [3]: + I2S1_WS_B, [4]: UT9_T1_C, [5]: CDC_D11_B */ + /* Selected: GPIO12_3 for "LEDRGB0_R" */ + {PORT_12, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_4 on pin F5. Functions: [0]: GPIO12_4, [1]: OSPI0_SS1_C, [2]: SPI3_MISO_A, [3]: + UT10_T0_C, [4]: >>>CAN_RXD_C<<<, [5]: CDC_D12_B */ + /* Selected: CAN_RXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_5 on pin A10. Functions: [0]: GPIO12_5, [1]: Reserved, [2]: SPI3_MOSI_A, [3]: UT10_T1_C, + [4]: >>>CAN_TXD_C<<<, [5]: CDC_D13_B */ + /* Selected: CAN_TXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_6 on pin E5. Functions: [0]: GPIO12_6, [1]: Reserved, [2]: SPI3_SCLK_A, [3]: UT11_T0_C, + [4]: >>>CAN_STBY_C<<<, [5]: CDC_D14_B */ + /* Selected: CAN_STBY_C for "CAN Transceiver" */ + {PORT_12, PIN_6, PINMUX_ALTERNATE_FUNCTION_4, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_0 on pin G18. Functions: [0]: GPIO13_0, [1]: OSPI1_D0_B, [2]: Reserved, [3]: SPI3_SS1_A, + [4]: >>>QEC0_X_C<<<, [5]: SD_D0_B, [6]: CDC_D16_B */ + /* Selected: QEC0_X_C for "Encoder" */ + {PORT_13, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_1 on pin G15. Functions: [0]: GPIO13_1, [1]: OSPI1_D1_B, [2]: SPI3_SS2_A, [3]: + >>>QEC0_Y_C<<<, [4]: SD_D1_B, [5]: CDC_D17_B */ + /* Selected: QEC0_Y_C for "Encoder" */ + {PORT_13, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_2 on pin F15. Functions: [0]: GPIO13_2, [1]: OSPI1_D2_B, [2]: SPI3_SS3_A, [3]: + >>>QEC0_Z_C<<<, [4]: SD_D2_B, [5]: CDC_D18_B */ + /* Selected: QEC0_Z_C for "Encoder" */ + {PORT_13, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_4 on pin E14. Functions: [0]: GPIO13_4, [1]: OSPI1_D4_B, [2]: >>>LPI2S_SDI_C<<<, [3]: + QEC1_Y_C, [4]: SD_D4_B, [5]: CDC_D20_B */ + /* Selected: LPI2S_SDI_C for "My LPI2S" */ + {PORT_13, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_5 on pin A17. Functions: [0]: GPIO13_5, [1]: OSPI1_D5_B, [2]: >>>LPI2S_SDO_C<<<, [3]: + QEC1_Z_C, [4]: SD_D5_B, [5]: CDC_D21_B */ + /* Selected: LPI2S_SDO_C for "My LPI2S" */ + {PORT_13, PIN_5, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_6 on pin B15. Functions: [0]: GPIO13_6, [1]: OSPI1_D6_B, [2]: >>>LPI2S_SCLK_C<<<, [3]: + QEC2_X_C, [4]: SD_D6_B, [5]: CDC_D22_B */ + /* Selected: LPI2S_SCLK_C for "My LPI2S" */ + {PORT_13, PIN_6, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_7 on pin A15. Functions: [0]: GPIO13_7, [1]: OSPI1_D7_B, [2]: >>>LPI2S_WS_C<<<, [3]: + QEC2_Y_C, [4]: SD_D7_B, [5]: CDC_D23_B */ + /* Selected: LPI2S_WS_C for "My LPI2S" */ + {PORT_13, PIN_7, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_0 on pin B9. Functions: [0]: GPIO14_0 [1]: OSPI1_SCLK_B, [2]: >>>UART6_RX_C<<<,, [3]: + QEC2_Z_C, [4]: SD_CMD_B, [5]: LFRC_OUT_B */ + /* Selected: UART6_RX_C */ + {PORT_14, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P14_1 on pin H2. Functions: [0]: GPIO14_1 [1]: OSPI1_SCLKN_B, [2]: >>>UART6_TX_C<<<,, [3]: + Reserved, [4]: QEC3_X_C, [5]: SD_CLK_B, [6]: LFXO_OUT_B */ + /* Selected: UART6_TX_C */ + {PORT_14, PIN_1, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_2 on pin G1. Functions: [0]: >>>GPIO14_2<<<, [1]: OSPI1_SS0_B, [2]: UART7_RX_C, [3]: + Reserved, [4]: QEC3_Y_C, [5]: SD_RST_B */ + /* Selected: GPIO14_2 for "QEC_Z_GPO" */ + {PORT_14, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_4 on pin R8. Functions: [0]: GPIO14_4, [1]: >>>CMP3_OUT_B<<<, [2]: SPI1_MISO_C, [3]: + FAULT0_C */ + /* Selected: CMP3_OUT_B for "CMP3_OUT" */ + {PORT_14, PIN_4, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_5 on pin L11. Functions: [0]: GPIO14_5, [1]: >>>CMP2_OUT_B<<<, [2]: SPI1_MOSI_C, [3]: + FAULT1_C */ + /* Selected: CMP2_OUT_B for "CMP2_OUT" */ + {PORT_14, PIN_5, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_6 on pin K12. Functions: [0]: GPIO14_6, [1]: >>>CMP1_OUT_B<<<, [2]: SPI1_SCLK_C, [3]: + FAULT2_C */ + /* Selected: CMP1_OUT_B for "CMP1_OUT" */ + {PORT_14, PIN_6, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_7 on pin L12. Functions: [0]: GPIO14_7, [1]: >>>CMP0_OUT_B<<<, [2]: SPI1_SS0_C, [3]: + FAULT3_C */ + /* Selected: CMP0_OUT_B for "CMP0_OUT" */ + {PORT_14, PIN_7, PINMUX_ALTERNATE_FUNCTION_1, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_0 on pin V2 {FLEX IO}. Functions: [0]: >>>GPIOV_0<<<, [1]: LPTMR0_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_0 for "JOY_SW_A" */ + {PORT_15, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_1 on pin W2 {FLEX IO}. Functions: [0]: >>>GPIOV_1<<<, [1]: LPTMR1_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_1 for "JOY_SW_B" */ + {PORT_15, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_2 on pin U2 {FLEX IO}. Functions: [0]: >>>GPIOV_2<<<, [1]: LPTMR2_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_2 for "JOY_SW_C" */ + {PORT_15, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_3 on pin V1 {FLEX IO}. Functions: [0]: >>>GPIOV_3<<<, [1]: LPTMR3_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_3 for "JOY_SW_D" */ + {PORT_15, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_4 on pin V3. Functions: [0]: >>>GPIOV_4<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_4 for "JOY_SW_CENTER" */ + {PORT_15, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_5 on pin W4. Functions: [0]: >>>GPIOV_5<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_5 for "LCD_RESET" */ + {PORT_15, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_6 on pin V4. Functions: [0]: >>>GPIOV_6<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_6 for "OSPI0_RESET" */ + {PORT_15, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_7 on pin W5. Functions: [0]: >>>GPIOV_7<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_7 for "OSPI1_RESET" */ + {PORT_15, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA} + +}; + +#endif /* __PINS_H__ */ diff --git a/board/AppKit-E7/RTE/CMSIS/RTX_Config.c b/board/AppKit-E7/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/board/AppKit-E7/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/board/AppKit-E7/RTE/CMSIS/RTX_Config.c.base@5.2.0 b/board/AppKit-E7/RTE/CMSIS/RTX_Config.c.base@5.2.0 new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/board/AppKit-E7/RTE/CMSIS/RTX_Config.c.base@5.2.0 @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/board/AppKit-E7/RTE/CMSIS/RTX_Config.h b/board/AppKit-E7/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..f8756c5 --- /dev/null +++ b/board/AppKit-E7/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/board/AppKit-E7/RTE/CMSIS/RTX_Config.h.base@5.6.1 b/board/AppKit-E7/RTE/CMSIS/RTX_Config.h.base@5.6.1 new file mode 100644 index 0000000..f8756c5 --- /dev/null +++ b/board/AppKit-E7/RTE/CMSIS/RTX_Config.h.base@5.6.1 @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h new file mode 100644 index 0000000..f58ba08 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h @@ -0,0 +1,9675 @@ +/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] +// Configuration settings for Driver_MRAM in component ::Drivers:MRAM +#define RTE_MRAM 1 +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] + +// CPI (Camera) [Driver_CPI] +// Configuration settings for Driver_CPI in component ::Drivers:CPI +#define RTE_CPI 1 +#if RTE_CPI + +// CPI interrupt priority <0-255> +// Defines CPI interrupt priority. +// Default: 0 +#define RTE_CPI_IRQ_PRI 0 + +// CPI CSI halt enable/disable +// <0=> disable +// <1=> enable +// Defines CPI CSI halt enable/disable. +// Default: 0 +#define RTE_CPI_CSI_HALT 0 + +// CPI Row roundup +// <0=> disable +// <1=> enable +// Defines CPI row roundup to 64 bit. +// Default: 0 +#define RTE_CPI_ROW_ROUNDUP 0 + +// CPI FIFO read watermark +// Defines FIFO read watermark. +// Default: 0x8 +#define RTE_CPI_FIFO_READ_WATERMARK 0x8 + +// CPI FIFO write watermark +// Defines CPI FIFO write watermark. +// Default: 0x18 +#define RTE_CPI_FIFO_WRITE_WATERMARK 0x18 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE 0 + +#if (RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_CPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// <4=> 16 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_CODE10ON8 0 + +// Select camera MT9M114 data mask +// <0=> 16 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit +// Defines camera MT9M114 data mask +// Default: 10 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MASK 1 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// CPI (Camera) [Driver_CPI] + +// LPCPI (Camera) [Driver_LPCPI] +// Configuration settings for Driver_LPCPI in component ::Drivers:LPCPI +#define RTE_LPCPI 0 +#if RTE_LPCPI + +// LPCPI interrupt priority <0-255> +// Defines LPCPI interrupt priority. +// Default: 0 +#define RTE_LPCPI_IRQ_PRI 0 + +// LPCPI Row roundup +// <0=> disable +// <1=> enable +// Defines LPCPI row roundup to 64 bit. +// Default: 0 +#define RTE_LPCPI_ROW_ROUNDUP 0 + +// LPCPI FIFO read watermark +// Defines LPCPI FIFO read watermark. +// Default: 0x8 +#define RTE_LPCPI_FIFO_READ_WATERMARK 0x8 + +// LPCPI FIFO write watermark +// Defines LPCPI FIFO write watermark. +// Default: 0x18 +#define RTE_LPCPI_FIFO_WRITE_WATERMARK 0x18 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_CODE10ON8 0 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// LPCPI (Camera) [Driver_LPCPI] + +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] +// Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 +#define RTE_MIPI_CSI2 1 +#if RTE_MIPI_CSI2 + +// Select CSI2 DPHY backend +// Selects CSI2 RX DPHY to be used by Driver_MIPI_CSI2. +// Default: CSI2 RX DPHY +#define RTE_MIPI_CSI2_DPHY_BACKEND 0 + +// CSI pixel clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CSI pixel clock select +// Default: Select AXI clock source +#define RTE_CSI2_PIX_CLK_SEL 0 + +// select IPI mode +// <0=> camera mode +// <1=> controller mode +// defines select IPI mode +// default: camera mode +#define RTE_MIPI_CSI2_IPI_MODE 0 + +// select memory flush +// <0=> manual +// <1=> auto +// defines select memory flush +// default: auto +#define RTE_MIPI_CSI2_MEMFLUSH 1 + +// select sync event mode +// <0=> not trigger by frame start +// <1=> trigger by frame start +// defines select sync event mode +// default : not trigger by frame start +#define RTE_MIPI_CSI2_SYNC_ET_MODE 0 + +// select sync event select +// <0=> auto +// <1=> programmed +// defines select sync event select +// default : programmed +#define RTE_MIPI_CSI2_SYNC_ET_SEL 1 + +// embedded packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use embedded packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_EMBEDDED 0 + +// blanking packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use blanking packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_BLANKING 0 + +// null packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use null packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_NULL 0 + +// line start packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use line start packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_LINE_START 0 + +// video packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use video packets for IPI synchronization events +// default: enable +#define RTE_MIPI_CSI2_EN_VIDEO 1 + +// datatype to overwrite +// select CSI2 Data type to overwrite +// <24=> YUV420_8 +// <25=> YUV420_10 +// <26=> YUV420_8_LEGACY +// <28=> YUV420_8_SHIFT +// <29=> YUV420_10_SHIFT +// <30=> YUV422_8 +// <31=> YUV422_10 +// <32=> RGB444 +// <33=> RGB555 +// <34=> RGB565 +// <35=> RGB666 +// <36=> RGB888 +// <40=> RAW6 +// <41=> RAW7 +// <42=> RAW8 +// <43=> RAW10 +// <44=> RAW12 +// <45=> RAW14 +// <46=> RAW16 +// <48=> USER_DEFINED_1 +// <49=> USER_DEFINED_2 +// <50=> USER_DEFINED_3 +// <51=> USER_DEFINED_4 +// <52=> USER_DEFINED_5 +// <53=> USER_DEFINED_6 +// <54=> USER_DEFINED_7 +// <55=> USER_DEFINED_8 +// defines select CSI2 Data type to be overwrite +// default: RAW10 +#define RTE_MIPI_CSI2_EN_DT 43 + +// datatype to overwrite with programmed datatype +// define if want to use programmed datatype ignoring datatype of the header +// default: 0 +#define RTE_MIPI_CSI2_EN_DT_OVERWRITE 0 + +// Horizontal Synchronism Active Time range <0-2047> +// Defines possible range for selecting horizontal sync active time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HSA_TIME 5 + +// Horizontal Synchronism back porch Time range <0-2047> +// Defines possible range for selecting horizontal sync back porch time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HBP_TIME 10 + +// Horizontal sync delay Time range <0-2047> +// Defines possible range for selecting horizontal sync delay time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HSD_TIME 280 + +// Horizontal Active Time range <0-2047> +// Defines possible range for selecting horizontal active time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HACTIVE_TIME 560 + +// Vertical sync active period range <0-511> +// Defines possible range for selecting vertical sync active period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VSA_LINE 4 + +// Vertical back porch period range <0-511> +// Defines possible range for selecting vertical back porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VBP_LINE 4 + +// Vertical front porch period range <0-511> +// Defines possible range for selecting vertical front porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VFP_LINE 4 + +// Vertical active period range <0-8191> +// Defines possible range for selecting vertical active period +// Default: 560 +#define RTE_MIPI_CSI2_IPI_VACTIVE_LINE 560 + +// CSI2 interrupt priority <0-255> +// Defines CSI2 interrupt priority. +// Default: 0 +#define RTE_MIPI_CSI2_IRQ_PRI 0 + +// ARX3A0 [Driver_ARX3A0] +// Enable/Disable ARX3A0 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable ARX3A0 camera sensor +// default: enable +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera ARX3A0 frame per second +// <5=> 5 FPS +// <40=> 40 FPS +// <60=> 60 FPS +// <90=> 90 FPS +// Defines camera ARX3A0 frame per second +// Default: 90 FPS +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CFG_FPS 90 + +// Select camera ARX3A0 frequency +// Defines camera ARX3A0 frequency +// Default: 400000000 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select ARX3A0 CSI2 Data type +// defines select CSI2 Data type +// default: 43(RAW10) +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_DATA_TYPE 43 + +// select ARX3A0 number of lanes in DPHY +// defines select ARX3A0 number of lanes in DPHY. +// default: 2 two lane +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_N_LANES 2 + +// select ARX3A0 virtual channel ID +// defines select ARX3A0 virtual channel ID. +// default: 0 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_VC_ID 0 + +// select ARX3A0 override CPI color mode +// defines select ARX3A0 override CPI color mode. +// default: 1 (Ensable) +#define RTE_ARX3A0_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select ARX3A0 CPI color mode +// defines select ARX3A0 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_ARX3A0_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select ARX3A0 frame height +// defines select ARX3A0 frame height. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_HEIGHT 560 + +// select ARX3A0 frame width +// defines select ARX3A0 frame width. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_WIDTH 560 + +// Select camera sensor ARX3A0 CSI clock source division [Divisor] <2-511> +// Defines camera sensor ARX3A0 CSI clock source division +// Default: 20 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor ARX3A0 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// ARX3A0 [Driver_ARX3A0] + +// AR0144 [Driver_AR0144] +// Enable/Disable AR0144 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0144 camera sensor +// default: enable +#define RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0144 frequency +// Defines camera AR0144 frequency +// Default: 225000000 +#define RTE_AR0144_CAMERA_SENSOR_CSI_FREQ 225000000 + +// select AR0144 CSI2 Data type +// defines select CSI2 Data type +// default: 44(RAW12) +#define RTE_AR0144_CAMERA_SENSOR_CSI_DATA_TYPE 44 + +// select AR0144 number of lanes in DPHY +// defines select AR0144 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0144_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0144 virtual channel ID +// defines select AR0144 virtual channel ID. +// default: 0 +#define RTE_AR0144_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0144 override CPI color mode +// defines select AR0144 override CPI color mode. +// default: 1 (Ensable) +#define RTE_AR0144_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0144 CPI color mode +// defines select AR0144 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0144_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0144 frame height +// defines select AR0144 frame height. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_HEIGHT 800 + +// select AR0144 frame width +// defines select AR0144 frame width. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_WIDTH 1280 + +// Select camera sensor AR0144 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0144 CSI clock source division +// Default: 20 +#define RTE_AR0144_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0144 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0114 [Driver_AR0114] + +// AR0145 [Driver_AR0145] +// Enable/Disable AR0145 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0145 camera sensor +// default: enable +#define RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0145 frequency +// Defines camera AR0145 frequency +// Default: 400000000 +#define RTE_AR0145_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select AR0145 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2A(RAW8) +#define RTE_AR0145_CAMERA_SENSOR_CSI_DATA_TYPE 0x2A + +// select AR0145 number of lanes in DPHY +// defines select AR0145 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0145_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0145 virtual channel ID +// defines select AR0145 virtual channel ID. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0145 override CPI color mode +// defines select AR0145 override CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select AR0145 CPI color mode +// defines select AR0145 CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +// select AR0145 Image configuration +// Defines camera sensor AR0145 Image configuration +// <0=> 1280x800_Full_1M +// <1=> 640x400_YSum2_XBin2 +// <2=> 640x400_YSkip2_XSkip2 +// <3=> 320x200_YSkip2_XSkip2 +// Default: 0 +#define RTE_AR0145_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// Select camera sensor AR0145 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0145 CSI clock source division +// Default: 16 +#define RTE_AR0145_CAMERA_SENSOR_CSI_CLK_SCR_DIV 16 + +// RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0145 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0145 [Driver_AR0145] + +// AR0246 [Driver_AR0246] +// Enable/Disable AR0246 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0246 camera sensor +// default: enable +#define RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0246 frequency +// Defines camera AR0246 frequency +// Default: 442000000 +#define RTE_AR0246_CAMERA_SENSOR_CSI_FREQ 442000000 + +// select AR0246 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2C(RAW12) +#define RTE_AR0246_CAMERA_SENSOR_CSI_DATA_TYPE 0x2C + +// select AR0246 number of lanes in DPHY +// defines select AR0246 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0246_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0246 virtual channel ID +// defines select AR0246 virtual channel ID. +// default: 0 +#define RTE_AR0246_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0246 override CPI color mode +// defines select AR0246 override CPI color mode. +// default: 1 (Enable) +#define RTE_AR0246_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0246 CPI color mode +// defines select AR0246 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0246_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0246 frame height +// defines select AR0246 frame height. +// default: 472 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_HEIGHT 472 + +// select AR0246 frame width +// defines select AR0246 frame width. +// default: 684 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_WIDTH 684 + +// Select camera sensor AR0246 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0246 CSI clock source division +// Default: 15 +#define RTE_AR0246_CAMERA_SENSOR_CSI_CLK_SCR_DIV 15 + +// RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0246 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0246 [Driver_AR0246] + +// MT9M114_MIPI [Driver_MT9M114_MIPI] +// Enable/Disable MT9M114 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 MIPI camera sensor +// default: enable +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE) + +// Select camera MT9M114 MIPI frequency +// Defines camera MT9M114 MIPI frequency +// Default: 296000000 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_FREQ 320000000 + +// select MT9M114 Image configuration +// Defines camera sensor MT9M114 Image configuration +// <0=> 1288x728_RAW10 +// <1=> 1280x720_RAW8 +// <2=> 1280x720_RGB565 +// <3=> 640x480_RGB565 +// <4=> 320x240_RGB565 +// <5=> 320x320_RGB565 +// Default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 3 + +// select MT9M114 MIPI number of lanes in DPHY +// defines select MT9M114 MIPI number of lanes in DPHY. +// default: 1 one lane +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_N_LANES 1 + +// select MT9M114 MIPI virtual channel ID +// defines select MT9M114 MIPI virtual channel ID. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_VC_ID 0 + +// select MT9M114 MIPI override CPI color mode +// defines select MT9M114 MIPI override CPI color mode. +// default: 0 (Disable) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_OVERRIDE_CPI_COLOR_MODE 0 + +// select MT9M114 MIPI CPI color mode +// defines select MT9M114 MIPI CPI color mode. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CPI_COLOR_MODE 0 + +// Select camera sensor MT9M114 MIPI CSI clock source division [Divisor] <2-511> +// Defines camera sensor MT9M114 MIPI CSI clock source division +// Default: 20 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +// RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE +// Defines camera sensor MT9M114 MIPI i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE 1 + +#endif +// MT9M114_MIPI [Driver_MT9M114_MIPI] + +// HM0360_MIPI [Driver_HM0360_MIPI] +// Enable/Disable HM0360 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable HM0360 MIPI camera sensor +// default: enable +#define RTE_HM0360_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_HM0360_CAMERA_SENSOR_ENABLE) + +// Select camera HM0360 frequency +// Defines camera HM0360 frequency +// Default: 176000000 +#define RTE_HM0360_CAMERA_SENSOR_CSI_FREQ 176000000 + +// Select camera HM0360 frame per second +// <30=> 30 FPS +// <60=> 60 FPS +// Defines camera HM0360 frame per second +// Default: 60 FPS +#define RTE_HM0360_CAMERA_SENSOR_CSI_CFG_FPS 60 + +// Select camera HM0360 context select +// <0=> CONTEXT_A +// <1=> CONTEXT_B +// Defines camera HM0360 context select +// Default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL 0 + +// select HM0360 CSI2 Data type +// defines select CSI2 Data type +// default: 42(RAW8) +#define RTE_HM0360_CAMERA_SENSOR_CSI_DATA_TYPE 42 + +// select HM0360 number of lanes in DPHY +// defines select HM0360 number of lanes in DPHY. +// default: 1 one lane +#define RTE_HM0360_CAMERA_SENSOR_CSI_N_LANES 1 + +// select HM0360 virtual channel ID +// defines select HM0360 virtual channel ID. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_VC_ID 0 + +// select HM0360 override CPI color mode +// defines select HM0360 override CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select HM0360 CPI color mode +// defines select HM0360 CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +#if (RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL == 0) +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 480 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 640 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 240 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 240 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 320 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 320 +#endif + +// RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor HM0360 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// HM0360_MIPI [Driver_HM0360_MIPI] + +// OV5647_MIPI [Driver_OV5647_MIPI] +// Enable/Disable OV5647 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5647 MIPI camera sensor +// default: enable +#define RTE_OV5647_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5647_CAMERA_SENSOR_ENABLE) + +// Select camera OV5647 frequency +// Defines camera OV5647 frequency +// Default: 158000000 +#define RTE_OV5647_CAMERA_SENSOR_CSI_FREQ 158000000 + +// select OV5647 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5647_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5647 number of lanes in DPHY +// defines select OV5647 number of lanes in DPHY. +// default: 2 one lane +#define RTE_OV5647_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5647 virtual channel ID +// defines select OV5647 virtual channel ID. +// default: 0 +#define RTE_OV5647_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5647 override CPI color mode +// defines select OV5647 override CPI color mode. +// default: 1 +#define RTE_OV5647_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5647 CPI color mode +// defines select OV5647 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5647_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select OV5647 frame height +// defines select OV5647 frame height. +// default: 480 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select OV5647 frame width +// defines select OV5647 frame width. +// default: 640 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_WIDTH 640 + +// Select camera sensor OV5647 i2c instance +// Defines camera sensor OV5647 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5647_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// OV5647_MIPI [Driver_OV5647_MIPI] + +// OV5675_MIPI [Driver_OV5675_MIPI] +// Enable/Disable OV5675 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5675 MIPI camera sensor +// default: enable +#define RTE_OV5675_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5675_CAMERA_SENSOR_ENABLE) + +// Select camera OV5675 frequency +// Defines camera OV5675 frequency +// Default: 450000000 +#define RTE_OV5675_CAMERA_SENSOR_CSI_FREQ 450000000 + +// select OV5675 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5675_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5675 number of lanes in DPHY +// defines select OV5675 number of lanes in DPHY. +// default: 2 lane +#define RTE_OV5675_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5675 virtual channel ID +// defines select OV5675 virtual channel ID. +// default: 0 +#define RTE_OV5675_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5675 override CPI color mode +// defines select OV5675 override CPI color mode. +// default: 1 +#define RTE_OV5675_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5675 CPI color mode +// defines select OV5675 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. +// default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif + +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. +// default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif + +// Select camera sensor OV5675 i2c instance +// Defines camera sensor OV5675 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5675_CAMERA_SENSOR_I2C_INSTANCE 1 + +// Select camera sensor OV5675 CSI clock source division [Divisor] <2-511> +// Defines camera sensor OV5675 CSI clock source division +// Default: 20 +#define RTE_OV5675_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +#endif +// OV5675_MIPI [Driver_OV5675_MIPI] + +#endif +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] + +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] +// Configuration settings for Driver_MIPI_DSI in component ::Drivers:MIPI_DSI +#ifndef RTE_MIPI_DSI +#define RTE_MIPI_DSI 1 +#endif // RTE_MIPI_DSI + +#if RTE_MIPI_DSI + +// DPHY PLL input division factor +// Defines DPHY PLL input division factor +// Default: 3 +#define RTE_MIPI_DSI_PLL_INPUT_DIV_FACTOR_N 3 + +// DSI TX escape clock division value. +// Defines DSI TX escape clock division value. +// Default: 2 +#define RTE_MIPI_DSI_TX_ESC_CLK_DIVISION 2 + +// DPI Video Mode +// <0=> NON_BURST SYNC_PULSES +// <1=> NON_BURST SYNC_EVENTS +// <2=> BURST MODE +// Defines DPI Video Mode +// Default:BURST MODE +#define RTE_MIPI_DSI_VID_MODE_TYPE 2 + +// DSI Video number of Chunks +// Defines Number of chunks used to transfer single video packet . +// Default: 0 +#define RTE_MIPI_DSI_VID_NUM_CHUNKS 0 + +// DSI Size of NULL packet +// Defines Size of the NULL packet. +// Default: 0 +#define RTE_MIPI_DSI_VID_NULL_SIZE 0 + +// DSI IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_MIPI_DSI_IRQ_PRI 0 + +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] +// DSI ILI9806E LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9806E LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9806E_PANEL 1 + +#if RTE_MIPI_DSI_ILI9806E_PANEL + +// DSI ILI9806E panel variant +// <0=> E43RB_FW405 +// <1=> E43GB_MW405 +// <2=> E50RA_MW550 +// Defines ILI9806E panel variant +// Default: E43RB_FW405 +#define RTE_ILI9806E_PANEL_VARIANT 1 + +#if (RTE_ILI9806E_PANEL_VARIANT == 0) +#define RTE_ILI9806E_PANEL_E43RB_FW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 1) +#define RTE_ILI9806E_PANEL_E43GB_MW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 2) +#define RTE_ILI9806E_PANEL_E50RA_MW550_EN 1 +#endif + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9806E_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// <5=> 24bit +// Defines Color mode for display panel +// Default: 24bit +#define RTE_ILI9806E_PANEL_DSI_COLOR_MODE 5 + +// Number of data lanes +// <1=> ONE +// <2=> TWO +// Defines Number of data lanes +// Default: TWO +#define RTE_ILI9806E_PANEL_DSI_N_LANES 0x2 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9806E_PANEL_DSI_VC_ID 0 + +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] +#if (RTE_ILI9806E_PANEL_E43RB_FW405_EN || RTE_ILI9806E_PANEL_E43GB_MW405_EN) + +// Panel hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel FW405/MW405 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 5 +#define RTE_PANEL_HBP_TIME 5 + +// Panel FW405/MW405 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 5 +#define RTE_PANEL_HFP_TIME 5 + +// Panel FW405/MW405 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel FW405/MW405 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 2 +#define RTE_PANEL_VSYNC_LINE 2 + +// Panel FW405/MW405 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 10 +#define RTE_PANEL_VBP_LINE 10 + +// Panel FW405/MW405 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 10 +#define RTE_PANEL_VFP_LINE 10 + +// Panel FW405/MW405 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 800 +#define RTE_PANEL_VACTIVE_LINE 800 +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] +#elif RTE_ILI9806E_PANEL_E50RA_MW550_EN + +// Panel MW550 hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel MW550 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 30 +#define RTE_PANEL_HBP_TIME 30 + +// Panel MW550 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 18 +#define RTE_PANEL_HFP_TIME 18 + +// Panel MW550 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel MW550 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 4 +#define RTE_PANEL_VSYNC_LINE 4 + +// Panel MW550 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 30 +#define RTE_PANEL_VBP_LINE 30 + +// Panel MW550 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 20 +#define RTE_PANEL_VFP_LINE 20 + +// Panel MW550 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 854 +#define RTE_PANEL_VACTIVE_LINE 854 +#endif +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] +// DSI ILI9488 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9488 LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9488_PANEL 1 + +#if RTE_MIPI_DSI_ILI9488_PANEL + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9488_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// Defines Color mode for display panel +// Default: 16bit +#define RTE_ILI9488_PANEL_DSI_COLOR_MODE 1 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9488_PANEL_DSI_VC_ID 0 + +// Panel hsync time in pixels +// Defines ILI9488 LCD panel hsync time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HSYNC_TIME 10 + +// Panel ILI9488 hbp time in pixels +// Defines ILI9488 LCD panel hbp time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HBP_TIME 10 + +// Panel ILI9488 hfp time in pixels +// Defines ILI9488 LCD panel hfp time in pixels. +// Default: 40 +#define RTE_ILI9488_PANEL_HFP_TIME 40 + +// Panel ILI9488 hactive pixels +// Defines ILI9488 LCD panel hactive pixels. +// Default: 320 +#define RTE_ILI9488_PANEL_HACTIVE_TIME 320 + +// Panel ILI9488 vsync time in lines +// Defines ILI9488 LCD panel vsync time in lines. +// Default: 2 +#define RTE_ILI9488_PANEL_VSYNC_LINE 2 + +// Panel ILI9488 vbp time in lines +// Defines ILI9488 LCD panel vbp time in lines. +// Default: 16 +#define RTE_ILI9488_PANEL_VBP_LINE 16 + +// Panel ILI9488 vfp time in lines +// Defines ILI9488 LCD panel vfp time in lines. +// Default: 10 +#define RTE_ILI9488_PANEL_VFP_LINE 10 + +// Panel ILI9488 vactive lines +// Defines ILI9488 LCD panel vactive lines. +// Default: 480 +#define RTE_ILI9488_PANEL_VACTIVE_LINE 480 + +#endif +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] + +#endif +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] + +#endif +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] + +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] +// Configuration settings for Driver_Touch_Screen in component ::Drivers:touch screen +#define RTE_TOUCH_SCREEN 1 + +#if RTE_TOUCH_SCREEN + +// GT911 Touch screen +// <0=> DISABLE +// <1=> ENABLE +// Defines GT911 Touch screen +// Default: ENABLE +#define RTE_GT911 1 + +#if RTE_GT911 + +// select active touch points +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// defines select active touch points +// default: 5 +#define RTE_ACTIVE_TOUCH_POINTS 5 + +// RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL +// Defines GT911 Touchscreen i2c slave address selection +// <0x14=> I2C_SLAVE_ADDRESS_HEX_14 +// <0x5D=> I2C_SLAVE_ADDRESS_HEX_5D +// Default: 0x14 +#define RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL 0x14 +#endif + +#endif +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] + +// CDC200 (cdc200) [Driver_CDC200] +// Configuration settings for Driver_CDC200 in component ::Drivers:CDC200 +#define RTE_CDC200 1 + +#if RTE_CDC200 + +// CDC200 IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_CDC200_IRQ_PRI 0 + +// CDC200 clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CDC200 clock select +// Default: Select AXI clock source +#define RTE_CDC200_CLK_SEL 0 + +// CDC200 background color red <0-255> +// Defines CDC200 background color red. +// Default: 0 +#define RTE_CDC200_BGC_RED 0 + +// CDC200 background color green <0-255> +// Defines CDC200 background color green. +// Default: 0 +#define RTE_CDC200_BGC_GREEN 0 + +// CDC200 background color blue <0-255> +// Defines CDC200 background color blue. +// Default: 0 +#define RTE_CDC200_BGC_BLUE 0 + +// CDC200 pixel format +// <0=> ARGB8888 +// <1=> RGB888 +// <2=> RGB565 +//      <3=> RGBA8888 +//      <6=> ARGB1555 +//      <7=> ARGB4444 +// Defines CDC200 pixel format +// Default: RGB888 +#define RTE_CDC200_PIXEL_FORMAT 1 + +// CDC200 Constant alpha <0-255> +// Defines CDC200 constant alpha range from 0 (fully transparent) to 255 or 1.0 (fully opaque). +// Default: 255 +#define RTE_CDC200_CONSTANT_ALPHA 255 + +// CDC200 blending factor +// <0=> CONST_ALPHA +// <1=> PIXEL_ALPHA_X_CONST_ALPHA +// Defines CDC200 blending factor selection. +// Default: PIXEL_ALPHA_X_CONST_ALPHA +#define RTE_CDC200_BLEND_FACTOR 1 + +// CDC200 DPI interface FPS +// Defines CDC200 DPI interface Framrate per second. +// Default: 60 +#define RTE_CDC200_DPI_FPS 60 + +// Parallel ILI6122 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines Parallel ILI6122 LCD PANEL +// Default: ENABLE +#ifndef RTE_ILI6122_PANEL +#define RTE_ILI6122_PANEL 0 +#endif // RTE_ILI6122_PANEL + +#if RTE_ILI6122_PANEL + +// CDC HSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC HSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_HSYNC_ACTIVE_LOW 0 + +// CDC VSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC VSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_VSYNC_ACTIVE_LOW 0 + +// CDC Pixel Clock Output pin active state +// <0=> FEED THROUGH +// <1=> INVERTED +// Defines CDC Pixel Clock pin active state +// Default: FEED THROUGH +#define RTE_ILI6122_PANEL_CDC_PIXCLK_FEED_THROUGH 0 + +// CDC BLANKING pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC BLANKINg pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_BLANK_ACTIVE_LOW 0 + +// Panel hsync time in pixels +// Defines ILI6122 LCD panel hsync time in pixels. +// Default: 1 +#define RTE_PANEL_HSYNC_TIME 1 + +// Panel hbp time in pixels +// Defines ILI6122 LCD panel hbp time in pixels. +// Default: 46 +#define RTE_PANEL_HBP_TIME 46 + +// Panel hfp time in pixels +// Defines ILI6122 LCD panel hfp time in pixels. +// Default: 210 +#define RTE_PANEL_HFP_TIME 210 + +// Panel hactive pixels +// Defines ILI6122 LCD panel hactive pixels. +// Default: 800 +#define RTE_PANEL_HACTIVE_TIME 800 + +// Panel vsync time in lines +// Defines ILI6122 LCD panel vsync time in lines. +// Default: 1 +#define RTE_PANEL_VSYNC_LINE 1 + +// Panel vbp time in lines +// Defines ILI6122 LCD panel vbp time in lines. +// Default: 23 +#define RTE_PANEL_VBP_LINE 23 + +// Panel vfp time in lines +// Defines ILI6122 LCD panel vfp time in lines. +// Default: 22 +#define RTE_PANEL_VFP_LINE 22 + +// Panel vactive lines +// Defines ILI6122 LCD panel vactive lines. +// Default: 480 +#define RTE_PANEL_VACTIVE_LINE 480 +#endif + +#endif +// CDC200 (cdc200) [Driver_CDC200] + +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] +// Configuration settings for Driver_I3C in component ::Drivers:I3C +#define RTE_I3C 1 + +#if RTE_I3C + +// I3C IRQ priority <0-255> +// Defines I3C Interrupt priority +// Default: 0 +#define RTE_I3C_IRQ_PRI 0 + +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] +// Configuration settings for Driver_I2CI3C in component ::Drivers:I2CI3C +#define RTE_I2CI3C 1 +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] + +// I3C DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I3C +// Default: DISABLE +#define RTE_I3C_DMA_ENABLE 0 + +// I3C DMA Selection +// <0=> DMA2(M55-HE) +// <1=> DMA0 +// Defines Select DMA0 for I3C. By default DMA0 will be considered +// Default: DMA0 +#define RTE_I3C_SELECT_DMA0 1 + +// I3C DMA IRQ priority <0-255> +// Defines I3C DMA Interrupt priority +// Default: 0 +#define RTE_I3C_DMA_IRQ_PRI 0 + +// I3C blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I3C +// Default: DISABLE +#define RTE_I3C_BLOCKING_MODE_ENABLE 0 + +// I3C Slave I2C/I3C Adaptive mode Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines whether I3C Slave starts with I2C mode or not. +// It is for for enabling some features for I2C/I3C mode +// Default: DISABLE +#define RTE_I3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 + +#endif +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] + +// IMU (Initial Measurement Unit) [Driver_IMU] +// Configuration settings for Driver_IMU in component ::Drivers:IMU +#define RTE_IMU 1 + +#if RTE_IMU + +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] +// Configuration settings for Driver_ICM42670 in component ::Drivers:IMU +#define RTE_ICM42670 1 + +#if RTE_ICM42670 + +// ICM42670 IMU enable In-band_interrupt +// <0=> DISABLE +// <1=> ENABLE +// Defines whether In-band-interrupt to be enabled +// If disabled, then Normal-GPIO interrupt will be enabled +// Default: DISABLE +#define RTE_ICM42670_IBI_ENABLE 0 + +#endif +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +// Configuration settings for Driver_BMI323 in component ::Drivers:IMU +#define RTE_BMI323 1 + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +#endif +// IMU (Initial Measurement Unit) [Driver_IMU] + +// SPI (Serial Peripheral Interface) +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] +// Configuration settings for Driver_SPI0 in component ::Drivers:SPI +#define RTE_SPI0 1 + +#ifdef RTE_SPI0 + +// SPI0 IRQ priority <0-255> +// Defines Interrupt priority for SPI0. +// Default: 0 +#define RTE_SPI0_IRQ_PRIORITY 0 + +// SPI0 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI0. +// Default: 0 +#define RTE_SPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI0 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_THRESHOLD 0 + +// SPI0 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_RX_FIFO_THRESHOLD 0 + +// SPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI0. +// Default: 0 +#define RTE_SPI0_CHIP_SELECTION_PIN 0 + +// SPI0 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI0. +// Default: 0 +#define RTE_SPI0_RX_SAMPLE_DELAY 0 + +// SPI0 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI0. +// Default: 1 +#define RTE_SPI0_SSTE_ENABLE 1 + +// SPI0 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI0_USE_MASTER_SS_SW 0 + +#if RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 SW SS Port <0-15> +// Defines SPI0 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PORT 0 + +// SPI0 SW SS Pin <0-7> +// Defines SPI0 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PIN 0 + +// SPI0 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI0. +// Default: 0 +#define RTE_SPI0_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI0 MicroWire frame format. +// Default: 0 +#define RTE_SPI0_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI0 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI0_MW_TRANSFER_MODE 0 + +// SPI0 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI0 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI0_MW_HANDSAHKE_ENABLE 0 + +// SPI0 MW Control Frame Size +// Defines MW Control Frame Size for SPI0. +// Default: 0 +#define RTE_SPI0_MW_CFS 16 +#endif // RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI0 +// Default: DISABLE +#define RTE_SPI0_DMA_ENABLE 0 + +// SPI0 DMA IRQ priority <0-255> +// Defines SPI0 DMA Interrupt priority +// Default: 0 +#define RTE_SPI0_DMA_IRQ_PRI 0 + +// SPI0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI0 +// Default: DISABLE +#define RTE_SPI0_BLOCKING_MODE_ENABLE 0 +#endif +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 1 + +#ifdef RTE_SPI1 + +// SPI1 IRQ priority <0-255> +// Defines Interrupt priority for SPI1. +// Default: 0 +#define RTE_SPI1_IRQ_PRIORITY 0 + +// SPI1 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI1. +// Default: 0 +#define RTE_SPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI1 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_THRESHOLD 0 + +// SPI1 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_RX_FIFO_THRESHOLD 0 + +// SPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI1. +// Default: 0 +#define RTE_SPI1_CHIP_SELECTION_PIN 0 + +// SPI1 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI1. +// Default: 0 +#define RTE_SPI1_RX_SAMPLE_DELAY 0 + +// SPI1 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI1. +// Default: 1 +#define RTE_SPI1_SSTE_ENABLE 1 + +// SPI1 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI1_USE_MASTER_SS_SW 0 + +#if RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 SW SS Port <0-15> +// Defines SPI1 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PORT 0 + +// SPI1 SW SS pin number <0-7> +// Defines SPI1 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PIN 0 + +// SPI1 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI1. +// Default: 0 +#define RTE_SPI1_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI1 MicroWire frame format. +// Default: 0 +#define RTE_SPI1_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI1 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI1_MW_TRANSFER_MODE 0 + +// SPI1 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI1 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI1_MW_HANDSAHKE_ENABLE 0 + +// SPI1 MW Control Frame Size +// Defines MW Control Frame Size for SPI1. +// Default: 0 +#define RTE_SPI1_MW_CFS 16 +#endif // RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI1 +// Default: DISABLE +#define RTE_SPI1_DMA_ENABLE 0 + +// SPI1 DMA IRQ priority <0-255> +// Defines SPI1 DMA Interrupt priority +// Default: 0 +#define RTE_SPI1_DMA_IRQ_PRI 0 + +// SPI1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI1 +// Default: DISABLE +#define RTE_SPI1_BLOCKING_MODE_ENABLE 0 +#endif +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 1 + +#ifdef RTE_SPI2 + +// SPI2 IRQ priority <0-255> +// Defines Interrupt priority for SPI2. +// Default: 0 +#define RTE_SPI2_IRQ_PRIORITY 0 + +// SPI2 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI2 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI2. +// Default: 0 +#define RTE_SPI2_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI2 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_THRESHOLD 0 + +// SPI2 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_RX_FIFO_THRESHOLD 0 + +// SPI2 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI2. +// Default: 0 +#define RTE_SPI2_CHIP_SELECTION_PIN 0 + +// SPI2 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI2. +// Default: 0 +#define RTE_SPI2_RX_SAMPLE_DELAY 0 + +// SPI2 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI2. +// Default: 1 +#define RTE_SPI2_SSTE_ENABLE 1 + +// SPI2 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI2_USE_MASTER_SS_SW 0 + +#if RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 SW SS Port <0-15> +// Defines SPI2 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PORT 0 + +// SPI2 SW SS pin number <0-7> +// Defines SPI2 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PIN 0 + +// SPI2 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI2. +// Default: 0 +#define RTE_SPI2_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI2 MicroWire frame format. +// Default: 0 +#define RTE_SPI2_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI2 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI2_MW_TRANSFER_MODE 0 + +// SPI2 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI2 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI2_MW_HANDSAHKE_ENABLE 0 + +// SPI2 MW Control Frame Size +// Defines MW Control Frame Size for SPI2. +// Default: 0 +#define RTE_SPI2_MW_CFS 0 +#endif // RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI2 +// Default: DISABLE +#define RTE_SPI2_DMA_ENABLE 0 + +// SPI2 DMA IRQ priority <0-255> +// Defines SPI2 DMA Interrupt priority +// Default: 0 +#define RTE_SPI2_DMA_IRQ_PRI 0 + +// SPI2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI2 +// Default: DISABLE +#define RTE_SPI2_BLOCKING_MODE_ENABLE 0 +#endif +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 1 + +#ifdef RTE_SPI3 + +// SPI3 IRQ priority <0-255> +// Defines Interrupt priority for SPI3. +// Default: 0 +#define RTE_SPI3_IRQ_PRIORITY 0 + +// SPI3 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI3 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI3. +// Default: 0 +#define RTE_SPI3_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI3 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_THRESHOLD 0 + +// SPI3 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_RX_FIFO_THRESHOLD 0 + +// SPI3 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI3. +// Default: 0 +#define RTE_SPI3_CHIP_SELECTION_PIN 1 + +// SPI3 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI3. +// Default: 0 +#define RTE_SPI3_RX_SAMPLE_DELAY 0 + +// SPI3 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI3. +// Default: 1 +#define RTE_SPI3_SSTE_ENABLE 1 + +// SPI3 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI3_USE_MASTER_SS_SW 0 + +#if RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 SW SS Port <0-15> +// Defines SPI3 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PORT 0 + +// SPI3 SW SS pin number <0-7> +// Defines SPI3 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PIN 0 + +// SPI3 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI3. +// Default: 0 +#define RTE_SPI3_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI3 MicroWire frame format. +// Default: 0 +#define RTE_SPI3_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI3 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI3_MW_TRANSFER_MODE 0 + +// SPI3 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI3 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI3_MW_HANDSAHKE_ENABLE 0 + +// SPI3 MW Control Frame Size +// Defines MW Control Frame Size for SPI3. +// Default: 0 +#define RTE_SPI3_MW_CFS 0 +#endif // RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI3 +// Default: DISABLE +#define RTE_SPI3_DMA_ENABLE 0 + +// SPI3 DMA IRQ priority <0-255> +// Defines SPI3 DMA Interrupt priority +// Default: 0 +#define RTE_SPI3_DMA_IRQ_PRI 0 + +// SPI3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI3 +// Default: DISABLE +#define RTE_SPI3_BLOCKING_MODE_ENABLE 0 +#endif +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// Configuration settings for Driver_LPSPI in component ::Drivers:SPI +#if defined(RTSS_HE) + +#define RTE_LPSPI 1 + +#ifdef RTE_LPSPI + +// LPSPI IRQ priority <0-255> +// Defines Interrupt priority for LPSPI. +// Default: 0 +#define RTE_LPSPI_IRQ_PRIORITY 0 + +// LPSPI TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// LPSPI load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// LPSPI TX FIFO threshold <0-15> +// Defines TX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_THRESHOLD 0 + +// LPSPI RX FIFO threshold <0-15> +// Defines RX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_RX_FIFO_THRESHOLD 0 + +// LPSPI slave selection +// <0=> SS_0 +// Defines slave selection for LPSPI. +// Default: 0 +#define RTE_LPSPI_CHIP_SELECTION_PIN 0 + +// LPSPI Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for LPSPI. +// Default: 1 +#define RTE_LPSPI_SSTE_ENABLE 1 + +// LPSPI Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_LPSPI_USE_MASTER_SS_SW 0 + +#if RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI SW SS Port <0-15> +// Defines LPSPI port of SS pin in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PORT 0 + +// LPSPI SW SS pin number <0-7> +// Defines LPSPI SS pin number in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PIN 0 + +// LPSPI SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for LPSPI. +// Default: 0 +#define RTE_LPSPI_SW_SPI_SS_POLARITY 0 +#endif // RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of LPSPI MicroWire frame format. +// Default: 0 +#define RTE_LPSPI_MICROWIRE_FRF_ENABLE 0 + +#if RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines LPSPI MicroWire transfer mode. +// Default: 0 +#define RTE_LPSPI_MW_TRANSFER_MODE 0 + +// LPSPI MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines LPSPI MicroWire handshake enable. +// Default: 0 +#define RTE_LPSPI_MW_HANDSAHKE_ENABLE 0 + +// LPSPI MW Control Frame Size +// Defines MW Control Frame Size for LPSPI. +// Default: 0 +#define RTE_LPSPI_MW_CFS 8 +#endif // RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPSPI +// Default: DISABLE +#define RTE_LPSPI_DMA_ENABLE 0 +#if RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPSPI. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPSPI_SELECT_DMA0 0 +#if RTE_LPSPI_SELECT_DMA0 + +// LPSPI DMA0 Group Selection +// <1=> DMA0_GROUP_1 +// <2=> DMA0_GROUP_2 +// Defines DMA0 Group for LPSPI. By default DMA0 Group 1 will be considered +// Default: DMA0_GROUP_1 +#define RTE_LPSPI_SELECT_DMA0_GROUP 1 +#endif // RTE_LPSPI_SELECT_DMA0 +#endif // RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA IRQ priority <0-255> +// Defines LPSPI DMA Interrupt priority +// Default: 0 +#define RTE_LPSPI_DMA_IRQ_PRI 0 + +// LPSPI blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPSPI +// Default: DISABLE +#define RTE_LPSPI_BLOCKING_MODE_ENABLE 0 +#endif // RTE_LPSPI +#endif // RTSS_HE + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// SPI (Serial Peripheral Interface) + +// OSPI (Octal Serial Peripheral Interface) +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI0 1 +#if RTE_OSPI0 +// OSPI0 IRQ priority <0-255> +// Defines OSPI0 Interrupt priority +// Default: 0 +#define RTE_OSPI0_IRQ_PRIORITY 0 + +// OSPI0 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <3=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI0_SPI_FRAME_FORMAT 3 + +// OSPI0 Bus speed +// Defines the OSPI0 Bus speed +// Default: 100000000 +#define RTE_OSPI0_BUS_SPEED 100000000 + +// OSPI0 Wait Cycles +// Defines the OSPI0 Wait Cycles for connected device +// Default: 6 +#define RTE_OSPI0_WAIT_CYCLES 6 + +// OSPI0 DFS +// Defines OSPI0 Data Frame Size +// Default: 16 +#define RTE_OSPI0_DFS 16 + +// OSPI0 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI0 +// Default: 0 +#define RTE_OSPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI0 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_FIFO_THRESHOLD 64 + +// OSPI0 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_FIFO_THRESHOLD 0 + +// OSPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_DMA_ENABLE 0 +#if RTE_OSPI0_DMA_ENABLE + +// OSPI0 TX DMA Data level +// Defines TX DMA Data level for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_DMA_DATA_LEVEL 64 + +// OSPI0 RX DMA Data level +// Defines RX DMA Data level for OSPI0 +// Default: 15 +#define RTE_OSPI0_RX_DMA_DATA_LEVEL 15 + +// OSPI0 DMA IRQ priority <0-255> +// Defines OSPI0 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI0_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI0 +// Default: 0 +#define RTE_OSPI0_CHIP_SELECTION_PIN 0 + +// OSPI0 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_SAMPLE_DELAY 0 + +// OSPI0 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI0 +// Default: 0 +#define RTE_OSPI0_DDR_DRIVE_EDGE 0 + +// OSPI0 RXDS Delay <0-16> +// Defines the delay applied to the RXDS signal of OSPI0 +// Default: 0 +#define RTE_OSPI0_RXDS_DELAY 11 + +// OSPI0 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI0 +// Default: 0 +#define RTE_OSPI0_SIGNAL_DELAY 22 +#endif +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] + +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI1 1 +#if RTE_OSPI1 +// OSPI1 IRQ priority <0-255> +// Defines OSPI1 Interrupt priority +// Default: 0 +#define RTE_OSPI1_IRQ_PRIORITY 0 + +// OSPI1 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <3=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI1_SPI_FRAME_FORMAT 3 + +// OSPI1 Bus speed +// Defines the OSPI1 Bus speed +// Default: 100000000 +#define RTE_OSPI1_BUS_SPEED 100000000 + +// OSPI1 Wait Cycles +// Defines the OSPI1 Wait Cycles for connected device +// Default: 16 +#define RTE_OSPI1_WAIT_CYCLES 3 + +// OSPI1 DFS +// Defines OSPI1 Data Frame Size +// Default: 32 +#define RTE_OSPI1_DFS 32 + +// OSPI1 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI1 +// Default: 0 +#define RTE_OSPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI1 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI1 +// Default: 64 +#define RTE_OSPI1_TX_FIFO_THRESHOLD 64 + +// OSPI1 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_FIFO_THRESHOLD 0 + +// OSPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_DMA_ENABLE 0 +#if RTE_OSPI1_DMA_ENABLE + +// OSPI1 TX DMA Data level +// Defines TX DMA Data level for OSPI1 +// Default: 130 +#define RTE_OSPI1_TX_DMA_DATA_LEVEL 130 + +// OSPI1 RX DMA Data level +// Defines RX DMA Data level for OSPI1 +// Default: 15 +#define RTE_OSPI1_RX_DMA_DATA_LEVEL 15 + +// OSPI1 DMA IRQ priority <0-255> +// Defines OSPI1 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI1_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI1. +// Default: 0 +#define RTE_OSPI1_CHIP_SELECTION_PIN 0 + +// OSPI1 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_SAMPLE_DELAY 0 + +// OSPI1 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI1 +// Default: 1 +#define RTE_OSPI1_DDR_DRIVE_EDGE 1 + +// OSPI1 RXDS Delay <0-16> +// Defines the delay applied to the RXDS signal of OSPI1 +// Default: 11 +#define RTE_OSPI1_RXDS_DELAY 11 + +// OSPI1 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI1 +// Default: 0 +#define RTE_OSPI1_SIGNAL_DELAY 0 +#endif +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// OSPI (Octal Serial Peripheral Interface) + +// +// FLASH (ISSI FLASH) [Driver_Flash] +// Configuration settings for Driver_Flash in component ::Drivers:Flash +#define RTE_ISSI_FLASH 1 +#if RTE_ISSI_FLASH + +// ISSI FLASH SIZE +// ISSI flash density in bytes +// Default: 0x2000000 +#define RTE_ISSI_FLASH_SIZE 0x2000000 + +// ISSI FLASH OSPI Instance +// Defines the OSPI controller instance the ISSI flash is connected to +// Default: 1 +#define RTE_ISSI_FLASH_OSPI_DRV_NUM 1 + +// ISSI FLASH OSPI Bus speed +// Defines the OSPI Bus speed +// Default: 100000000 +#define RTE_ISSI_FLASH_OSPI_BUS_SPEED 100000000 + +// ISSI FLASH Wait cycles +// Defines the number of wait (dummy) cycles needed for fast read operations +// Default: 16 +#define RTE_ISSI_FLASH_WAIT_CYCLES 16 + +#endif +// FLASH (ISSI FLASH) [Driver_Flash] + +// I2S (Integrated Interchip Sound) +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] +// Configuration settings for Driver_SAI0 in component ::Drivers:SAI +#define RTE_I2S0 1 + +#if RTE_I2S0 + +// I2S0 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S0 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S0_WSS_CLOCK_CYCLES 2 + +// I2S0 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S0 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S0_SCLKG_CLOCK_CYCLES 0 + +// I2S0 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S0_RX_TRIG_LVL 7 + +// I2S0 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S0_TX_TRIG_LVL 8 + +// I2S0 IRQ priority <0-255> +// Defines I2S0 Interrupt priority +// Default: 0 +#define RTE_I2S0_IRQ_PRI 0 + +// I2S0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S0 +// Default: ENABLE +#define RTE_I2S0_DMA_ENABLE 0 + +// I2S0 DMA IRQ priority <0-255> +// Defines I2S0 DMA Interrupt priority +// Default: 0 +#define RTE_I2S0_DMA_IRQ_PRI 0 + +// I2S0 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S0 +// Default: DISABLE +#define RTE_I2S0_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] + +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] +// Configuration settings for Driver_SAI1 in component ::Drivers:SAI +#define RTE_I2S1 1 + +#if RTE_I2S1 + +// I2S1 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S1 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S1_WSS_CLOCK_CYCLES 2 + +// I2S1 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S1 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S1_SCLKG_CLOCK_CYCLES 0 + +// I2S1 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S1_RX_TRIG_LVL 7 + +// I2S1 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S1_TX_TRIG_LVL 8 + +// I2S1 IRQ priority <0-255> +// Defines I2S1 Interrupt priority +// Default: 1 +#define RTE_I2S1_IRQ_PRI 1 + +// I2S1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S1 +// Default: ENABLE +#define RTE_I2S1_DMA_ENABLE 0 + +// I2S1 DMA IRQ priority <0-255> +// Defines I2S1 DMA Interrupt priority +// Default: 0 +#define RTE_I2S1_DMA_IRQ_PRI 0 + +// I2S1 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S1 +// Default: DISABLE +#define RTE_I2S1_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] + +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] +// Configuration settings for Driver_SAI2 in component ::Drivers:SAI +#define RTE_I2S2 1 + +#if RTE_I2S2 + +// I2S2 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S2 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S2_WSS_CLOCK_CYCLES 2 + +// I2S2 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S2 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S2_SCLKG_CLOCK_CYCLES 0 + +// I2S2 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S2_RX_TRIG_LVL 7 + +// I2S2 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S2_TX_TRIG_LVL 8 + +// I2S2 IRQ priority <0-255> +// Defines I2S2 Interrupt priority +// Default: 0 +#define RTE_I2S2_IRQ_PRI 10 + +// I2S2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S2 +// Default: ENABLE +#define RTE_I2S2_DMA_ENABLE 0 + +// I2S2 DMA IRQ priority <0-255> +// Defines I2S2 DMA Interrupt priority +// Default: 0 +#define RTE_I2S2_DMA_IRQ_PRI 0 + +// I2S2 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S2 +// Default: DISABLE +#define RTE_I2S2_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] + +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] +// Configuration settings for Driver_SAI3 in component ::Drivers:SAI +#define RTE_I2S3 1 + +#if RTE_I2S3 + +// I2S3 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S3 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S3_WSS_CLOCK_CYCLES 2 + +// I2S3 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S3 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S3_SCLKG_CLOCK_CYCLES 0 + +// I2S3 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S3_RX_TRIG_LVL 7 + +// I2S3 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S3_TX_TRIG_LVL 8 + +// I2S3 IRQ priority <0-255> +// Defines I2S3 Interrupt priority +// Default: 0 +#define RTE_I2S3_IRQ_PRI 0 + +// I2S3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S3 +// Default: ENABLE +#define RTE_I2S3_DMA_ENABLE 0 + +// I2S3 DMA IRQ priority <0-255> +// Defines I2S3 DMA Interrupt priority +// Default: 0 +#define RTE_I2S3_DMA_IRQ_PRI 0 + +// I2S3 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S3 +// Default: DISABLE +#define RTE_I2S3_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// Configuration settings for Driver_SAILP in component ::Drivers:SAI +#if defined(RTSS_HE) + +#define RTE_LPI2S 1 + +#if RTE_LPI2S + +// LPI2S WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines LPI2S size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_LPI2S_WSS_CLOCK_CYCLES 2 + +// LPI2S SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines LPI2S SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_LPI2S_SCLKG_CLOCK_CYCLES 0 + +// LPI2S RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_LPI2S_RX_TRIG_LVL 7 + +// LPI2S TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_LPI2S_TX_TRIG_LVL 8 + +// LPI2S IRQ priority <0-255> +// Defines LPI2S Interrupt priority +// Default: 1 +#define RTE_LPI2S_IRQ_PRI 1 + +// LPI2S DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI2S +// Default: ENABLE +#define RTE_LPI2S_DMA_ENABLE 0 +#if RTE_LPI2S_DMA_ENABLE + +// LPI2S DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPI2S. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPI2S_SELECT_DMA0 0 +#endif + +// LPI2S DMA IRQ priority <0-255> +// Defines LPI2S DMA Interrupt priority +// Default: 0 +#define RTE_LPI2S_DMA_IRQ_PRI 0 + +// LPI2S Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPI2S +// Default: DISABLE +#define RTE_LPI2S_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPI2S +#endif // defined(RTSS_HE) + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// I2S (Integrated Interchip Sound) + +// WM8904 Codec [Driver_WM8904] +// Configuration settings for Driver_WM8904 in component ::Drivers:WM8904 +#define RTE_WM8904_CODEC 1 + +#if RTE_WM8904_CODEC + +// Select WM8904 i2c instance +// Defines WM8904 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 0 +#define RTE_WM8904_CODEC_I2C_INSTANCE 0 +#endif + +// WM8904 Codec [Driver_WM8904] + +// UART (Universal asynchronous receiver transmitter) +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_UART0 1 + +#if RTE_UART0 + +// UART0 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART0 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART0_RX_TRIG_LVL 0 + +// UART0 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART0 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART0_TX_TRIG_LVL 0 + +// UART0 IRQ priority <0-255> +// Defines Interrupt priority for UART0. +// Default: 0 +#define RTE_UART0_IRQ_PRI 0 + +// UART0 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART0 clock source. +// Default: CLK_100MHz +#define RTE_UART0_CLK_SOURCE 1 + +// UART0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART0 +// Default: DISABLE +#define RTE_UART0_DMA_ENABLE 0 + +// UART0 DMA IRQ priority <0-255> +// Defines UART0 DMA Interrupt priority +// Default: 0 +#define RTE_UART0_DMA_IRQ_PRI 0 + +// UART0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART0 +// Default: DISABLE +#define RTE_UART0_BLOCKING_MODE_ENABLE 0 + +#endif // UART0 + +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_UART1 1 + +#if RTE_UART1 + +// UART1 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART1 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART1_RX_TRIG_LVL 0 + +// UART1 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART1 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART1_TX_TRIG_LVL 0 + +// UART1 IRQ priority <0-255> +// Defines Interrupt priority for UART1. +// Default: 0 +#define RTE_UART1_IRQ_PRI 0 + +// UART1 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART1 clock source. +// Default: CLK_100MHz +#define RTE_UART1_CLK_SOURCE 1 + +// UART1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART1 +// Default: DISABLE +#define RTE_UART1_DMA_ENABLE 0 + +// UART1 DMA IRQ priority <0-255> +// Defines UART1 DMA Interrupt priority +// Default: 0 +#define RTE_UART1_DMA_IRQ_PRI 0 + +// UART1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART1 +// Default: DISABLE +#define RTE_UART1_BLOCKING_MODE_ENABLE 0 + +#endif // UART1 + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::Drivers:USART +#define RTE_UART2 1 + +#if RTE_UART2 + +// UART2 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART2 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART2_RX_TRIG_LVL 0 + +// UART2 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART2 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART2_TX_TRIG_LVL 0 + +// UART2 IRQ priority <0-255> +// Defines Interrupt priority for UART2. +// Default: 0 +#define RTE_UART2_IRQ_PRI 0 + +// UART2 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART2 clock source. +// Default: CLK_100MHz +#define RTE_UART2_CLK_SOURCE 1 + +// UART2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART2 +// Default: DISABLE +#define RTE_UART2_DMA_ENABLE 0 + +// UART2 DMA IRQ priority <0-255> +// Defines UART2 DMA Interrupt priority +// Default: 0 +#define RTE_UART2_DMA_IRQ_PRI 0 + +// UART2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART2 +// Default: DISABLE +#define RTE_UART2_BLOCKING_MODE_ENABLE 0 + +#endif // UART2 + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::Drivers:USART +#define RTE_UART3 1 + +#if RTE_UART3 + +// UART3 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART3 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART3_RX_TRIG_LVL 0 + +// UART3 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART3 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART3_TX_TRIG_LVL 0 + +// UART3 IRQ priority <0-255> +// Defines Interrupt priority for UART3. +// Default: 0 +#define RTE_UART3_IRQ_PRI 0 + +// UART3 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART3 clock source. +// Default: CLK_100MHz +#define RTE_UART3_CLK_SOURCE 1 + +// UART3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART3 +// Default: DISABLE +#define RTE_UART3_DMA_ENABLE 0 + +// UART3 DMA IRQ priority <0-255> +// Defines UART3 DMA Interrupt priority +// Default: 0 +#define RTE_UART3_DMA_IRQ_PRI 0 + +// UART3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART3 +// Default: DISABLE +#define RTE_UART3_BLOCKING_MODE_ENABLE 0 + +#endif // UART3 + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::Drivers:USART +#define RTE_UART4 1 + +#if RTE_UART4 + +// UART4 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART4 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART4_RX_TRIG_LVL 0 + +// UART4 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART4 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART4_TX_TRIG_LVL 0 + +// UART4 IRQ priority <0-255> +// Defines Interrupt priority for UART4. +// Default: 0 +#define RTE_UART4_IRQ_PRI 0 + +// UART4 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART4 clock source. +// Default: CLK_100MHz +#define RTE_UART4_CLK_SOURCE 1 + +#define RTE_UART4_RS485_ENABLE 0 +#if RTE_UART4_RS485_ENABLE +#define RTE_UART4_RS485_TRANSFER_MODE 2 +#define RTE_UART4_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART4_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART4 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART4 +// Default: DISABLE +#define RTE_UART4_DMA_ENABLE 0 + +// UART4 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART4. By default DMA0 will be considered. +// Default: DMA0 +#define RTE_UART4_SELECT_DMA0 1 + +// UART4 DMA IRQ priority <0-255> +// Defines UART4 DMA Interrupt priority +// Default: 0 +#define RTE_UART4_DMA_IRQ_PRI 0 + +// UART4 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART4 +// Default: DISABLE +#define RTE_UART4_BLOCKING_MODE_ENABLE 0 + +#endif // UART4 + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::Drivers:USART +#define RTE_UART5 1 + +#if RTE_UART5 + +// UART5 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART5 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART5_RX_TRIG_LVL 0 + +// UART5 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART5 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART5_TX_TRIG_LVL 0 + +// UART5 IRQ priority <0-255> +// Defines Interrupt priority for UART5. +// Default: 0 +#define RTE_UART5_IRQ_PRI 0 + +// UART5 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART5 clock source. +// Default: CLK_100MHz +#define RTE_UART5_CLK_SOURCE 1 + +#define RTE_UART5_RS485_ENABLE 0 +#if RTE_UART5_RS485_ENABLE +#define RTE_UART5_RS485_TRANSFER_MODE 2 +#define RTE_UART5_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART5_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART5 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART5 +// Default: DISABLE +#define RTE_UART5_DMA_ENABLE 0 + +// UART5 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART5. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART5_SELECT_DMA0 1 + +// UART5 DMA IRQ priority <0-255> +// Defines UART5 DMA Interrupt priority +// Default: 0 +#define RTE_UART5_DMA_IRQ_PRI 0 + +// UART5 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART5 +// Default: DISABLE +#define RTE_UART5_BLOCKING_MODE_ENABLE 0 + +#endif // UART5 + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::Drivers:USART +#define RTE_UART6 1 + +#if RTE_UART6 + +// UART6 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART6 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART6_RX_TRIG_LVL 0 + +// UART6 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART6 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART6_TX_TRIG_LVL 0 + +// UART6 IRQ priority <0-255> +// Defines Interrupt priority for UART6. +// Default: 0 +#define RTE_UART6_IRQ_PRI 0 + +// UART6 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART6 clock source. +// Default: CLK_100MHz +#define RTE_UART6_CLK_SOURCE 1 + +#define RTE_UART6_RS485_ENABLE 0 +#if RTE_UART6_RS485_ENABLE +#define RTE_UART6_RS485_TRANSFER_MODE 2 +#define RTE_UART6_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART6_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART6 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART6 +// Default: DISABLE +#define RTE_UART6_DMA_ENABLE 0 + +// UART6 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART6. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART6_SELECT_DMA0 1 + +// UART6 DMA IRQ priority <0-255> +// Defines UART6 DMA Interrupt priority +// Default: 0 +#define RTE_UART6_DMA_IRQ_PRI 0 + +// UART6 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART6 +// Default: DISABLE +#define RTE_UART6_BLOCKING_MODE_ENABLE 0 + +#endif // UART6 + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::Drivers:USART +#define RTE_UART7 1 + +#if RTE_UART7 + +// UART7 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART7 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART7_RX_TRIG_LVL 0 + +// UART7 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART7 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART7_TX_TRIG_LVL 0 + +// UART7 IRQ priority <0-255> +// Defines Interrupt priority for UART7. +// Default: 0 +#define RTE_UART7_IRQ_PRI 0 + +// UART7 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART7 clock source. +// Default: CLK_100MHz +#define RTE_UART7_CLK_SOURCE 1 + +#define RTE_UART7_RS485_ENABLE 0 +#if RTE_UART7_RS485_ENABLE +#define RTE_UART7_RS485_TRANSFER_MODE 2 +#define RTE_UART7_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART7_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART7 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART7 +// Default: DISABLE +#define RTE_UART7_DMA_ENABLE 0 + +// UART7 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART7. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART7_SELECT_DMA0 1 + +// UART7 DMA IRQ priority <0-255> +// Defines UART7 DMA Interrupt priority +// Default: 0 +#define RTE_UART7_DMA_IRQ_PRI 0 + +// UART7 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART7 +// Default: DISABLE +#define RTE_UART7_BLOCKING_MODE_ENABLE 0 + +#endif // UART7 + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// Configuration settings for Driver_USARTLP in component ::Drivers:USART +#if defined(RTSS_HE) +#define RTE_LPUART 1 +#endif + +#if RTE_LPUART + +// LPUART RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines LPUART receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_LPUART_RX_TRIG_LVL 0 + +// LPUART TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines LPUART transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_LPUART_TX_TRIG_LVL 0 + +// LPUART IRQ priority <0-255> +// Defines Interrupt priority for LPUART. +// Default: 0 +#define RTE_LPUART_IRQ_PRI 0 + +// LPUART DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPUART +// Default: DISABLE +#define RTE_LPUART_DMA_ENABLE 0 + +// LPUART DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPUART. By default DMA0 will be considered +// Default: DMA0 +#define RTE_LPUART_SELECT_DMA0 1 + +// LPUART DMA IRQ priority <0-255> +// Defines LPUART DMA Interrupt priority +// Default: 0 +#define RTE_LPUART_DMA_IRQ_PRI 0 + +// LPUART blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPUART +// Default: DISABLE +#define RTE_LPUART_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPUART + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// UART (Universal asynchronous receiver transmitter) + +// LPTIMER (Low power timer) +// LPTIMER (Low power timer) [Driver_LPTIMER] +// Configuration settings for Driver_LPTIMER in component ::Drivers:LPTIMER +#define RTE_LPTIMER 1 + +#if RTE_LPTIMER + +// LPTIMER CHANNEL 0 +// Configuration settings for Driver_LPTIMER channel 0 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL0 1 + +// CHANNEL0 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 0. +// Default: 0 +#define RTE_LPTIMER_CHANNEL0_IRQ_PRIORITY (0) + +// CHANNEL0 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel0. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL0_FREE_RUN_MODE (0) + +// CHANNEL0 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel0. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL0_CLK_SRC (0) +// LPTIMER CHANNEL 0 + +// LPTIMER CHANNEL 1 +// Configuration settings for Driver_LPTIMER channel 1 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL1 1 + +// CHANNEL1 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 1. +// Default: 0 +#define RTE_LPTIMER_CHANNEL1_IRQ_PRIORITY (0) + +// CHANNEL1 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel1. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL1_FREE_RUN_MODE (0) + +// CHANNEL1 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel1. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL1_CLK_SRC (0) +// LPTIMER CHANNEL 1 + +// LPTIMER CHANNEL 2 +// Configuration settings for Driver_LPTIMER channel 2 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL2 1 + +// CHANNEL2 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 2. +// Default: 0 +#define RTE_LPTIMER_CHANNEL2_IRQ_PRIORITY (0) + +// CHANNEL2 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel2. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL2_FREE_RUN_MODE (0) + +// CHANNEL2 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel2. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL2_CLK_SRC (0) +// LPTIMER CHANNEL 2 + +// LPTIMER CHANNEL 3 +// Configuration settings for Driver_LPTIMER channel 3 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL3 1 + +// CHANNEL3 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 3. +// Default: 0 +#define RTE_LPTIMER_CHANNEL3_IRQ_PRIORITY (0) + +// CHANNEL3 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel3. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL3_FREE_RUN_MODE (0) + +// CHANNEL3 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel3. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL3_CLK_SRC (0) +// LPTIMER CHANNEL 3 +#endif /* RTE_LPTIMER */ +// LPTIMER (Low power timer) [Driver_LPTIMER] +// LPTIMER (Low power timer) + +// RTC (Real time clock) +// RTC0 (Real time clock) [Driver_RTC0] +// Configuration settings for Driver_RTC0 in component ::Drivers:RTC +#define RTE_RTC0 1 + +#if RTE_RTC0 + +// RTC0 IRQ priority <0-255> +// Defines Interrupt priority for RTC0. +// Default: 0 +#define RTE_RTC0_IRQ_PRI 0 +#endif +// RTC0 (Real time clock) [Driver_RTC0] +// RTC (Real time clock) + +// WDT (Watchdog Timer) +// WDT0 (Watchdog Timer) [Driver_WDT0] +// Configuration settings for Driver_WDT0 in component ::Drivers:WDT +#define RTE_WDT0 1 +// WDT0 (Watchdog Timer) [Driver_WDT0] +// WDT (Watchdog Timer) + +// UTIMER (Universal Timer) +// UTIMER (Universal Timer) [Driver_UTIMER] +// Configuration settings for Driver_UTIMER in component ::Drivers:UTIMER +#define RTE_UTIMER 1 + +#if RTE_UTIMER + +// UTIMER CHANNEL 0 +// Configuration settings for UTIMER channel 0 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL0 1 + +// CHANNEL0 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_FIXED_BUFFER 0 + +// CHANNEL0 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DMA_CLEAR_ENABLE 0 + +// CHANNEL0 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 0. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL0_FAULT_TYPE 0 + +// CHANNEL0 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 0. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 + +// CHANNEL0 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_A 1 + +// CHANNEL0 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_B 0 + +// CHANNEL0 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_START_STATE 0 + +// CHANNEL0 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_STOP_STATE 0 + +// CHANNEL0 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL0 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_START_STATE 0 + +// CHANNEL0 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_STOP_STATE 0 + +// CHANNEL0 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL0 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_CREST 1 + +// CHANNEL0 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_TROUGH 0 + +// CHANNEL0 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 0. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE 0 + +// CHANNEL0 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 0. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL0_BUFFER_OPERATION 0 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_A 2 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_B 0 + +// CHANNEL0 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL0 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 + +// CHANNEL0 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 0 + +// UTIMER CHANNEL 1 +// Configuration settings for UTIMER channel 1 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL1 1 + +// CHANNEL1 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_FIXED_BUFFER 0 + +// CHANNEL1 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DMA_CLEAR_ENABLE 0 + +// CHANNEL1 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 1. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL1_FAULT_TYPE 0 + +// CHANNEL1 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 + +// CHANNEL1 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_A 0 + +// CHANNEL1 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_B 0 + +// CHANNEL1 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_START_STATE 0 + +// CHANNEL1 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_STOP_STATE 0 + +// CHANNEL1 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL1 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_START_STATE 0 + +// CHANNEL1 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_STOP_STATE 0 + +// CHANNEL1 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL1 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_CREST 1 + +// CHANNEL1 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_TROUGH 0 + +// CHANNEL1 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 1. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE 1 + +// CHANNEL1 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 1. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL1_BUFFER_OPERATION 1 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_A 0 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_B 0 + +// CHANNEL1 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL1 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 + +// CHANNEL1 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 1 + +// UTIMER CHANNEL 2 +// Configuration settings for UTIMER channel 2 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL2 1 + +// CHANNEL2 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_FIXED_BUFFER 0 + +// CHANNEL2 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DMA_CLEAR_ENABLE 0 + +// CHANNEL2 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 2. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL2_FAULT_TYPE 0 + +// CHANNEL2 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 2. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 + +// CHANNEL2 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_A 0 + +// CHANNEL2 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_B 0 + +// CHANNEL2 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_START_STATE 0 + +// CHANNEL2 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_STOP_STATE 0 + +// CHANNEL2 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL2 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_START_STATE 0 + +// CHANNEL2 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_STOP_STATE 0 + +// CHANNEL2 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL2 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_CREST 1 + +// CHANNEL2 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_TROUGH 0 + +// CHANNEL2 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 2. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE 1 + +// CHANNEL2 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 2. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL2_BUFFER_OPERATION 1 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_A 2 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_B 0 + +// CHANNEL2 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel2 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL2 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 + +// CHANNEL2 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 2 + +// UTIMER CHANNEL 3 +// Configuration settings for UTIMER channel 3 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL3 1 + +// CHANNEL3 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_FIXED_BUFFER 0 + +// CHANNEL3 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DMA_CLEAR_ENABLE 0 + +// CHANNEL3 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 3. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL3_FAULT_TYPE 0 + +// CHANNEL3 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 3. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL3_BUF_TROUGH_N_CREST 0 + +// CHANNEL3 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_A 0 + +// CHANNEL3 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_B 0 + +// CHANNEL3 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_START_STATE 0 + +// CHANNEL3 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_STOP_STATE 0 + +// CHANNEL3 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL3 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_START_STATE 0 + +// CHANNEL3 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_STOP_STATE 0 + +// CHANNEL3 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL3 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_CREST 1 + +// CHANNEL3 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_TROUGH 0 + +// CHANNEL3 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 3. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE 0 + +// CHANNEL3 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 3. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL3_BUFFER_OPERATION 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_A 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_B 0 + +// CHANNEL3 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL3 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_ENABLE 0 + +// CHANNEL3 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 3 + +// UTIMER CHANNEL 4 +// Configuration settings for UTIMER channel 4 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL4 1 + +// CHANNEL4 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_FIXED_BUFFER 0 + +// CHANNEL4 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DMA_CLEAR_ENABLE 0 + +// CHANNEL4 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 4. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL4_FAULT_TYPE 0 + +// CHANNEL4 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL4_BUF_TROUGH_N_CREST 0 + +// CHANNEL4 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_A 1 + +// CHANNEL4 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_B 0 + +// CHANNEL4 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_START_STATE 0 + +// CHANNEL4 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_STOP_STATE 0 + +// CHANNEL4 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL4 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_START_STATE 0 + +// CHANNEL4 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_STOP_STATE 0 + +// CHANNEL4 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL4 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_CREST 1 + +// CHANNEL4 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_TROUGH 1 + +// CHANNEL4 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 4. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE 1 + +// CHANNEL4 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 4. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL4_BUFFER_OPERATION 1 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_A 2 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_B 2 + +// CHANNEL4 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL4 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_ENABLE 0 + +// CHANNEL4 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 4 + +// UTIMER CHANNEL 5 +// Configuration settings for UTIMER channel 5 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL5 1 + +// CHANNEL5 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_FIXED_BUFFER 0 + +// CHANNEL5 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DMA_CLEAR_ENABLE 0 + +// CHANNEL5 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 5. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL5_FAULT_TYPE 0 + +// CHANNEL5 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 5. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL5_BUF_TROUGH_N_CREST 0 + +// CHANNEL5 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_A 1 + +// CHANNEL5 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_B 0 + +// CHANNEL5 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_START_STATE 0 + +// CHANNEL5 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_STOP_STATE 0 + +// CHANNEL5 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL5 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL5 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_START_STATE 0 + +// CHANNEL5 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_STOP_STATE 0 + +// CHANNEL5 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL5 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL5 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_CREST 1 + +// CHANNEL5 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_TROUGH 0 + +// CHANNEL5 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 5. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE 1 + +// CHANNEL5 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 5. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL5_BUFFER_OPERATION 1 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_A 2 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_B 0 + +// CHANNEL5 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL5 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_ENABLE 0 + +// CHANNEL5 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 5 + +// UTIMER CHANNEL 6 +// Configuration settings for UTIMER channel 6 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL6 1 + +// CHANNEL6 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_FIXED_BUFFER 0 + +// CHANNEL6 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DMA_CLEAR_ENABLE 0 + +// CHANNEL6 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 6. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL6_FAULT_TYPE 0 + +// CHANNEL6 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 6. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL6_BUF_TROUGH_N_CREST 0 + +// CHANNEL6 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_A 1 + +// CHANNEL6 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_B 0 + +// CHANNEL6 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_START_STATE 0 + +// CHANNEL6 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_STOP_STATE 0 + +// CHANNEL6 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL6 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL6 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_START_STATE 0 + +// CHANNEL6 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_STOP_STATE 0 + +// CHANNEL6 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL6 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL6 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_CREST 1 + +// CHANNEL6 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_TROUGH 0 + +// CHANNEL6 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 6. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE 0 + +// CHANNEL6 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 6. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL6_BUFFER_OPERATION 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_A 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_B 0 + +// CHANNEL6 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL6 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_ENABLE 0 + +// CHANNEL6 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 6 + +// UTIMER CHANNEL 7 +// Configuration settings for UTIMER channel 7 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL7 1 + +// CHANNEL7 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_FIXED_BUFFER 0 + +// CHANNEL7 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DMA_CLEAR_ENABLE 0 + +// CHANNEL7 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 7. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL7_FAULT_TYPE 0 + +// CHANNEL7 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 7. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL7_BUF_TROUGH_N_CREST 0 + +// CHANNEL7 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_A 0 + +// CHANNEL7 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_B 0 + +// CHANNEL7 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_START_STATE 0 + +// CHANNEL7 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_STOP_STATE 0 + +// CHANNEL7 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL7 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_START_STATE 0 + +// CHANNEL7 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_STOP_STATE 0 + +// CHANNEL7 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL7 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_CREST 1 + +// CHANNEL7 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_TROUGH 0 + +// CHANNEL7 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 7. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE 1 + +// CHANNEL7 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 7. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL7_BUFFER_OPERATION 1 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_A 2 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_B 0 + +// CHANNEL7 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL7 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_ENABLE 0 + +// CHANNEL7 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 7 + +// UTIMER CHANNEL 8 +// Configuration settings for UTIMER channel 8 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL8 1 + +// CHANNEL8 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_FIXED_BUFFER 0 + +// CHANNEL8 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DMA_CLEAR_ENABLE 0 + +// CHANNEL8 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 8. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL8_FAULT_TYPE 0 + +// CHANNEL8 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 8. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL8_BUF_TROUGH_N_CREST 0 + +// CHANNEL8 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_A 1 + +// CHANNEL8 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_B 0 + +// CHANNEL8 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_START_STATE 0 + +// CHANNEL8 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_STOP_STATE 0 + +// CHANNEL8 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL8 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL8 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_START_STATE 0 + +// CHANNEL8 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_STOP_STATE 0 + +// CHANNEL8 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL8 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL8 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_CREST 1 + +// CHANNEL8 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_TROUGH 0 + +// CHANNEL8 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 8. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE 0 + +// CHANNEL8 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 8. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL8_BUFFER_OPERATION 0 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_A 2 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_B 0 + +// CHANNEL8 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL8 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_ENABLE 0 + +// CHANNEL8 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 8 + +// UTIMER CHANNEL 9 +// Configuration settings for UTIMER channel 9 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL9 1 + +// CHANNEL9 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_FIXED_BUFFER 0 + +// CHANNEL9 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DMA_CLEAR_ENABLE 0 + +// CHANNEL9 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 9. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL9_FAULT_TYPE 0 + +// CHANNEL9 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 9. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL9_BUF_TROUGH_N_CREST 0 + +// CHANNEL9 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_A 0 + +// CHANNEL9 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_B 1 + +// CHANNEL9 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_START_STATE 0 + +// CHANNEL9 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_STOP_STATE 0 + +// CHANNEL9 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL9 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL9 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_START_STATE 0 + +// CHANNEL9 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_STOP_STATE 0 + +// CHANNEL9 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_MATCH_COUNT 1 + +// CHANNEL9 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_CYCLE_END 2 + +// CHANNEL9 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_CREST 1 + +// CHANNEL9 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_TROUGH 0 + +// CHANNEL9 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 9. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE 0 + +// CHANNEL9 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 9. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL9_BUFFER_OPERATION 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_A 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_B 0 + +// CHANNEL9 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL9 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_ENABLE 0 + +// CHANNEL9 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 9 + +// UTIMER CHANNEL 10 +// Configuration settings for UTIMER channel 10 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL10 1 + +// CHANNEL10 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_FIXED_BUFFER 0 + +// CHANNEL10 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DMA_CLEAR_ENABLE 0 + +// CHANNEL10 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 10. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL10_FAULT_TYPE 0 + +// CHANNEL10 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 10. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL10_BUF_TROUGH_N_CREST 0 + +// CHANNEL10 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_A 1 + +// CHANNEL10 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_B 0 + +// CHANNEL10 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_START_STATE 0 + +// CHANNEL10 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_STOP_STATE 0 + +// CHANNEL10 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL10 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL10 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_START_STATE 0 + +// CHANNEL10 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_STOP_STATE 0 + +// CHANNEL10 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL10 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL10 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_CREST 1 + +// CHANNEL10 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_TROUGH 0 + +// CHANNEL10 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 10. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE 0 + +// CHANNEL10 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 10. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL10_BUFFER_OPERATION 0 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_A 2 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_B 0 + +// CHANNEL10 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL10 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_ENABLE 0 + +// CHANNEL10 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 10 + +// UTIMER CHANNEL 11 +// Configuration settings for UTIMER channel 11 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL11 1 + +// CHANNEL11 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_FIXED_BUFFER 0 + +// CHANNEL11 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DMA_CLEAR_ENABLE 0 + +// CHANNEL11 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 11. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL11_FAULT_TYPE 0 + +// CHANNEL11 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 11. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL11_BUF_TROUGH_N_CREST 0 + +// CHANNEL11 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_A 0 + +// CHANNEL11 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_B 0 + +// CHANNEL11 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_START_STATE 0 + +// CHANNEL11 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_STOP_STATE 0 + +// CHANNEL11 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL11 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_START_STATE 0 + +// CHANNEL11 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_STOP_STATE 0 + +// CHANNEL11 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL11 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_CREST 1 + +// CHANNEL11 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_TROUGH 0 + +// CHANNEL11 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 11. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE 1 + +// CHANNEL11 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 11. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL11_BUFFER_OPERATION 1 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_A 2 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_B 0 + +// CHANNEL11 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL11 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_ENABLE 0 +// UTIMER CHANNEL 11 + +// UTIMER CHANNEL 12 +// Configuration settings for UTIMER channel 12 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL12 1 + +// CHANNEL11 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_VALUE 0 + +// CHANNEL12 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_FIXED_BUFFER 0 + +// CHANNEL12 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DMA_CLEAR_ENABLE 0 + +// CHANNEL12 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 12. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL12_FAULT_TYPE 0 + +// CHANNEL12 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 12. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL12_BUF_TROUGH_N_CREST 0 + +// CHANNEL12 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_A 1 + +// CHANNEL12 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_B 0 + +// CHANNEL12 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_START_STATE 0 + +// CHANNEL12 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_STOP_STATE 0 + +// CHANNEL12 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL12 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_START_STATE 0 + +// CHANNEL12 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_STOP_STATE 0 + +// CHANNEL12 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL12 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_CREST 1 + +// CHANNEL12 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_TROUGH 0 + +// CHANNEL12 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 12. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE 0 + +// CHANNEL12 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 12. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL12_BUFFER_OPERATION 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_A 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_B 0 + +// CHANNEL12 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL12 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_ENABLE 0 + +// CHANNEL12 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 12 + +// UTIMER CHANNEL 13 +// Configuration settings for UTIMER channel 13 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL13 1 + +// CHANNEL13 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_FIXED_BUFFER 0 + +// CHANNEL13 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DMA_CLEAR_ENABLE 0 + +// CHANNEL13 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 13. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL13_FAULT_TYPE 0 + +// CHANNEL13 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 13. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL13_BUF_TROUGH_N_CREST 0 + +// CHANNEL13 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_A 1 + +// CHANNEL13 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_B 0 + +// CHANNEL13 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_START_STATE 0 + +// CHANNEL13 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_STOP_STATE 0 + +// CHANNEL13 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL13 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_START_STATE 0 + +// CHANNEL13 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_STOP_STATE 0 + +// CHANNEL13 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL13 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_CREST 1 + +// CHANNEL13 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_TROUGH 0 + +// CHANNEL13 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 13. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE 0 + +// CHANNEL13 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 13. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL13_BUFFER_OPERATION 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_A 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_B 0 + +// CHANNEL13 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL13 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_ENABLE 0 + +// CHANNEL13 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 13 + +// UTIMER CHANNEL 14 +// Configuration settings for UTIMER channel 14 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL14 1 + +// CHANNEL14 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_FIXED_BUFFER 0 + +// CHANNEL14 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DMA_CLEAR_ENABLE 0 + +// CHANNEL14 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 14. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL14_FAULT_TYPE 0 + +// CHANNEL14 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 14. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL14_BUF_TROUGH_N_CREST 0 + +// CHANNEL14 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_A 1 + +// CHANNEL14 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_B 0 + +// CHANNEL14 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_START_STATE 0 + +// CHANNEL14 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_STOP_STATE 0 + +// CHANNEL14 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL14 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_START_STATE 0 + +// CHANNEL14 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_STOP_STATE 0 + +// CHANNEL14 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL14 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_CREST 1 + +// CHANNEL14 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_TROUGH 0 + +// CHANNEL14 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 14. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE 0 + +// CHANNEL14 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 14. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL14_BUFFER_OPERATION 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_A 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_B 0 + +// CHANNEL14 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL14 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_ENABLE 0 + +// CHANNEL14 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 14 + +// UTIMER CHANNEL 15 +// Configuration settings for UTIMER channel 15 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL15 1 + +// CHANNEL15 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_FIXED_BUFFER 0 + +// CHANNEL15 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DMA_CLEAR_ENABLE 0 + +// CHANNEL15 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 15. +// Default: LOW_UNTIL_CYCLE_END +#define RTE_UTIMER_CHANNEL15_FAULT_TYPE 0 + +// CHANNEL15 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 15. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL15_BUF_TROUGH_N_CREST 0 + +// CHANNEL15 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_A 1 + +// CHANNEL15 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_B 0 + +// CHANNEL15 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_START_STATE 0 + +// CHANNEL15 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_STOP_STATE 0 + +// CHANNEL15 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL15 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_START_STATE 0 + +// CHANNEL15 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_STOP_STATE 0 + +// CHANNEL15 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL15 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_CREST 1 + +// CHANNEL15 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_TROUGH 0 + +// CHANNEL15 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 15. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE 0 + +// CHANNEL15 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 15. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL15_BUFFER_OPERATION 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_A 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_B 0 + +// CHANNEL15 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL15 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_ENABLE 0 + +// CHANNEL15 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 15 +#endif /*RTE_UTIMER*/ +// UTIMER (Universal timer) [Driver_UTIMER] +// UTIMER (Universal Timer) + +// DAC (Digital to analog converter ) +// DAC0 (Digital to analog converter ) [Driver_DAC0] +// Configuration settings for Driver_DAC0 in component ::Drivers:DAC +#define RTE_DAC0 1 +#if RTE_DAC0 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC0_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC0_TWOSCOMP_EN 0 +#endif +// DAC0 (Digital to analog converter) [Driver_DAC0] + +// DAC1 (Digital to analog converter ) [Driver_DAC1] +// Configuration settings for Driver_DAC1 in component ::Drivers:DAC +#define RTE_DAC1 1 +#if RTE_DAC1 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC1_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC1_TWOSCOMP_EN 0 +#endif +// DAC1 (Digital to Analog converter) [Driver_DAC1] +// DAC(Digital to analog converter) + +// ADC (Analog to Digital Converter) +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] +// Configuration settings for Driver_ADC120 in component ::Drivers:ADC12 +#define RTE_ADC120 1 +#if RTE_ADC120 +#define RTE_ADC120_IRQ_PRIORITY 0 + +// ADC120 DONE0 IRQ PRIORITY <0-225> +// defines ADC120 done0 interrupt priority +// default: 0 +#define RTE_ADC120_DONE0_IRQ_PRIORITY 0 + +// ADC120 DONE1 IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_DONE1_IRQ_PRIORITY 0 + +// ADC120 CMPA IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPA_IRQ_PRIORITY 0 + +// ADC120 CMPB IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC120_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC120_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC120_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC120_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC120_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC120_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC120_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC120_DIFFERENTIAL_EN 0 + +// Enable PGA +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC120 PGA enable +// Default: DISABLE +#define RTE_ADC120_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC120_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_BIAS 2 + +#endif +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] + +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] +// Configuration settings for Driver_ADC121 in component ::Drivers:ADC +#define RTE_ADC121 1 +#if RTE_ADC121 + +// ADC121 DONE0 IRQ PRIORITY <0-225> +// defines ADC121 done0 interrupt priority +// default: 0 +#define RTE_ADC121_DONE0_IRQ_PRIORITY 0 + +// ADC121 DONE1 IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_DONE1_IRQ_PRIORITY 0 + +// ADC121 CMPA IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPA_IRQ_PRIORITY 0 + +// ADC121 CMPB IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC121_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC121_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC121_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC121_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC121_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC121_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC121_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC121_DIFFERENTIAL_EN 0 + +// Pga enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC121 using PGA gain +// Default: DISABLE +#define RTE_ADC121_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC121_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_BIAS 2 + +#endif +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] + +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] +// Configuration settings for Driver_ADC122 in component ::Drivers:ADC +#define RTE_ADC122 1 +#if RTE_ADC122 + +// ADC122 DONE0 IRQ PRIORITY <0-225> +// defines ADC122 done0 interrupt priority +// default: 0 +#define RTE_ADC122_DONE0_IRQ_PRIORITY 0 + +// ADC122 DONE1 IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_DONE1_IRQ_PRIORITY 0 + +// ADC122 CMPA IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPA_IRQ_PRIORITY 0 + +// ADC122 CMPB IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC122_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC122_CLOCK_DIV (2) + +// Sample Width <2-32> +// defines Width in divided clocks of the sample output signal +// default: 16 +#define RTE_ADC122_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC122_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC122_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC122_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC122_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC122_DIFFERENTIAL_EN 0 + +// Enable PGA ADC122 +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC122 using PGA gain +// Default: DISABLE +#define RTE_ADC122_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC122_PGA_GAIN (0) +// RTE_ADC122_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_BIAS 2 + +#endif +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] + +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// Configuration settings for Driver_ADC24 in component ::Drivers:ADC +#define RTE_ADC24 1 +#if RTE_ADC24 + +// ADC24 DONE0 IRQ PRIORITY <0-225> +// defines ADC24 done0 interrupt priority +// default: 0 +#define RTE_ADC24_DONE0_IRQ_PRIORITY 0 + +// ADC24 DONE1 IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_DONE1_IRQ_PRIORITY 0 + +// ADC24 CMPA IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPA_IRQ_PRIORITY 0 + +// ADC24 CMPB IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-4> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC24_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC24_CLOCK_DIV (2) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC24_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC24_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC24_SHIFT_LEFT_OR_RIGHT (1) + +// Ouput rate select +// <0=> 1 KS/s +// <1=> 2 KS/s +// <2=> 4 KS/s +// <3=> 8 KS/s +// <4=> 16 KS/s +// Defines Select adc24 output rate +// Default: 0 +#define RTE_ADC24_OUTPUT_RATE (0) + +// PGA enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable PGA to set PGA gain +// Default: DISABLE +#define RTE_ADC24_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC24_PGA_GAIN (0) + +// Bias Control +// <0=> 5 uA +// <1=> 6.25 uA +// <3=> 7.5 uA +// <7=> 8.75 uA +// Defines Bias control +// Default: 3 +#define RTE_ADC24_BIAS (3) + +#endif +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// ADC (Analog to Digital Converter) + +// CRC (Cyclic Redundancy Check) +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] +// Configuration settings for Driver_CRC0 in component ::Drivers:CRC +#define RTE_CRC0 1 +#if RTE_CRC0 + +// CRC0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC0 +// Default: 0 +#define RTE_CRC0_DMA_ENABLE 0 +#if RTE_CRC0_DMA_ENABLE + +// CRC0 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC0. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC0_SELECT_DMA 0 +#endif + +// CRC0 DMA IRQ priority <0-255> +// Defines CRC0 DMA Interrupt priority +// Default: 0 +#define RTE_CRC0_DMA_IRQ_PRI 0 +#endif +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] + +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// Configuration settings for Driver_CRC1 in component ::Drivers:CRC +#define RTE_CRC1 1 +#if RTE_CRC1 + +// CRC1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC1 +// Default: 0 +#define RTE_CRC1_DMA_ENABLE 0 +#if RTE_CRC1_DMA_ENABLE + +// CRC1 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC1. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC1_SELECT_DMA 0 +#endif + +// CRC1 DMA IRQ priority <0-255> +// Defines CRC1 DMA Interrupt priority +// Default: 0 +#define RTE_CRC1_DMA_IRQ_PRI 0 +#endif +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// + +// HWSEM (Hardware Semaphore) +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] +// Configuration settings for Driver_HWSEM0 in component ::Drivers:HWSEM +#define RTE_HWSEM0 1 +#if RTE_HWSEM0 + +// HWSEM0 IRQ priority <0-255> +// Defines HWSEM0 Interrupt priority +// Default: 0 +#define RTE_HWSEM0_IRQPRIORITY 0 +#endif + +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] +// Configuration settings for Driver_HWSEM1 in component ::Drivers:HWSEM +#define RTE_HWSEM1 0 +#if RTE_HWSEM1 + +// HWSEM1 IRQ priority <0-255> +// Defines HWSEM1 Interrupt priority +// Default: 0 +#define RTE_HWSEM1_IRQPRIORITY 0 +#endif + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] +// Configuration settings for Driver_HWSEM2 in component ::Drivers:HWSEM +#define RTE_HWSEM2 0 +#if RTE_HWSEM2 + +// HWSEM2 IRQ priority <0-255> +// Defines HWSEM2 Interrupt priority +// Default: 0 +#define RTE_HWSEM2_IRQPRIORITY 0 +#endif + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] +// Configuration settings for Driver_HWSEM3 in component ::Drivers:HWSEM +#define RTE_HWSEM3 0 +#if RTE_HWSEM3 + +// HWSEM3 IRQ priority <0-255> +// Defines HWSEM3 Interrupt priority +// Default: 0 +#define RTE_HWSEM3_IRQPRIORITY 0 +#endif + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] +// Configuration settings for Driver_HWSEM4 in component ::Drivers:HWSEM +#define RTE_HWSEM4 0 +#if RTE_HWSEM4 + +// HWSEM4 IRQ priority <0-255> +// Defines HWSEM4 Interrupt priority +// Default: 0 +#define RTE_HWSEM4_IRQPRIORITY 0 +#endif + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] +// Configuration settings for Driver_HWSEM5 in component ::Drivers:HWSEM +#define RTE_HWSEM5 0 +#if RTE_HWSEM5 + +// HWSEM5 IRQ priority <0-255> +// Defines HWSEM5 Interrupt priority +// Default: 0 +#define RTE_HWSEM5_IRQPRIORITY 0 +#endif + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] +// Configuration settings for Driver_HWSEM6 in component ::Drivers:HWSEM +#define RTE_HWSEM6 0 +#if RTE_HWSEM6 + +// HWSEM6 IRQ priority <0-255> +// Defines HWSEM6 Interrupt priority +// Default: 0 +#define RTE_HWSEM6_IRQPRIORITY 0 +#endif + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] +// Configuration settings for Driver_HWSEM7 in component ::Drivers:HWSEM +#define RTE_HWSEM7 0 +#if RTE_HWSEM7 + +// HWSEM7 IRQ priority <0-255> +// Defines HWSEM7 Interrupt priority +// Default: 0 +#define RTE_HWSEM7_IRQPRIORITY 0 +#endif + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] +// Configuration settings for Driver_HWSEM8 in component ::Drivers:HWSEM +#define RTE_HWSEM8 0 +#if RTE_HWSEM8 + +// HWSEM8 IRQ priority <0-255> +// Defines HWSEM8 Interrupt priority +// Default: 0 +#define RTE_HWSEM8_IRQPRIORITY 0 +#endif + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] +// Configuration settings for Driver_HWSEM9 in component ::Drivers:HWSEM +#define RTE_HWSEM9 0 +#if RTE_HWSEM9 + +// HWSEM9 IRQ priority <0-255> +// Defines HWSEM9 Interrupt priority +// Default: 0 +#define RTE_HWSEM9_IRQPRIORITY 0 +#endif + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] +// Configuration settings for Driver_HWSEM10 in component ::Drivers:HWSEM +#define RTE_HWSEM10 0 +#if RTE_HWSEM10 + +// HWSEM10 IRQ priority <0-255> +// Defines HWSEM10 Interrupt priority +// Default: 0 +#define RTE_HWSEM10_IRQPRIORITY 0 +#endif + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] +// Configuration settings for Driver_HWSEM11 in component ::Drivers:HWSEM +#define RTE_HWSEM11 0 +#if RTE_HWSEM11 + +// HWSEM11 IRQ priority <0-255> +// Defines HWSEM11 Interrupt priority +// Default: 0 +#define RTE_HWSEM11_IRQPRIORITY 0 +#endif + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] +// Configuration settings for Driver_HWSEM12 in component ::Drivers:HWSEM +#define RTE_HWSEM12 0 +#if RTE_HWSEM12 + +// HWSEM12 IRQ priority <0-255> +// Defines HWSEM12 Interrupt priority +// Default: 0 +#define RTE_HWSEM12_IRQPRIORITY 0 +#endif + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] +// Configuration settings for Driver_HWSEM13 in component ::Drivers:HWSEM +#define RTE_HWSEM13 0 +#if RTE_HWSEM13 + +// HWSEM13 IRQ priority <0-255> +// Defines HWSEM13 Interrupt priority +// Default: 0 +#define RTE_HWSEM13_IRQPRIORITY 0 +#endif + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] +// Configuration settings for Driver_HWSEM14 in component ::Drivers:HWSEM +#define RTE_HWSEM14 0 +#if RTE_HWSEM14 + +// HWSEM14 IRQ priority <0-255> +// Defines HWSEM14 Interrupt priority +// Default: 0 +#define RTE_HWSEM14_IRQPRIORITY 0 +#endif + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// Configuration settings for Driver_HWSEM15 in component ::Drivers:HWSEM +#define RTE_HWSEM15 0 +#if RTE_HWSEM15 + +// HWSEM15 IRQ priority <0-255> +// Defines HWSEM15 Interrupt priority +// Default: 0 +#define RTE_HWSEM15_IRQPRIORITY 0 +#endif + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// + +// High speed Analog Comparator +// CMP0 (Analog Comparator ) [Driver_CMP0] +// Configuration settings for Driver_CMP0 in component ::Drivers:Comparator +#define RTE_HSCMP0 1 +#if RTE_HSCMP0 + +// CMP0 IRQ priority <0-255> +// Defines Interrupt priority for CMP0. +// Default: 0 +#define RTE_CMP0_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_0 +// <1=> PIN_P0_6 +// <2=> PIN_P1_4 +// <3=> PIN_P0_4 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_0; 01 = P0_6; 10 = P1_4; 11 = P0_4 +// Default : 0 +#define RTE_CMP0_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP0_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP0_SEL_HYSTERISIS 7 + +#endif +// CMP0 (Analog Comparator) [Driver_CMP0] + +// CMP1 (Analog Comparator ) [Driver_CMP1] +// Configuration settings for Driver_CMP1 in component ::Drivers:Comparator +#define RTE_HSCMP1 1 +#if RTE_HSCMP1 + +// CMP1 IRQ priority <0-255> +// Defines Interrupt priority for CMP1. +// Default: 0 +#define RTE_CMP1_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_1 +// <1=> PIN_P0_7 +// <2=> PIN_P1_5 +// <3=> PIN_P0_5 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_1; 01 = P0_7; 10 = P1_5; 11 = P0_5 +// Default : 0 +#define RTE_CMP1_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP1_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP1_SEL_HYSTERISIS 7 + +#endif +// CMP1 (Analog Comparator) [Driver_CMP1] + +// CMP2 (Analog Comparator ) [Driver_CMP2] +// Configuration settings for Driver_CMP2 in component ::Drivers:Comparator +#define RTE_HSCMP2 1 +#if RTE_HSCMP2 + +// CMP2 IRQ priority <0-255> +// Defines Interrupt priority for CMP2. +// Default: 0 +#define RTE_CMP2_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_2 +// <1=> PIN_P1_0 +// <2=> PIN_P1_6 +// <3=> PIN_P1_2 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_2; 01 = P1_0; 10 = P1_6; 11 = P1_2 +// Default : 0 +#define RTE_CMP2_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP2_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP2_SEL_HYSTERISIS 7 + +#endif +// CMP2 (Analog Comparator) [Driver_CMP2] + +// CMP3 (Analog Comparator ) [Driver_CMP3] +// Configuration settings for Driver_CMP3 in component ::Drivers:Comparator +#define RTE_HSCMP3 1 +#if RTE_HSCMP3 + +// CMP3 IRQ priority <0-255> +// Defines Interrupt priority for CMP3. +// Default: 0 +#define RTE_CMP3_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_3 +// <1=> PIN_P1_1 +// <2=> PIN_P1_7 +// <3=> PIN_P1_3 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_3; 01 = P1_1; 10 = P1_7; 11 = P1_3 +// Default : 0 +#define RTE_CMP3_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP3_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP3_SEL_HYSTERISIS 7 + +#endif +// CMP3 (Analog Comparator) [Driver_CMP3] + +#if defined(RTSS_HE) +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +// Configuration settings for Driver_LPCMP in component ::Drivers:LPCMP +#define RTE_LPCMP 1 + +#if RTE_LPCMP + +// LPCMP IRQ priority <0-255> +// Defines Interrupt priority for LPCMP. +// Default: 0 +#define RTE_LPCMP_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P2_4 +// <1=> PIN_P2_5 +// <2=> PIN_P2_6 +// <3=> PIN_P2_7 +// Defines:select input to the positive terminal of LPCMP; +// 00 = P2_4; 01 = P2_5; 10 = P2_6; 11 = P2_7 +// Default : 0 +#define RTE_LPCMP_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> AON_VREF +// <1=> PIN_P2_0 +// <2=> PIN_P2_1 +// <3=> PIN_P2_2 +// Defines: select input to the negative terminal of LPCMP; +// 00 = AON Vref(0.8v); 01 = P2_0; 10 = P2_1 Vref; 11 = P2_2 +// Default : 0 +#define RTE_LPCMP_SEL_NEGATIVE 0 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select LPCMP hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_LPCMP_SEL_HYSTERISIS 7 + +#endif +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +#endif // defined(RTSS_HE) +// CMP (Analog Comparator) + +// I2C (Inter Integrated Circuit) +// I2C (Inter Integrated Circuit) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#if RTE_I2C0 + +// I2C0 IRQ priority <0-255> +// Defines Interrupt priority for I2C0. +// Default: 0 +#define RTE_I2C0_IRQ_PRIORITY 0 +// I2C0 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C0. +// Default: 16 +#define RTE_I2C0_TX_FIFO_THRESHOLD 16 + +// I2C0 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C0. +// Default: 0 +#define RTE_I2C0_RX_FIFO_THRESHOLD 0 + +// I2C0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C0 +// Default: DISABLE +#define RTE_I2C0_DMA_ENABLE 0 +#if RTE_I2C0_DMA_ENABLE + +// I2C0 DMA IRQ priority <0-255> +// Defines I2C0 DMA Interrupt priority +// Default: 0 +#define RTE_I2C0_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C0] + +// I2C (Inter Integrated Circuit) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#if RTE_I2C1 + +// I2C1 IRQ priority <0-255> +// Defines Interrupt priority for I2C1. +// Default: 0 +#define RTE_I2C1_IRQ_PRIORITY 0 +// I2C1 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C1. +// Default: 16 +#define RTE_I2C1_TX_FIFO_THRESHOLD 16 + +// I2C1 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C1. +// Default: 0 +#define RTE_I2C1_RX_FIFO_THRESHOLD 0 + +// I2C1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C1 +// Default: DISABLE +#define RTE_I2C1_DMA_ENABLE 0 +#if RTE_I2C1_DMA_ENABLE + +// I2C1 DMA IRQ priority <0-255> +// Defines I2C1 DMA Interrupt priority +// Default: 0 +#define RTE_I2C1_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C1] + +// I2C (Inter Integrated Circuit) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C + +#define RTE_I2C2 1 +#if RTE_I2C2 + +// I2C2 IRQ priority <0-255> +// Defines Interrupt priority for I2C2. +// Default: 0 +#define RTE_I2C2_IRQ_PRIORITY 0 +// I2C2 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C2. +// Default: 16 +#define RTE_I2C2_TX_FIFO_THRESHOLD 16 + +// I2C2 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C2. +// Default: 0 +#define RTE_I2C2_RX_FIFO_THRESHOLD 0 + +// I2C2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C2 +// Default: DISABLE +#define RTE_I2C2_DMA_ENABLE 0 +#if RTE_I2C2_DMA_ENABLE + +// I2C2 DMA IRQ priority <0-255> +// Defines I2C2 DMA Interrupt priority +// Default: 0 +#define RTE_I2C2_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C2] + +// I2C (Inter Integrated Circuit) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C + +#define RTE_I2C3 1 + +#if RTE_I2C3 + +// I2C3 IRQ priority <0-255> +// Defines Interrupt priority for I2C3. +// Default: 0 +#define RTE_I2C3_IRQ_PRIORITY 0 +// I2C3 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C3. +// Default: 16 +#define RTE_I2C3_TX_FIFO_THRESHOLD 16 + +// I2C3 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C3. +// Default: 0 +#define RTE_I2C3_RX_FIFO_THRESHOLD 0 + +// I2C3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C3 +// Default: DISABLE +#define RTE_I2C3_DMA_ENABLE 0 +#if RTE_I2C3_DMA_ENABLE + +// I2C3 DMA IRQ priority <0-255> +// Defines I2C3 DMA Interrupt priority +// Default: 0 +#define RTE_I2C3_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C3] + +// LPI2C0 (Low Power Inter-Integrated Circuit) [Driver_LPI2C0] +// Configuration settings for Driver_LPI2C0 in component ::Drivers:LPI2C +#if defined(RTSS_HE) +#define RTE_LPI2C0 1 +#if RTE_LPI2C0 + +// LPI2C0 IRQ PRIORITY <0-225> +// defines LPI2C0 interrupt priority +// default: 0 +#define RTE_LPI2C0_IRQ_PRIORITY 0 + +// LPI2C0 Bus-Speed <1-400000> +// defines LPI2C0 Bus-Speed - It is used for Bit-time calculation in driver +// default: 400KHz +#define RTE_LPI2C0_BUS_SPEED 400000 + +#endif +// LPI2C0(Low Power Inter-Integrated Circuit) [Driver_LPI2C0] +#endif // defined(RTSS_HE) +// + +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] +// Configuration settings for Driver_DMA0 in component ::Drivers:DMA +#define RTE_DMA0 1 +#if RTE_DMA0 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA0_APB_INTERFACE 0 +// DMA0 Abort interrupt priority <0-255> +// Defines DMA0 Abort interrupt priority. +// Default: 0 +#define RTE_DMA0_ABORT_IRQ_PRI 0 +// DMA0 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_IRQ_NS_STATE 0 +// DMA0 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_PERIPH_NS_STATE 0 +#endif +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] + +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] +#if defined(RTSS_HP) + +// Configuration settings for Driver_DMA1 in component ::Drivers:DMA +#define RTE_DMA1 1 +#if RTE_DMA1 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA1_APB_INTERFACE 0 +// DMA1 Abort interrupt priority <0-255> +// Defines DMA1 Abort interrupt priority. +// Default: 0 +#define RTE_DMA1_ABORT_IRQ_PRI 0 +// DMA1 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_IRQ_NS_STATE 0 +// DMA1 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] + +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] +// Configuration settings for Driver_DMA2 in component ::Drivers:DMA +#if defined(RTSS_HE) + +#define RTE_DMA2 1 +#if RTE_DMA2 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA2_APB_INTERFACE 0 +// DMA2 Abort interrupt priority <0-255> +// Defines DMA2 Abort interrupt priority. +// Default: 0 +#define RTE_DMA2_ABORT_IRQ_PRI 0 +// DMA2 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_IRQ_NS_STATE 0 +// DMA2 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] + +// GPIO (general purpose input and output) +// GPIO0 +// Configuration settings for Driver_GPIO0 in component ::Drivers:GPIO +#define RTE_GPIO0 1 + +#if RTE_GPIO0 + +// GPIO0 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO0. +// Default: 0 +#define RTE_GPIO0_DB_CLK_DIV 1 + +// GPIO0_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN0. +// Default: 0 +#define RTE_GPIO0_PIN0_IRQ_PRIORITY 0 + +// GPIO0_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN1. +// Default: 0 +#define RTE_GPIO0_PIN1_IRQ_PRIORITY 0 + +// GPIO0_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN2. +// Default: 0 +#define RTE_GPIO0_PIN2_IRQ_PRIORITY 0 + +// GPIO0_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN3. +// Default: 0 +#define RTE_GPIO0_PIN3_IRQ_PRIORITY 0 + +// GPIO0_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN4. +// Default: 0 +#define RTE_GPIO0_PIN4_IRQ_PRIORITY 0 + +// GPIO0_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN5. +// Default: 0 +#define RTE_GPIO0_PIN5_IRQ_PRIORITY 0 + +// GPIO0_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN6. +// Default: 0 +#define RTE_GPIO0_PIN6_IRQ_PRIORITY 0 + +// GPIO0_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN7. +// Default: 0 +#define RTE_GPIO0_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO0 + +// GPIO1 +// Configuration settings for Driver_GPIO1 in component ::Drivers:GPIO +#define RTE_GPIO1 1 + +#if RTE_GPIO1 + +// GPIO1 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO1. +// Default: 0 +#define RTE_GPIO1_DB_CLK_DIV 1 + +// GPIO1_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN0. +// Default: 0 +#define RTE_GPIO1_PIN0_IRQ_PRIORITY 0 + +// GPIO1_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN1. +// Default: 0 +#define RTE_GPIO1_PIN1_IRQ_PRIORITY 0 + +// GPIO1_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN2. +// Default: 0 +#define RTE_GPIO1_PIN2_IRQ_PRIORITY 0 + +// GPIO1_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO1_PIN3_IRQ_PRIORITY 0 + +// GPIO1_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN4. +// Default: 0 +#define RTE_GPIO1_PIN4_IRQ_PRIORITY 0 + +// GPIO1_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN5. +// Default: 0 +#define RTE_GPIO1_PIN5_IRQ_PRIORITY 0 + +// GPIO1_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN6. +// Default: 0 +#define RTE_GPIO1_PIN6_IRQ_PRIORITY 0 + +// GPIO1_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN7. +// Default: 0 +#define RTE_GPIO1_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO1 + +// GPIO2 +// Configuration settings for Driver_GPIO2 in component ::Drivers:GPIO +#define RTE_GPIO2 1 + +#if RTE_GPIO2 + +// GPIO2 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO2. +// Default: 0 +#define RTE_GPIO2_DB_CLK_DIV 1 + +// GPIO2_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN0. +// Default: 0 +#define RTE_GPIO2_PIN0_IRQ_PRIORITY 0 + +// GPIO2_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN1. +// Default: 0 +#define RTE_GPIO2_PIN1_IRQ_PRIORITY 0 + +// GPIO2_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN2. +// Default: 0 +#define RTE_GPIO2_PIN2_IRQ_PRIORITY 0 + +// GPIO2_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO2_PIN3_IRQ_PRIORITY 0 + +// GPIO2_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN4. +// Default: 0 +#define RTE_GPIO2_PIN4_IRQ_PRIORITY 0 + +// GPIO2_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN5. +// Default: 0 +#define RTE_GPIO2_PIN5_IRQ_PRIORITY 0 + +// GPIO2_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN6. +// Default: 0 +#define RTE_GPIO2_PIN6_IRQ_PRIORITY 0 + +// GPIO2_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN7. +// Default: 0 +#define RTE_GPIO2_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO2 + +// GPIO3 +// Configuration settings for Driver_GPIO3 in component ::Drivers:GPIO +#define RTE_GPIO3 1 + +#if RTE_GPIO3 + +// GPIO3 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO3. +// Default: 0 +#define RTE_GPIO3_DB_CLK_DIV 1 + +// GPIO3_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN0. +// Default: 0 +#define RTE_GPIO3_PIN0_IRQ_PRIORITY 0 + +// GPIO3_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN1. +// Default: 0 +#define RTE_GPIO3_PIN1_IRQ_PRIORITY 0 + +// GPIO3_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN2. +// Default: 0 +#define RTE_GPIO3_PIN2_IRQ_PRIORITY 0 + +// GPIO3_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN3. +// Default: 0 +#define RTE_GPIO3_PIN3_IRQ_PRIORITY 0 + +// GPIO3_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN4. +// Default: 0 +#define RTE_GPIO3_PIN4_IRQ_PRIORITY 0 + +// GPIO3_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN5. +// Default: 0 +#define RTE_GPIO3_PIN5_IRQ_PRIORITY 0 + +// GPIO3_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN6. +// Default: 0 +#define RTE_GPIO3_PIN6_IRQ_PRIORITY 0 + +// GPIO3_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN7. +// Default: 0 +#define RTE_GPIO3_PIN7_IRQ_PRIORITY 0 + +// GPIO3_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO3 + +// GPIO4 +// Configuration settings for Driver_GPIO4 in component ::Drivers:GPIO +#define RTE_GPIO4 1 + +#if RTE_GPIO4 + +// GPIO4 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO4. +// Default: 0 +#define RTE_GPIO4_DB_CLK_DIV 1 + +// GPIO4_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN0. +// Default: 0 +#define RTE_GPIO4_PIN0_IRQ_PRIORITY 0 + +// GPIO4_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN1. +// Default: 0 +#define RTE_GPIO4_PIN1_IRQ_PRIORITY 0 + +// GPIO4_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN2. +// Default: 0 +#define RTE_GPIO4_PIN2_IRQ_PRIORITY 0 + +// GPIO4_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN3. +// Default: 0 +#define RTE_GPIO4_PIN3_IRQ_PRIORITY 0 + +// GPIO4_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN4. +// Default: 0 +#define RTE_GPIO4_PIN4_IRQ_PRIORITY 0 + +// GPIO4_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN5. +// Default: 0 +#define RTE_GPIO4_PIN5_IRQ_PRIORITY 0 + +// GPIO4_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN6. +// Default: 0 +#define RTE_GPIO4_PIN6_IRQ_PRIORITY 0 + +// GPIO4_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN7. +// Default: 0 +#define RTE_GPIO4_PIN7_IRQ_PRIORITY 0 + +// GPIO4_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// GPIO4 + +// GPIO5 +// Configuration settings for Driver_GPIO5 in component ::Drivers:GPIO +#define RTE_GPIO5 1 + +#if RTE_GPIO5 + +// GPIO5 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO5. +// Default: 0 +#define RTE_GPIO5_DB_CLK_DIV 1 + +// GPIO5_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN0. +// Default: 0 +#define RTE_GPIO5_PIN0_IRQ_PRIORITY 0 + +// GPIO5_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN1. +// Default: 0 +#define RTE_GPIO5_PIN1_IRQ_PRIORITY 0 + +// GPIO5_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN2. +// Default: 0 +#define RTE_GPIO5_PIN2_IRQ_PRIORITY 0 + +// GPIO5_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN3. +// Default: 0 +#define RTE_GPIO5_PIN3_IRQ_PRIORITY 0 + +// GPIO5_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN4. +// Default: 0 +#define RTE_GPIO5_PIN4_IRQ_PRIORITY 0 + +// GPIO5_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN5. +// Default: 0 +#define RTE_GPIO5_PIN5_IRQ_PRIORITY 0 + +// GPIO5_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN6. +// Default: 0 +#define RTE_GPIO5_PIN6_IRQ_PRIORITY 0 + +// GPIO5_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN7. +// Default: 0 +#define RTE_GPIO5_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO5 + +// GPIO6 +// Configuration settings for Driver_GPIO6 in component ::Drivers:GPIO +#define RTE_GPIO6 1 + +#if RTE_GPIO6 + +// GPIO6 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO6. +// Default: 0 +#define RTE_GPIO6_DB_CLK_DIV 1 + +// GPIO6_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN0. +// Default: 0 +#define RTE_GPIO6_PIN0_IRQ_PRIORITY 0 + +// GPIO6_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN1. +// Default: 0 +#define RTE_GPIO6_PIN1_IRQ_PRIORITY 0 + +// GPIO6_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN2. +// Default: 0 +#define RTE_GPIO6_PIN2_IRQ_PRIORITY 0 + +// GPIO6_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN3. +// Default: 0 +#define RTE_GPIO6_PIN3_IRQ_PRIORITY 0 + +// GPIO6_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN4. +// Default: 0 +#define RTE_GPIO6_PIN4_IRQ_PRIORITY 0 + +// GPIO6_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN5. +// Default: 0 +#define RTE_GPIO6_PIN5_IRQ_PRIORITY 0 + +// GPIO6_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN6. +// Default: 0 +#define RTE_GPIO6_PIN6_IRQ_PRIORITY 0 + +// GPIO6_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN7. +// Default: 0 +#define RTE_GPIO6_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO6 + +// GPIO7 +// Configuration settings for Driver_GPIO7 in component ::Drivers:GPIO +#define RTE_GPIO7 1 + +#if RTE_GPIO7 + +// GPIO7 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO7. +// Default: 0 +#define RTE_GPIO7_DB_CLK_DIV 1 + +// GPIO7_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN0. +// Default: 0 +#define RTE_GPIO7_PIN0_IRQ_PRIORITY 0 + +// GPIO7_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN1. +// Default: 0 +#define RTE_GPIO7_PIN1_IRQ_PRIORITY 0 + +// GPIO7_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN2. +// Default: 0 +#define RTE_GPIO7_PIN2_IRQ_PRIORITY 0 + +// GPIO7_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN3. +// Default: 0 +#define RTE_GPIO7_PIN3_IRQ_PRIORITY 0 + +// GPIO7_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN4. +// Default: 0 +#define RTE_GPIO7_PIN4_IRQ_PRIORITY 0 + +// GPIO7_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN5. +// Default: 0 +#define RTE_GPIO7_PIN5_IRQ_PRIORITY 0 + +// GPIO7_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN6. +// Default: 0 +#define RTE_GPIO7_PIN6_IRQ_PRIORITY 0 + +// GPIO7_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN7. +// Default: 0 +#define RTE_GPIO7_PIN7_IRQ_PRIORITY 0 + +// GPIO7_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO7 + +// GPIO8 +// Configuration settings for Driver_GPIO8 in component ::Drivers:GPIO +#define RTE_GPIO8 1 + +#if RTE_GPIO8 + +// GPIO8 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO8. +// Default: 0 +#define RTE_GPIO8_DB_CLK_DIV 1 + +// GPIO8_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN0. +// Default: 0 +#define RTE_GPIO8_PIN0_IRQ_PRIORITY 0 + +// GPIO8_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN1. +// Default: 0 +#define RTE_GPIO8_PIN1_IRQ_PRIORITY 0 + +// GPIO8_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN2. +// Default: 0 +#define RTE_GPIO8_PIN2_IRQ_PRIORITY 0 + +// GPIO8_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN3. +// Default: 0 +#define RTE_GPIO8_PIN3_IRQ_PRIORITY 0 + +// GPIO8_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN4. +// Default: 0 +#define RTE_GPIO8_PIN4_IRQ_PRIORITY 0 + +// GPIO8_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN5. +// Default: 0 +#define RTE_GPIO8_PIN5_IRQ_PRIORITY 0 + +// GPIO8_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN6. +// Default: 0 +#define RTE_GPIO8_PIN6_IRQ_PRIORITY 0 + +// GPIO8_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN7. +// Default: 0 +#define RTE_GPIO8_PIN7_IRQ_PRIORITY 0 + +// GPIO8_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO8 + +// GPIO9 +// Configuration settings for Driver_GPIO9 in component ::Drivers:GPIO +#define RTE_GPIO9 1 + +#if RTE_GPIO9 + +// GPIO9 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO9. +// Default: 0 +#define RTE_GPIO9_DB_CLK_DIV 1 + +// GPIO9_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN0. +// Default: 0 +#define RTE_GPIO9_PIN0_IRQ_PRIORITY 0 + +// GPIO9_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN1. +// Default: 0 +#define RTE_GPIO9_PIN1_IRQ_PRIORITY 0 + +// GPIO9_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN2. +// Default: 0 +#define RTE_GPIO9_PIN2_IRQ_PRIORITY 0 + +// GPIO9_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN3. +// Default: 0 +#define RTE_GPIO9_PIN3_IRQ_PRIORITY 0 + +// GPIO9_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN4. +// Default: 0 +#define RTE_GPIO9_PIN4_IRQ_PRIORITY 0 + +// GPIO9_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN5. +// Default: 0 +#define RTE_GPIO9_PIN5_IRQ_PRIORITY 0 + +// GPIO9_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN6. +// Default: 0 +#define RTE_GPIO9_PIN6_IRQ_PRIORITY 0 + +// GPIO9_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN7. +// Default: 0 +#define RTE_GPIO9_PIN7_IRQ_PRIORITY 0 + +// GPIO9_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO9 + +// GPIO10 +// Configuration settings for Driver_GPIO10 in component ::Drivers:GPIO +#define RTE_GPIO10 1 + +#if RTE_GPIO10 + +// GPIO10 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO10. +// Default: 0 +#define RTE_GPIO10_DB_CLK_DIV 1 + +// GPIO10_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN0. +// Default: 0 +#define RTE_GPIO10_PIN0_IRQ_PRIORITY 0 + +// GPIO10_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN1. +// Default: 0 +#define RTE_GPIO10_PIN1_IRQ_PRIORITY 0 + +// GPIO10_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN2. +// Default: 0 +#define RTE_GPIO10_PIN2_IRQ_PRIORITY 0 + +// GPIO10_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN3. +// Default: 0 +#define RTE_GPIO10_PIN3_IRQ_PRIORITY 0 + +// GPIO10_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN4. +// Default: 0 +#define RTE_GPIO10_PIN4_IRQ_PRIORITY 0 + +// GPIO10_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN5. +// Default: 0 +#define RTE_GPIO10_PIN5_IRQ_PRIORITY 0 + +// GPIO10_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN6. +// Default: 0 +#define RTE_GPIO10_PIN6_IRQ_PRIORITY 0 + +// GPIO10_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN7. +// Default: 0 +#define RTE_GPIO10_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO10 + +// GPIO11 +// Configuration settings for Driver_GPIO11 in component ::Drivers:GPIO +#define RTE_GPIO11 1 + +#if RTE_GPIO11 + +// GPIO11 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO11. +// Default: 0 +#define RTE_GPIO11_DB_CLK_DIV 1 + +// GPIO11_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN0. +// Default: 0 +#define RTE_GPIO11_PIN0_IRQ_PRIORITY 0 + +// GPIO11_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN1. +// Default: 0 +#define RTE_GPIO11_PIN1_IRQ_PRIORITY 0 + +// GPIO11_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN2. +// Default: 0 +#define RTE_GPIO11_PIN2_IRQ_PRIORITY 0 + +// GPIO11_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN3. +// Default: 0 +#define RTE_GPIO11_PIN3_IRQ_PRIORITY 0 + +// GPIO11_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN4. +// Default: 0 +#define RTE_GPIO11_PIN4_IRQ_PRIORITY 0 + +// GPIO11_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN5. +// Default: 0 +#define RTE_GPIO11_PIN5_IRQ_PRIORITY 0 + +// GPIO11_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN6. +// Default: 0 +#define RTE_GPIO11_PIN6_IRQ_PRIORITY 0 + +// GPIO11_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN7. +// Default: 0 +#define RTE_GPIO11_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO11 + +// GPIO12 +// Configuration settings for Driver_GPIO12 in component ::Drivers:GPIO +#define RTE_GPIO12 1 + +#if RTE_GPIO12 + +// GPIO12 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO12. +// Default: 0 +#define RTE_GPIO12_DB_CLK_DIV 1 + +// GPIO12_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN0. +// Default: 0 +#define RTE_GPIO12_PIN0_IRQ_PRIORITY 0 + +// GPIO12_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN1. +// Default: 0 +#define RTE_GPIO12_PIN1_IRQ_PRIORITY 0 + +// GPIO12_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN2. +// Default: 0 +#define RTE_GPIO12_PIN2_IRQ_PRIORITY 0 + +// GPIO12_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN3. +// Default: 0 +#define RTE_GPIO12_PIN3_IRQ_PRIORITY 0 + +// GPIO12_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN4. +// Default: 0 +#define RTE_GPIO12_PIN4_IRQ_PRIORITY 0 + +// GPIO12_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN5. +// Default: 0 +#define RTE_GPIO12_PIN5_IRQ_PRIORITY 0 + +// GPIO12_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN6. +// Default: 0 +#define RTE_GPIO12_PIN6_IRQ_PRIORITY 0 + +// GPIO12_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN7. +// Default: 0 +#define RTE_GPIO12_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO12 + +// GPIO13 +// Configuration settings for Driver_GPIO13 in component ::Drivers:GPIO +#define RTE_GPIO13 1 + +#if RTE_GPIO13 + +// GPIO13 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO13. +// Default: 0 +#define RTE_GPIO13_DB_CLK_DIV 1 + +// GPIO13_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN0. +// Default: 0 +#define RTE_GPIO13_PIN0_IRQ_PRIORITY 0 + +// GPIO13_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN1. +// Default: 0 +#define RTE_GPIO13_PIN1_IRQ_PRIORITY 0 + +// GPIO13_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN2. +// Default: 0 +#define RTE_GPIO13_PIN2_IRQ_PRIORITY 0 + +// GPIO13_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN3. +// Default: 0 +#define RTE_GPIO13_PIN3_IRQ_PRIORITY 0 + +// GPIO13_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN4. +// Default: 0 +#define RTE_GPIO13_PIN4_IRQ_PRIORITY 0 + +// GPIO13_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN5. +// Default: 0 +#define RTE_GPIO13_PIN5_IRQ_PRIORITY 0 + +// GPIO13_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN6. +// Default: 0 +#define RTE_GPIO13_PIN6_IRQ_PRIORITY 0 + +// GPIO13_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN7. +// Default: 0 +#define RTE_GPIO13_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO13 + +// GPIO14 +// Configuration settings for Driver_GPIO14 in component ::Drivers:GPIO +#define RTE_GPIO14 1 + +#if RTE_GPIO14 + +// GPIO14 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO14. +// Default: 0 +#define RTE_GPIO14_DB_CLK_DIV 1 + +// GPIO14_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN0. +// Default: 0 +#define RTE_GPIO14_PIN0_IRQ_PRIORITY 0 + +// GPIO14_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN1. +// Default: 0 +#define RTE_GPIO14_PIN1_IRQ_PRIORITY 0 + +// GPIO14_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN2. +// Default: 0 +#define RTE_GPIO14_PIN2_IRQ_PRIORITY 0 + +// GPIO14_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN3. +// Default: 0 +#define RTE_GPIO14_PIN3_IRQ_PRIORITY 0 + +// GPIO14_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN4. +// Default: 0 +#define RTE_GPIO14_PIN4_IRQ_PRIORITY 0 + +// GPIO14_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN5. +// Default: 0 +#define RTE_GPIO14_PIN5_IRQ_PRIORITY 0 + +// GPIO14_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN6. +// Default: 0 +#define RTE_GPIO14_PIN6_IRQ_PRIORITY 0 + +// GPIO14_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN7. +// Default: 0 +#define RTE_GPIO14_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO14 + +// LPGPIO +// Configuration settings for Driver_LPGPIO in component ::Drivers:GPIO +#define RTE_LPGPIO 1 + +#if RTE_LPGPIO + +// LPGPIO_PIN0 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN0. +// Default: 0 +#define RTE_LPGPIO_PIN0_IRQ_PRIORITY 0 + +// LPGPIO_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN1 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN1. +// Default: 0 +#define RTE_LPGPIO_PIN1_IRQ_PRIORITY 0 + +// LPGPIO_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN2 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN2. +// Default: 0 +#define RTE_LPGPIO_PIN2_IRQ_PRIORITY 0 + +// LPGPIO_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN3 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN3. +// Default: 0 +#define RTE_LPGPIO_PIN3_IRQ_PRIORITY 0 + +// LPGPIO_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN4 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN4. +// Default: 0 +#define RTE_LPGPIO_PIN4_IRQ_PRIORITY 0 + +// LPGPIO_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN5 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN5. +// Default: 0 +#define RTE_LPGPIO_PIN5_IRQ_PRIORITY 0 + +// LPGPIO_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN6 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN6. +// Default: 0 +#define RTE_LPGPIO_PIN6_IRQ_PRIORITY 0 + +// LPGPIO_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN7 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN7. +// Default: 0 +#define RTE_LPGPIO_PIN7_IRQ_PRIORITY 0 + +// LPGPIO_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// LPGPIO + +// GPIO (general purpose input and output) + +// PDM(Pulse Density Modulation) +// PDM (Pulse density modulation) [Driver_PDM] +// Configuration settings for Driver_PDM in component ::Drivers:PDM +#define RTE_PDM 1 +#if RTE_PDM + +// PDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for PDM +// Default: ENABLE +#define RTE_PDM_DMA_ENABLE 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_PDM_DMA_IRQ_PRIORITY 0 + +// PDM IRQ priority <0-255> +// Defines Interrupt priority for PDM. +// Default: 0 +#define RTE_PDM_IRQ_PRIORITY 0 + +// PDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_PDM_FIFO_WATERMARK 5 + +#endif +// PDM (Pulse density modulation) [Driver_PDM] + +// PDM (Pulse density modulation) + +#if defined(RTSS_HE) +// LPPDM(Low Power Pulse Density Modulation) +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +// Configuration settings for Driver_LPPDM in component ::Drivers:LPPDM +#define RTE_LPPDM 1 + +#if RTE_LPPDM + +// LPPDM IRQ priority <0-255> +// Defines Interrupt priority for LPPDM. +// Default: 0 +#define RTE_LPPDM_IRQ_PRIORITY 0 + +// LPPDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_LPPDM_FIFO_WATERMARK 5 + +// LPPDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPPDM +// Default: ENABLE +#define RTE_LPPDM_DMA_ENABLE 0 +#if RTE_LPPDM_DMA_ENABLE + +// LPPDM DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPPDM. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPPDM_SELECT_DMA0 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_LPPDM_DMA_IRQ_PRIORITY 0 +#endif +#endif +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +#endif // defined(RTSS_HE) +// LPPDM (Low Power Pulse density modulation) + +// CANFD (Controller Area Network - Fast Mode) +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// Configuration settings for Driver_CANFD0 in component ::Drivers:CANFD +#define RTE_CANFD0 1 + +#if RTE_CANFD0 + +// CANFD0 IRQ priority <0-255> +// Defines Interrupt priority for CANFD0. +// Default: 0 +#define RTE_CANFD0_IRQ_PRIORITY 0 + +// CANFD0 Clock Source +// <0=> 38.4 MHz Clock +// <1=> 160 MHz Clock +// Defines Clock Source for CANFD0. +// Default: 160 MHz +#define RTE_CANFD0_CLK_SOURCE 1 + +// CANFD0 Clock Speed (Hz) <160000-80000000> +// Defines Clock Speed for CANFD0. +// Maximum Clock speed is 80MHz +// Recommended speeds with 160MHz clock source: 20MHz, 40MHz, 80MHz +// Default: 20MHz +#define RTE_CANFD0_CLK_SPEED 20000000 + +// CANFD0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for CANFD0 +// Default: DISABLE +#define RTE_CANFD0_BLOCKING_MODE_ENABLE 0 + +#endif +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// CANFD (Controller Area Network - Fast Mode) + +// SDC (Secure Digital Controller) +// SDC (Secure Digital Controller 0) [Driver_SDC0] +// Configuration settings for Driver_SDC0 in component ::Drivers:SDC +#define RTE_SDC 1 + +#if RTE_SDC + +// SDC BUS WIDTH SELECT +// <0=> BUS_WIDTH_1BIT +// <1=> BUS_WIDTH_4BIT +// Defines SDC0 size of bus width +// Default: BUS_WIDTH_4BIT +#define RTE_SDC_BUS_WIDTH 1 + +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz +// Default: 25MHz +#define RTE_SDC_CLOCK_SELECT 25000000 + +// SDC DMA SELECT +// <0=> SDMA +// <1=> ADMA2 +// Defines SDC0 DMA select +// Default: ADMA2 +#define RTE_SDC_DMA_SELECT 1 + +// SDC IRQ MODE SELECT +// <0=> Polling Mode +// <1=> IRQ Mode +// Defines SDC IRQ MODE select +// Default: IRQ MODE +#define RTE_SDC_IRQ_MODE_SELECT 1 + +// SDC IRQ priority <0-255> +// Defines SDC Interrupt priority +// Default: 0 +#define RTE_SDC_IRQ_PRI 0 + +// SDC WAKEUP IRQ priority <0-255> +// Defines SDC Wakeup Interrupt priority +// Default: 0 +#define RTE_SDC_WAKEUP_IRQ_PRI 0 + +#endif +// SDC0 (Secure Digital Controller 0) [Driver_SDC0] +// SDC (Secure Digital Controller) + +// ETH_MAC (Ethernet MAC) +// ETH_MAC (Ethernet MAC) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:ETH_MAC +#define RTE_ETH_MAC 1 + +#if RTE_ETH_MAC + +// ETH MAC IRQ priority <0-255> +// Defines ETH MAC Interrupt priority +// Default: 0 +#define RTE_ETH_MAC_IRQ_PRIORITY 0 + +#endif +// ETH (Ethernet MAC) [Driver_ETH_MAC0] +// ETH (Ethernet MAC) + +// Power Management (PM) +// Handle Spurious Wakeup +// <0=> Disable +// <1=> Enable +// define Handle Spurious Wakeup +// default: Enable +#define PM_HANDLE_SPURIOUS_WAKEUP 1 +// Power Management (PM) + +#endif /* __RTE_DEVICE_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 new file mode 100644 index 0000000..d189a2f --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/RTE_Device.h.base@2.2.0 @@ -0,0 +1,9675 @@ +/* Copyright (C) 2022 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] +// Configuration settings for Driver_MRAM in component ::Drivers:MRAM +#define RTE_MRAM 1 +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] + +// CPI (Camera) [Driver_CPI] +// Configuration settings for Driver_CPI in component ::Drivers:CPI +#define RTE_CPI 1 +#if RTE_CPI + +// CPI interrupt priority <0-255> +// Defines CPI interrupt priority. +// Default: 0 +#define RTE_CPI_IRQ_PRI 0 + +// CPI CSI halt enable/disable +// <0=> disable +// <1=> enable +// Defines CPI CSI halt enable/disable. +// Default: 0 +#define RTE_CPI_CSI_HALT 0 + +// CPI Row roundup +// <0=> disable +// <1=> enable +// Defines CPI row roundup to 64 bit. +// Default: 0 +#define RTE_CPI_ROW_ROUNDUP 0 + +// CPI FIFO read watermark +// Defines FIFO read watermark. +// Default: 0x8 +#define RTE_CPI_FIFO_READ_WATERMARK 0x8 + +// CPI FIFO write watermark +// Defines CPI FIFO write watermark. +// Default: 0x18 +#define RTE_CPI_FIFO_WRITE_WATERMARK 0x18 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE 0 + +#if (RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_CPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// <4=> 16 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_CODE10ON8 0 + +// Select camera MT9M114 data mask +// <0=> 16 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit +// Defines camera MT9M114 data mask +// Default: 10 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MASK 1 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// CPI (Camera) [Driver_CPI] + +// LPCPI (Camera) [Driver_LPCPI] +// Configuration settings for Driver_LPCPI in component ::Drivers:LPCPI +#define RTE_LPCPI 0 +#if RTE_LPCPI + +// LPCPI interrupt priority <0-255> +// Defines LPCPI interrupt priority. +// Default: 0 +#define RTE_LPCPI_IRQ_PRI 0 + +// LPCPI Row roundup +// <0=> disable +// <1=> enable +// Defines LPCPI row roundup to 64 bit. +// Default: 0 +#define RTE_LPCPI_ROW_ROUNDUP 0 + +// LPCPI FIFO read watermark +// Defines LPCPI FIFO read watermark. +// Default: 0x8 +#define RTE_LPCPI_FIFO_READ_WATERMARK 0x8 + +// LPCPI FIFO write watermark +// Defines LPCPI FIFO write watermark. +// Default: 0x18 +#define RTE_LPCPI_FIFO_WRITE_WATERMARK 0x18 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_CODE10ON8 0 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// LPCPI (Camera) [Driver_LPCPI] + +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] +// Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 +#define RTE_MIPI_CSI2 1 +#if RTE_MIPI_CSI2 + +// Select CSI2 DPHY backend +// Selects CSI2 RX DPHY to be used by Driver_MIPI_CSI2. +// Default: CSI2 RX DPHY +#define RTE_MIPI_CSI2_DPHY_BACKEND 0 + +// CSI pixel clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CSI pixel clock select +// Default: Select AXI clock source +#define RTE_CSI2_PIX_CLK_SEL 0 + +// select IPI mode +// <0=> camera mode +// <1=> controller mode +// defines select IPI mode +// default: camera mode +#define RTE_MIPI_CSI2_IPI_MODE 0 + +// select memory flush +// <0=> manual +// <1=> auto +// defines select memory flush +// default: auto +#define RTE_MIPI_CSI2_MEMFLUSH 1 + +// select sync event mode +// <0=> not trigger by frame start +// <1=> trigger by frame start +// defines select sync event mode +// default : not trigger by frame start +#define RTE_MIPI_CSI2_SYNC_ET_MODE 0 + +// select sync event select +// <0=> auto +// <1=> programmed +// defines select sync event select +// default : programmed +#define RTE_MIPI_CSI2_SYNC_ET_SEL 1 + +// embedded packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use embedded packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_EMBEDDED 0 + +// blanking packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use blanking packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_BLANKING 0 + +// null packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use null packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_NULL 0 + +// line start packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use line start packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_LINE_START 0 + +// video packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use video packets for IPI synchronization events +// default: enable +#define RTE_MIPI_CSI2_EN_VIDEO 1 + +// datatype to overwrite +// select CSI2 Data type to overwrite +// <24=> YUV420_8 +// <25=> YUV420_10 +// <26=> YUV420_8_LEGACY +// <28=> YUV420_8_SHIFT +// <29=> YUV420_10_SHIFT +// <30=> YUV422_8 +// <31=> YUV422_10 +// <32=> RGB444 +// <33=> RGB555 +// <34=> RGB565 +// <35=> RGB666 +// <36=> RGB888 +// <40=> RAW6 +// <41=> RAW7 +// <42=> RAW8 +// <43=> RAW10 +// <44=> RAW12 +// <45=> RAW14 +// <46=> RAW16 +// <48=> USER_DEFINED_1 +// <49=> USER_DEFINED_2 +// <50=> USER_DEFINED_3 +// <51=> USER_DEFINED_4 +// <52=> USER_DEFINED_5 +// <53=> USER_DEFINED_6 +// <54=> USER_DEFINED_7 +// <55=> USER_DEFINED_8 +// defines select CSI2 Data type to be overwrite +// default: RAW10 +#define RTE_MIPI_CSI2_EN_DT 43 + +// datatype to overwrite with programmed datatype +// define if want to use programmed datatype ignoring datatype of the header +// default: 0 +#define RTE_MIPI_CSI2_EN_DT_OVERWRITE 0 + +// Horizontal Synchronism Active Time range <0-2047> +// Defines possible range for selecting horizontal sync active time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HSA_TIME 5 + +// Horizontal Synchronism back porch Time range <0-2047> +// Defines possible range for selecting horizontal sync back porch time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HBP_TIME 10 + +// Horizontal sync delay Time range <0-2047> +// Defines possible range for selecting horizontal sync delay time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HSD_TIME 280 + +// Horizontal Active Time range <0-2047> +// Defines possible range for selecting horizontal active time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HACTIVE_TIME 560 + +// Vertical sync active period range <0-511> +// Defines possible range for selecting vertical sync active period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VSA_LINE 4 + +// Vertical back porch period range <0-511> +// Defines possible range for selecting vertical back porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VBP_LINE 4 + +// Vertical front porch period range <0-511> +// Defines possible range for selecting vertical front porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VFP_LINE 4 + +// Vertical active period range <0-8191> +// Defines possible range for selecting vertical active period +// Default: 560 +#define RTE_MIPI_CSI2_IPI_VACTIVE_LINE 560 + +// CSI2 interrupt priority <0-255> +// Defines CSI2 interrupt priority. +// Default: 0 +#define RTE_MIPI_CSI2_IRQ_PRI 0 + +// ARX3A0 [Driver_ARX3A0] +// Enable/Disable ARX3A0 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable ARX3A0 camera sensor +// default: enable +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera ARX3A0 frame per second +// <5=> 5 FPS +// <40=> 40 FPS +// <60=> 60 FPS +// <90=> 90 FPS +// Defines camera ARX3A0 frame per second +// Default: 90 FPS +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CFG_FPS 90 + +// Select camera ARX3A0 frequency +// Defines camera ARX3A0 frequency +// Default: 400000000 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select ARX3A0 CSI2 Data type +// defines select CSI2 Data type +// default: 43(RAW10) +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_DATA_TYPE 43 + +// select ARX3A0 number of lanes in DPHY +// defines select ARX3A0 number of lanes in DPHY. +// default: 2 two lane +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_N_LANES 2 + +// select ARX3A0 virtual channel ID +// defines select ARX3A0 virtual channel ID. +// default: 0 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_VC_ID 0 + +// select ARX3A0 override CPI color mode +// defines select ARX3A0 override CPI color mode. +// default: 1 (Ensable) +#define RTE_ARX3A0_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select ARX3A0 CPI color mode +// defines select ARX3A0 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_ARX3A0_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select ARX3A0 frame height +// defines select ARX3A0 frame height. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_HEIGHT 560 + +// select ARX3A0 frame width +// defines select ARX3A0 frame width. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_WIDTH 560 + +// Select camera sensor ARX3A0 CSI clock source division [Divisor] <2-511> +// Defines camera sensor ARX3A0 CSI clock source division +// Default: 20 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor ARX3A0 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// ARX3A0 [Driver_ARX3A0] + +// AR0144 [Driver_AR0144] +// Enable/Disable AR0144 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0144 camera sensor +// default: enable +#define RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0144 frequency +// Defines camera AR0144 frequency +// Default: 225000000 +#define RTE_AR0144_CAMERA_SENSOR_CSI_FREQ 225000000 + +// select AR0144 CSI2 Data type +// defines select CSI2 Data type +// default: 44(RAW12) +#define RTE_AR0144_CAMERA_SENSOR_CSI_DATA_TYPE 44 + +// select AR0144 number of lanes in DPHY +// defines select AR0144 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0144_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0144 virtual channel ID +// defines select AR0144 virtual channel ID. +// default: 0 +#define RTE_AR0144_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0144 override CPI color mode +// defines select AR0144 override CPI color mode. +// default: 1 (Ensable) +#define RTE_AR0144_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0144 CPI color mode +// defines select AR0144 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0144_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0144 frame height +// defines select AR0144 frame height. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_HEIGHT 800 + +// select AR0144 frame width +// defines select AR0144 frame width. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_WIDTH 1280 + +// Select camera sensor AR0144 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0144 CSI clock source division +// Default: 20 +#define RTE_AR0144_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0144 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0114 [Driver_AR0114] + +// AR0145 [Driver_AR0145] +// Enable/Disable AR0145 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0145 camera sensor +// default: enable +#define RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0145 frequency +// Defines camera AR0145 frequency +// Default: 400000000 +#define RTE_AR0145_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select AR0145 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2A(RAW8) +#define RTE_AR0145_CAMERA_SENSOR_CSI_DATA_TYPE 0x2A + +// select AR0145 number of lanes in DPHY +// defines select AR0145 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0145_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0145 virtual channel ID +// defines select AR0145 virtual channel ID. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0145 override CPI color mode +// defines select AR0145 override CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select AR0145 CPI color mode +// defines select AR0145 CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +// select AR0145 Image configuration +// Defines camera sensor AR0145 Image configuration +// <0=> 1280x800_Full_1M +// <1=> 640x400_YSum2_XBin2 +// <2=> 640x400_YSkip2_XSkip2 +// <3=> 320x200_YSkip2_XSkip2 +// Default: 0 +#define RTE_AR0145_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// Select camera sensor AR0145 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0145 CSI clock source division +// Default: 16 +#define RTE_AR0145_CAMERA_SENSOR_CSI_CLK_SCR_DIV 16 + +// RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0145 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0145 [Driver_AR0145] + +// AR0246 [Driver_AR0246] +// Enable/Disable AR0246 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0246 camera sensor +// default: enable +#define RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0246 frequency +// Defines camera AR0246 frequency +// Default: 442000000 +#define RTE_AR0246_CAMERA_SENSOR_CSI_FREQ 442000000 + +// select AR0246 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2C(RAW12) +#define RTE_AR0246_CAMERA_SENSOR_CSI_DATA_TYPE 0x2C + +// select AR0246 number of lanes in DPHY +// defines select AR0246 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0246_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0246 virtual channel ID +// defines select AR0246 virtual channel ID. +// default: 0 +#define RTE_AR0246_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0246 override CPI color mode +// defines select AR0246 override CPI color mode. +// default: 1 (Enable) +#define RTE_AR0246_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0246 CPI color mode +// defines select AR0246 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0246_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0246 frame height +// defines select AR0246 frame height. +// default: 472 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_HEIGHT 472 + +// select AR0246 frame width +// defines select AR0246 frame width. +// default: 684 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_WIDTH 684 + +// Select camera sensor AR0246 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0246 CSI clock source division +// Default: 15 +#define RTE_AR0246_CAMERA_SENSOR_CSI_CLK_SCR_DIV 15 + +// RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0246 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0246 [Driver_AR0246] + +// MT9M114_MIPI [Driver_MT9M114_MIPI] +// Enable/Disable MT9M114 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 MIPI camera sensor +// default: enable +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE) + +// Select camera MT9M114 MIPI frequency +// Defines camera MT9M114 MIPI frequency +// Default: 296000000 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_FREQ 320000000 + +// select MT9M114 Image configuration +// Defines camera sensor MT9M114 Image configuration +// <0=> 1288x728_RAW10 +// <1=> 1280x720_RAW8 +// <2=> 1280x720_RGB565 +// <3=> 640x480_RGB565 +// <4=> 320x240_RGB565 +// <5=> 320x320_RGB565 +// Default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 2 + +// select MT9M114 MIPI number of lanes in DPHY +// defines select MT9M114 MIPI number of lanes in DPHY. +// default: 1 one lane +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_N_LANES 1 + +// select MT9M114 MIPI virtual channel ID +// defines select MT9M114 MIPI virtual channel ID. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_VC_ID 0 + +// select MT9M114 MIPI override CPI color mode +// defines select MT9M114 MIPI override CPI color mode. +// default: 0 (Disable) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_OVERRIDE_CPI_COLOR_MODE 0 + +// select MT9M114 MIPI CPI color mode +// defines select MT9M114 MIPI CPI color mode. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CPI_COLOR_MODE 0 + +// Select camera sensor MT9M114 MIPI CSI clock source division [Divisor] <2-511> +// Defines camera sensor MT9M114 MIPI CSI clock source division +// Default: 20 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +// RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE +// Defines camera sensor MT9M114 MIPI i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE 1 + +#endif +// MT9M114_MIPI [Driver_MT9M114_MIPI] + +// HM0360_MIPI [Driver_HM0360_MIPI] +// Enable/Disable HM0360 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable HM0360 MIPI camera sensor +// default: enable +#define RTE_HM0360_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_HM0360_CAMERA_SENSOR_ENABLE) + +// Select camera HM0360 frequency +// Defines camera HM0360 frequency +// Default: 176000000 +#define RTE_HM0360_CAMERA_SENSOR_CSI_FREQ 176000000 + +// Select camera HM0360 frame per second +// <30=> 30 FPS +// <60=> 60 FPS +// Defines camera HM0360 frame per second +// Default: 60 FPS +#define RTE_HM0360_CAMERA_SENSOR_CSI_CFG_FPS 60 + +// Select camera HM0360 context select +// <0=> CONTEXT_A +// <1=> CONTEXT_B +// Defines camera HM0360 context select +// Default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL 0 + +// select HM0360 CSI2 Data type +// defines select CSI2 Data type +// default: 42(RAW8) +#define RTE_HM0360_CAMERA_SENSOR_CSI_DATA_TYPE 42 + +// select HM0360 number of lanes in DPHY +// defines select HM0360 number of lanes in DPHY. +// default: 1 one lane +#define RTE_HM0360_CAMERA_SENSOR_CSI_N_LANES 1 + +// select HM0360 virtual channel ID +// defines select HM0360 virtual channel ID. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_VC_ID 0 + +// select HM0360 override CPI color mode +// defines select HM0360 override CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select HM0360 CPI color mode +// defines select HM0360 CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +#if (RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL == 0) +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 480 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 640 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 240 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 240 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 320 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 320 +#endif + +// RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor HM0360 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// HM0360_MIPI [Driver_HM0360_MIPI] + +// OV5647_MIPI [Driver_OV5647_MIPI] +// Enable/Disable OV5647 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5647 MIPI camera sensor +// default: enable +#define RTE_OV5647_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5647_CAMERA_SENSOR_ENABLE) + +// Select camera OV5647 frequency +// Defines camera OV5647 frequency +// Default: 158000000 +#define RTE_OV5647_CAMERA_SENSOR_CSI_FREQ 158000000 + +// select OV5647 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5647_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5647 number of lanes in DPHY +// defines select OV5647 number of lanes in DPHY. +// default: 2 one lane +#define RTE_OV5647_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5647 virtual channel ID +// defines select OV5647 virtual channel ID. +// default: 0 +#define RTE_OV5647_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5647 override CPI color mode +// defines select OV5647 override CPI color mode. +// default: 1 +#define RTE_OV5647_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5647 CPI color mode +// defines select OV5647 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5647_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select OV5647 frame height +// defines select OV5647 frame height. +// default: 480 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select OV5647 frame width +// defines select OV5647 frame width. +// default: 640 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_WIDTH 640 + +// Select camera sensor OV5647 i2c instance +// Defines camera sensor OV5647 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5647_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// OV5647_MIPI [Driver_OV5647_MIPI] + +// OV5675_MIPI [Driver_OV5675_MIPI] +// Enable/Disable OV5675 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5675 MIPI camera sensor +// default: enable +#define RTE_OV5675_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5675_CAMERA_SENSOR_ENABLE) + +// Select camera OV5675 frequency +// Defines camera OV5675 frequency +// Default: 450000000 +#define RTE_OV5675_CAMERA_SENSOR_CSI_FREQ 450000000 + +// select OV5675 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5675_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5675 number of lanes in DPHY +// defines select OV5675 number of lanes in DPHY. +// default: 2 lane +#define RTE_OV5675_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5675 virtual channel ID +// defines select OV5675 virtual channel ID. +// default: 0 +#define RTE_OV5675_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5675 override CPI color mode +// defines select OV5675 override CPI color mode. +// default: 1 +#define RTE_OV5675_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5675 CPI color mode +// defines select OV5675 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. +// default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif + +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. +// default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif + +// Select camera sensor OV5675 i2c instance +// Defines camera sensor OV5675 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5675_CAMERA_SENSOR_I2C_INSTANCE 1 + +// Select camera sensor OV5675 CSI clock source division [Divisor] <2-511> +// Defines camera sensor OV5675 CSI clock source division +// Default: 20 +#define RTE_OV5675_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +#endif +// OV5675_MIPI [Driver_OV5675_MIPI] + +#endif +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] + +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] +// Configuration settings for Driver_MIPI_DSI in component ::Drivers:MIPI_DSI +#ifndef RTE_MIPI_DSI +#define RTE_MIPI_DSI 1 +#endif // RTE_MIPI_DSI + +#if RTE_MIPI_DSI + +// DPHY PLL input division factor +// Defines DPHY PLL input division factor +// Default: 3 +#define RTE_MIPI_DSI_PLL_INPUT_DIV_FACTOR_N 3 + +// DSI TX escape clock division value. +// Defines DSI TX escape clock division value. +// Default: 2 +#define RTE_MIPI_DSI_TX_ESC_CLK_DIVISION 2 + +// DPI Video Mode +// <0=> NON_BURST SYNC_PULSES +// <1=> NON_BURST SYNC_EVENTS +// <2=> BURST MODE +// Defines DPI Video Mode +// Default:BURST MODE +#define RTE_MIPI_DSI_VID_MODE_TYPE 2 + +// DSI Video number of Chunks +// Defines Number of chunks used to transfer single video packet . +// Default: 0 +#define RTE_MIPI_DSI_VID_NUM_CHUNKS 0 + +// DSI Size of NULL packet +// Defines Size of the NULL packet. +// Default: 0 +#define RTE_MIPI_DSI_VID_NULL_SIZE 0 + +// DSI IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_MIPI_DSI_IRQ_PRI 0 + +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] +// DSI ILI9806E LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9806E LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9806E_PANEL 1 + +#if RTE_MIPI_DSI_ILI9806E_PANEL + +// DSI ILI9806E panel variant +// <0=> E43RB_FW405 +// <1=> E43GB_MW405 +// <2=> E50RA_MW550 +// Defines ILI9806E panel variant +// Default: E43RB_FW405 +#define RTE_ILI9806E_PANEL_VARIANT 1 + +#if (RTE_ILI9806E_PANEL_VARIANT == 0) +#define RTE_ILI9806E_PANEL_E43RB_FW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 1) +#define RTE_ILI9806E_PANEL_E43GB_MW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 2) +#define RTE_ILI9806E_PANEL_E50RA_MW550_EN 1 +#endif + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9806E_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// <5=> 24bit +// Defines Color mode for display panel +// Default: 24bit +#define RTE_ILI9806E_PANEL_DSI_COLOR_MODE 1 + +// Number of data lanes +// <1=> ONE +// <2=> TWO +// Defines Number of data lanes +// Default: TWO +#define RTE_ILI9806E_PANEL_DSI_N_LANES 0x2 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9806E_PANEL_DSI_VC_ID 0 + +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] +#if (RTE_ILI9806E_PANEL_E43RB_FW405_EN || RTE_ILI9806E_PANEL_E43GB_MW405_EN) + +// Panel hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel FW405/MW405 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 5 +#define RTE_PANEL_HBP_TIME 5 + +// Panel FW405/MW405 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 5 +#define RTE_PANEL_HFP_TIME 5 + +// Panel FW405/MW405 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel FW405/MW405 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 2 +#define RTE_PANEL_VSYNC_LINE 2 + +// Panel FW405/MW405 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 10 +#define RTE_PANEL_VBP_LINE 10 + +// Panel FW405/MW405 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 10 +#define RTE_PANEL_VFP_LINE 10 + +// Panel FW405/MW405 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 800 +#define RTE_PANEL_VACTIVE_LINE 800 +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] +#elif RTE_ILI9806E_PANEL_E50RA_MW550_EN + +// Panel MW550 hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel MW550 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 30 +#define RTE_PANEL_HBP_TIME 30 + +// Panel MW550 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 18 +#define RTE_PANEL_HFP_TIME 18 + +// Panel MW550 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel MW550 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 4 +#define RTE_PANEL_VSYNC_LINE 4 + +// Panel MW550 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 30 +#define RTE_PANEL_VBP_LINE 30 + +// Panel MW550 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 20 +#define RTE_PANEL_VFP_LINE 20 + +// Panel MW550 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 854 +#define RTE_PANEL_VACTIVE_LINE 854 +#endif +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] +// DSI ILI9488 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9488 LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9488_PANEL 1 + +#if RTE_MIPI_DSI_ILI9488_PANEL + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9488_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// Defines Color mode for display panel +// Default: 16bit +#define RTE_ILI9488_PANEL_DSI_COLOR_MODE 1 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9488_PANEL_DSI_VC_ID 0 + +// Panel hsync time in pixels +// Defines ILI9488 LCD panel hsync time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HSYNC_TIME 10 + +// Panel ILI9488 hbp time in pixels +// Defines ILI9488 LCD panel hbp time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HBP_TIME 10 + +// Panel ILI9488 hfp time in pixels +// Defines ILI9488 LCD panel hfp time in pixels. +// Default: 40 +#define RTE_ILI9488_PANEL_HFP_TIME 40 + +// Panel ILI9488 hactive pixels +// Defines ILI9488 LCD panel hactive pixels. +// Default: 320 +#define RTE_ILI9488_PANEL_HACTIVE_TIME 320 + +// Panel ILI9488 vsync time in lines +// Defines ILI9488 LCD panel vsync time in lines. +// Default: 2 +#define RTE_ILI9488_PANEL_VSYNC_LINE 2 + +// Panel ILI9488 vbp time in lines +// Defines ILI9488 LCD panel vbp time in lines. +// Default: 16 +#define RTE_ILI9488_PANEL_VBP_LINE 16 + +// Panel ILI9488 vfp time in lines +// Defines ILI9488 LCD panel vfp time in lines. +// Default: 10 +#define RTE_ILI9488_PANEL_VFP_LINE 10 + +// Panel ILI9488 vactive lines +// Defines ILI9488 LCD panel vactive lines. +// Default: 480 +#define RTE_ILI9488_PANEL_VACTIVE_LINE 480 + +#endif +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] + +#endif +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] + +#endif +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] + +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] +// Configuration settings for Driver_Touch_Screen in component ::Drivers:touch screen +#define RTE_TOUCH_SCREEN 1 + +#if RTE_TOUCH_SCREEN + +// GT911 Touch screen +// <0=> DISABLE +// <1=> ENABLE +// Defines GT911 Touch screen +// Default: ENABLE +#define RTE_GT911 1 + +#if RTE_GT911 + +// select active touch points +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// defines select active touch points +// default: 5 +#define RTE_ACTIVE_TOUCH_POINTS 5 + +// RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL +// Defines GT911 Touchscreen i2c slave address selection +// <0x14=> I2C_SLAVE_ADDRESS_HEX_14 +// <0x5D=> I2C_SLAVE_ADDRESS_HEX_5D +// Default: 0x14 +#define RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL 0x14 +#endif + +#endif +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] + +// CDC200 (cdc200) [Driver_CDC200] +// Configuration settings for Driver_CDC200 in component ::Drivers:CDC200 +#define RTE_CDC200 1 + +#if RTE_CDC200 + +// CDC200 IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_CDC200_IRQ_PRI 0 + +// CDC200 clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CDC200 clock select +// Default: Select AXI clock source +#define RTE_CDC200_CLK_SEL 0 + +// CDC200 background color red <0-255> +// Defines CDC200 background color red. +// Default: 0 +#define RTE_CDC200_BGC_RED 0 + +// CDC200 background color green <0-255> +// Defines CDC200 background color green. +// Default: 0 +#define RTE_CDC200_BGC_GREEN 0 + +// CDC200 background color blue <0-255> +// Defines CDC200 background color blue. +// Default: 0 +#define RTE_CDC200_BGC_BLUE 0 + +// CDC200 pixel format +// <0=> ARGB8888 +// <1=> RGB888 +// <2=> RGB565 +//      <3=> RGBA8888 +//      <6=> ARGB1555 +//      <7=> ARGB4444 +// Defines CDC200 pixel format +// Default: RGB888 +#define RTE_CDC200_PIXEL_FORMAT 2 + +// CDC200 Constant alpha <0-255> +// Defines CDC200 constant alpha range from 0 (fully transparent) to 255 or 1.0 (fully opaque). +// Default: 255 +#define RTE_CDC200_CONSTANT_ALPHA 255 + +// CDC200 blending factor +// <0=> CONST_ALPHA +// <1=> PIXEL_ALPHA_X_CONST_ALPHA +// Defines CDC200 blending factor selection. +// Default: PIXEL_ALPHA_X_CONST_ALPHA +#define RTE_CDC200_BLEND_FACTOR 1 + +// CDC200 DPI interface FPS +// Defines CDC200 DPI interface Framrate per second. +// Default: 60 +#define RTE_CDC200_DPI_FPS 60 + +// Parallel ILI6122 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines Parallel ILI6122 LCD PANEL +// Default: ENABLE +#ifndef RTE_ILI6122_PANEL +#define RTE_ILI6122_PANEL 0 +#endif // RTE_ILI6122_PANEL + +#if RTE_ILI6122_PANEL + +// CDC HSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC HSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_HSYNC_ACTIVE_LOW 0 + +// CDC VSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC VSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_VSYNC_ACTIVE_LOW 0 + +// CDC Pixel Clock Output pin active state +// <0=> FEED THROUGH +// <1=> INVERTED +// Defines CDC Pixel Clock pin active state +// Default: FEED THROUGH +#define RTE_ILI6122_PANEL_CDC_PIXCLK_FEED_THROUGH 0 + +// CDC BLANKING pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC BLANKINg pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_BLANK_ACTIVE_LOW 0 + +// Panel hsync time in pixels +// Defines ILI6122 LCD panel hsync time in pixels. +// Default: 1 +#define RTE_PANEL_HSYNC_TIME 1 + +// Panel hbp time in pixels +// Defines ILI6122 LCD panel hbp time in pixels. +// Default: 46 +#define RTE_PANEL_HBP_TIME 46 + +// Panel hfp time in pixels +// Defines ILI6122 LCD panel hfp time in pixels. +// Default: 210 +#define RTE_PANEL_HFP_TIME 210 + +// Panel hactive pixels +// Defines ILI6122 LCD panel hactive pixels. +// Default: 800 +#define RTE_PANEL_HACTIVE_TIME 800 + +// Panel vsync time in lines +// Defines ILI6122 LCD panel vsync time in lines. +// Default: 1 +#define RTE_PANEL_VSYNC_LINE 1 + +// Panel vbp time in lines +// Defines ILI6122 LCD panel vbp time in lines. +// Default: 23 +#define RTE_PANEL_VBP_LINE 23 + +// Panel vfp time in lines +// Defines ILI6122 LCD panel vfp time in lines. +// Default: 22 +#define RTE_PANEL_VFP_LINE 22 + +// Panel vactive lines +// Defines ILI6122 LCD panel vactive lines. +// Default: 480 +#define RTE_PANEL_VACTIVE_LINE 480 +#endif + +#endif +// CDC200 (cdc200) [Driver_CDC200] + +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] +// Configuration settings for Driver_I3C in component ::Drivers:I3C +#define RTE_I3C 1 + +#if RTE_I3C + +// I3C IRQ priority <0-255> +// Defines I3C Interrupt priority +// Default: 0 +#define RTE_I3C_IRQ_PRI 0 + +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] +// Configuration settings for Driver_I2CI3C in component ::Drivers:I2CI3C +#define RTE_I2CI3C 1 +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] + +// I3C DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I3C +// Default: DISABLE +#define RTE_I3C_DMA_ENABLE 0 + +// I3C DMA Selection +// <0=> DMA2(M55-HE) +// <1=> DMA0 +// Defines Select DMA0 for I3C. By default DMA0 will be considered +// Default: DMA0 +#define RTE_I3C_SELECT_DMA0 1 + +// I3C DMA IRQ priority <0-255> +// Defines I3C DMA Interrupt priority +// Default: 0 +#define RTE_I3C_DMA_IRQ_PRI 0 + +// I3C blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I3C +// Default: DISABLE +#define RTE_I3C_BLOCKING_MODE_ENABLE 0 + +// I3C Slave I2C/I3C Adaptive mode Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines whether I3C Slave starts with I2C mode or not. +// It is for for enabling some features for I2C/I3C mode +// Default: DISABLE +#define RTE_I3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 + +#endif +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] + +// IMU (Initial Measurement Unit) [Driver_IMU] +// Configuration settings for Driver_IMU in component ::Drivers:IMU +#define RTE_IMU 1 + +#if RTE_IMU + +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] +// Configuration settings for Driver_ICM42670 in component ::Drivers:IMU +#define RTE_ICM42670 1 + +#if RTE_ICM42670 + +// ICM42670 IMU enable In-band_interrupt +// <0=> DISABLE +// <1=> ENABLE +// Defines whether In-band-interrupt to be enabled +// If disabled, then Normal-GPIO interrupt will be enabled +// Default: DISABLE +#define RTE_ICM42670_IBI_ENABLE 0 + +#endif +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +// Configuration settings for Driver_BMI323 in component ::Drivers:IMU +#define RTE_BMI323 1 + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +#endif +// IMU (Initial Measurement Unit) [Driver_IMU] + +// SPI (Serial Peripheral Interface) +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] +// Configuration settings for Driver_SPI0 in component ::Drivers:SPI +#define RTE_SPI0 1 + +#ifdef RTE_SPI0 + +// SPI0 IRQ priority <0-255> +// Defines Interrupt priority for SPI0. +// Default: 0 +#define RTE_SPI0_IRQ_PRIORITY 0 + +// SPI0 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI0. +// Default: 0 +#define RTE_SPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI0 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_THRESHOLD 0 + +// SPI0 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_RX_FIFO_THRESHOLD 0 + +// SPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI0. +// Default: 0 +#define RTE_SPI0_CHIP_SELECTION_PIN 0 + +// SPI0 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI0. +// Default: 0 +#define RTE_SPI0_RX_SAMPLE_DELAY 0 + +// SPI0 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI0. +// Default: 1 +#define RTE_SPI0_SSTE_ENABLE 1 + +// SPI0 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI0_USE_MASTER_SS_SW 0 + +#if RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 SW SS Port <0-15> +// Defines SPI0 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PORT 0 + +// SPI0 SW SS Pin <0-7> +// Defines SPI0 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PIN 0 + +// SPI0 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI0. +// Default: 0 +#define RTE_SPI0_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI0 MicroWire frame format. +// Default: 0 +#define RTE_SPI0_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI0 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI0_MW_TRANSFER_MODE 0 + +// SPI0 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI0 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI0_MW_HANDSAHKE_ENABLE 0 + +// SPI0 MW Control Frame Size +// Defines MW Control Frame Size for SPI0. +// Default: 0 +#define RTE_SPI0_MW_CFS 16 +#endif // RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI0 +// Default: DISABLE +#define RTE_SPI0_DMA_ENABLE 0 + +// SPI0 DMA IRQ priority <0-255> +// Defines SPI0 DMA Interrupt priority +// Default: 0 +#define RTE_SPI0_DMA_IRQ_PRI 0 + +// SPI0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI0 +// Default: DISABLE +#define RTE_SPI0_BLOCKING_MODE_ENABLE 0 +#endif +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 1 + +#ifdef RTE_SPI1 + +// SPI1 IRQ priority <0-255> +// Defines Interrupt priority for SPI1. +// Default: 0 +#define RTE_SPI1_IRQ_PRIORITY 0 + +// SPI1 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI1. +// Default: 0 +#define RTE_SPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI1 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_THRESHOLD 0 + +// SPI1 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_RX_FIFO_THRESHOLD 0 + +// SPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI1. +// Default: 0 +#define RTE_SPI1_CHIP_SELECTION_PIN 0 + +// SPI1 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI1. +// Default: 0 +#define RTE_SPI1_RX_SAMPLE_DELAY 0 + +// SPI1 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI1. +// Default: 1 +#define RTE_SPI1_SSTE_ENABLE 1 + +// SPI1 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI1_USE_MASTER_SS_SW 0 + +#if RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 SW SS Port <0-15> +// Defines SPI1 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PORT 0 + +// SPI1 SW SS pin number <0-7> +// Defines SPI1 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PIN 0 + +// SPI1 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI1. +// Default: 0 +#define RTE_SPI1_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI1 MicroWire frame format. +// Default: 0 +#define RTE_SPI1_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI1 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI1_MW_TRANSFER_MODE 0 + +// SPI1 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI1 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI1_MW_HANDSAHKE_ENABLE 0 + +// SPI1 MW Control Frame Size +// Defines MW Control Frame Size for SPI1. +// Default: 0 +#define RTE_SPI1_MW_CFS 16 +#endif // RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI1 +// Default: DISABLE +#define RTE_SPI1_DMA_ENABLE 0 + +// SPI1 DMA IRQ priority <0-255> +// Defines SPI1 DMA Interrupt priority +// Default: 0 +#define RTE_SPI1_DMA_IRQ_PRI 0 + +// SPI1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI1 +// Default: DISABLE +#define RTE_SPI1_BLOCKING_MODE_ENABLE 0 +#endif +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 1 + +#ifdef RTE_SPI2 + +// SPI2 IRQ priority <0-255> +// Defines Interrupt priority for SPI2. +// Default: 0 +#define RTE_SPI2_IRQ_PRIORITY 0 + +// SPI2 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI2 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI2. +// Default: 0 +#define RTE_SPI2_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI2 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_THRESHOLD 0 + +// SPI2 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_RX_FIFO_THRESHOLD 0 + +// SPI2 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI2. +// Default: 0 +#define RTE_SPI2_CHIP_SELECTION_PIN 0 + +// SPI2 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI2. +// Default: 0 +#define RTE_SPI2_RX_SAMPLE_DELAY 0 + +// SPI2 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI2. +// Default: 1 +#define RTE_SPI2_SSTE_ENABLE 1 + +// SPI2 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI2_USE_MASTER_SS_SW 0 + +#if RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 SW SS Port <0-15> +// Defines SPI2 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PORT 0 + +// SPI2 SW SS pin number <0-7> +// Defines SPI2 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PIN 0 + +// SPI2 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI2. +// Default: 0 +#define RTE_SPI2_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI2 MicroWire frame format. +// Default: 0 +#define RTE_SPI2_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI2 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI2_MW_TRANSFER_MODE 0 + +// SPI2 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI2 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI2_MW_HANDSAHKE_ENABLE 0 + +// SPI2 MW Control Frame Size +// Defines MW Control Frame Size for SPI2. +// Default: 0 +#define RTE_SPI2_MW_CFS 0 +#endif // RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI2 +// Default: DISABLE +#define RTE_SPI2_DMA_ENABLE 0 + +// SPI2 DMA IRQ priority <0-255> +// Defines SPI2 DMA Interrupt priority +// Default: 0 +#define RTE_SPI2_DMA_IRQ_PRI 0 + +// SPI2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI2 +// Default: DISABLE +#define RTE_SPI2_BLOCKING_MODE_ENABLE 0 +#endif +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 1 + +#ifdef RTE_SPI3 + +// SPI3 IRQ priority <0-255> +// Defines Interrupt priority for SPI3. +// Default: 0 +#define RTE_SPI3_IRQ_PRIORITY 0 + +// SPI3 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI3 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI3. +// Default: 0 +#define RTE_SPI3_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI3 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_THRESHOLD 0 + +// SPI3 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_RX_FIFO_THRESHOLD 0 + +// SPI3 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// Defines slave selection for SPI3. +// Default: 0 +#define RTE_SPI3_CHIP_SELECTION_PIN 1 + +// SPI3 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI3. +// Default: 0 +#define RTE_SPI3_RX_SAMPLE_DELAY 0 + +// SPI3 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI3. +// Default: 1 +#define RTE_SPI3_SSTE_ENABLE 1 + +// SPI3 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI3_USE_MASTER_SS_SW 0 + +#if RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 SW SS Port <0-15> +// Defines SPI3 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PORT 0 + +// SPI3 SW SS pin number <0-7> +// Defines SPI3 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PIN 0 + +// SPI3 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI3. +// Default: 0 +#define RTE_SPI3_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI3 MicroWire frame format. +// Default: 0 +#define RTE_SPI3_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI3 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI3_MW_TRANSFER_MODE 0 + +// SPI3 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI3 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI3_MW_HANDSAHKE_ENABLE 0 + +// SPI3 MW Control Frame Size +// Defines MW Control Frame Size for SPI3. +// Default: 0 +#define RTE_SPI3_MW_CFS 0 +#endif // RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI3 +// Default: DISABLE +#define RTE_SPI3_DMA_ENABLE 0 + +// SPI3 DMA IRQ priority <0-255> +// Defines SPI3 DMA Interrupt priority +// Default: 0 +#define RTE_SPI3_DMA_IRQ_PRI 0 + +// SPI3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI3 +// Default: DISABLE +#define RTE_SPI3_BLOCKING_MODE_ENABLE 0 +#endif +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// Configuration settings for Driver_LPSPI in component ::Drivers:SPI +#if defined(RTSS_HE) + +#define RTE_LPSPI 1 + +#ifdef RTE_LPSPI + +// LPSPI IRQ priority <0-255> +// Defines Interrupt priority for LPSPI. +// Default: 0 +#define RTE_LPSPI_IRQ_PRIORITY 0 + +// LPSPI TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// LPSPI load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// LPSPI TX FIFO threshold <0-15> +// Defines TX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_THRESHOLD 0 + +// LPSPI RX FIFO threshold <0-15> +// Defines RX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_RX_FIFO_THRESHOLD 0 + +// LPSPI slave selection +// <0=> SS_0 +// Defines slave selection for LPSPI. +// Default: 0 +#define RTE_LPSPI_CHIP_SELECTION_PIN 0 + +// LPSPI Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for LPSPI. +// Default: 1 +#define RTE_LPSPI_SSTE_ENABLE 1 + +// LPSPI Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_LPSPI_USE_MASTER_SS_SW 0 + +#if RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI SW SS Port <0-15> +// Defines LPSPI port of SS pin in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PORT 0 + +// LPSPI SW SS pin number <0-7> +// Defines LPSPI SS pin number in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PIN 0 + +// LPSPI SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for LPSPI. +// Default: 0 +#define RTE_LPSPI_SW_SPI_SS_POLARITY 0 +#endif // RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of LPSPI MicroWire frame format. +// Default: 0 +#define RTE_LPSPI_MICROWIRE_FRF_ENABLE 0 + +#if RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines LPSPI MicroWire transfer mode. +// Default: 0 +#define RTE_LPSPI_MW_TRANSFER_MODE 0 + +// LPSPI MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines LPSPI MicroWire handshake enable. +// Default: 0 +#define RTE_LPSPI_MW_HANDSAHKE_ENABLE 0 + +// LPSPI MW Control Frame Size +// Defines MW Control Frame Size for LPSPI. +// Default: 0 +#define RTE_LPSPI_MW_CFS 8 +#endif // RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPSPI +// Default: DISABLE +#define RTE_LPSPI_DMA_ENABLE 0 +#if RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPSPI. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPSPI_SELECT_DMA0 0 +#if RTE_LPSPI_SELECT_DMA0 + +// LPSPI DMA0 Group Selection +// <1=> DMA0_GROUP_1 +// <2=> DMA0_GROUP_2 +// Defines DMA0 Group for LPSPI. By default DMA0 Group 1 will be considered +// Default: DMA0_GROUP_1 +#define RTE_LPSPI_SELECT_DMA0_GROUP 1 +#endif // RTE_LPSPI_SELECT_DMA0 +#endif // RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA IRQ priority <0-255> +// Defines LPSPI DMA Interrupt priority +// Default: 0 +#define RTE_LPSPI_DMA_IRQ_PRI 0 + +// LPSPI blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPSPI +// Default: DISABLE +#define RTE_LPSPI_BLOCKING_MODE_ENABLE 0 +#endif // RTE_LPSPI +#endif // RTSS_HE + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// SPI (Serial Peripheral Interface) + +// OSPI (Octal Serial Peripheral Interface) +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI0 1 +#if RTE_OSPI0 +// OSPI0 IRQ priority <0-255> +// Defines OSPI0 Interrupt priority +// Default: 0 +#define RTE_OSPI0_IRQ_PRIORITY 0 + +// OSPI0 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <3=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI0_SPI_FRAME_FORMAT 3 + +// OSPI0 Bus speed +// Defines the OSPI0 Bus speed +// Default: 100000000 +#define RTE_OSPI0_BUS_SPEED 100000000 + +// OSPI0 Wait Cycles +// Defines the OSPI0 Wait Cycles for connected device +// Default: 6 +#define RTE_OSPI0_WAIT_CYCLES 6 + +// OSPI0 DFS +// Defines OSPI0 Data Frame Size +// Default: 16 +#define RTE_OSPI0_DFS 16 + +// OSPI0 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI0 +// Default: 0 +#define RTE_OSPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI0 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_FIFO_THRESHOLD 64 + +// OSPI0 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_FIFO_THRESHOLD 0 + +// OSPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_DMA_ENABLE 0 +#if RTE_OSPI0_DMA_ENABLE + +// OSPI0 TX DMA Data level +// Defines TX DMA Data level for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_DMA_DATA_LEVEL 64 + +// OSPI0 RX DMA Data level +// Defines RX DMA Data level for OSPI0 +// Default: 15 +#define RTE_OSPI0_RX_DMA_DATA_LEVEL 15 + +// OSPI0 DMA IRQ priority <0-255> +// Defines OSPI0 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI0_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI0 +// Default: 0 +#define RTE_OSPI0_CHIP_SELECTION_PIN 0 + +// OSPI0 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_SAMPLE_DELAY 0 + +// OSPI0 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI0 +// Default: 0 +#define RTE_OSPI0_DDR_DRIVE_EDGE 0 + +// OSPI0 RXDS Delay <0-16> +// Defines the delay applied to the RXDS signal of OSPI0 +// Default: 0 +#define RTE_OSPI0_RXDS_DELAY 11 + +// OSPI0 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI0 +// Default: 0 +#define RTE_OSPI0_SIGNAL_DELAY 22 +#endif +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] + +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI1 1 +#if RTE_OSPI1 +// OSPI1 IRQ priority <0-255> +// Defines OSPI1 Interrupt priority +// Default: 0 +#define RTE_OSPI1_IRQ_PRIORITY 0 + +// OSPI1 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <3=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI1_SPI_FRAME_FORMAT 3 + +// OSPI1 Bus speed +// Defines the OSPI1 Bus speed +// Default: 100000000 +#define RTE_OSPI1_BUS_SPEED 100000000 + +// OSPI1 Wait Cycles +// Defines the OSPI1 Wait Cycles for connected device +// Default: 16 +#define RTE_OSPI1_WAIT_CYCLES 3 + +// OSPI1 DFS +// Defines OSPI1 Data Frame Size +// Default: 32 +#define RTE_OSPI1_DFS 32 + +// OSPI1 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI1 +// Default: 0 +#define RTE_OSPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI1 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI1 +// Default: 64 +#define RTE_OSPI1_TX_FIFO_THRESHOLD 64 + +// OSPI1 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_FIFO_THRESHOLD 0 + +// OSPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_DMA_ENABLE 0 +#if RTE_OSPI1_DMA_ENABLE + +// OSPI1 TX DMA Data level +// Defines TX DMA Data level for OSPI1 +// Default: 130 +#define RTE_OSPI1_TX_DMA_DATA_LEVEL 130 + +// OSPI1 RX DMA Data level +// Defines RX DMA Data level for OSPI1 +// Default: 15 +#define RTE_OSPI1_RX_DMA_DATA_LEVEL 15 + +// OSPI1 DMA IRQ priority <0-255> +// Defines OSPI1 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI1_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI1. +// Default: 0 +#define RTE_OSPI1_CHIP_SELECTION_PIN 0 + +// OSPI1 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_SAMPLE_DELAY 0 + +// OSPI1 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI1 +// Default: 1 +#define RTE_OSPI1_DDR_DRIVE_EDGE 1 + +// OSPI1 RXDS Delay <0-16> +// Defines the delay applied to the RXDS signal of OSPI1 +// Default: 11 +#define RTE_OSPI1_RXDS_DELAY 11 + +// OSPI1 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI1 +// Default: 0 +#define RTE_OSPI1_SIGNAL_DELAY 0 +#endif +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// OSPI (Octal Serial Peripheral Interface) + +// +// FLASH (ISSI FLASH) [Driver_Flash] +// Configuration settings for Driver_Flash in component ::Drivers:Flash +#define RTE_ISSI_FLASH 1 +#if RTE_ISSI_FLASH + +// ISSI FLASH SIZE +// ISSI flash density in bytes +// Default: 0x2000000 +#define RTE_ISSI_FLASH_SIZE 0x2000000 + +// ISSI FLASH OSPI Instance +// Defines the OSPI controller instance the ISSI flash is connected to +// Default: 1 +#define RTE_ISSI_FLASH_OSPI_DRV_NUM 1 + +// ISSI FLASH OSPI Bus speed +// Defines the OSPI Bus speed +// Default: 100000000 +#define RTE_ISSI_FLASH_OSPI_BUS_SPEED 100000000 + +// ISSI FLASH Wait cycles +// Defines the number of wait (dummy) cycles needed for fast read operations +// Default: 16 +#define RTE_ISSI_FLASH_WAIT_CYCLES 16 + +#endif +// FLASH (ISSI FLASH) [Driver_Flash] + +// I2S (Integrated Interchip Sound) +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] +// Configuration settings for Driver_SAI0 in component ::Drivers:SAI +#define RTE_I2S0 1 + +#if RTE_I2S0 + +// I2S0 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S0 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S0_WSS_CLOCK_CYCLES 2 + +// I2S0 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S0 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S0_SCLKG_CLOCK_CYCLES 0 + +// I2S0 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S0_RX_TRIG_LVL 7 + +// I2S0 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S0_TX_TRIG_LVL 8 + +// I2S0 IRQ priority <0-255> +// Defines I2S0 Interrupt priority +// Default: 0 +#define RTE_I2S0_IRQ_PRI 0 + +// I2S0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S0 +// Default: ENABLE +#define RTE_I2S0_DMA_ENABLE 0 + +// I2S0 DMA IRQ priority <0-255> +// Defines I2S0 DMA Interrupt priority +// Default: 0 +#define RTE_I2S0_DMA_IRQ_PRI 0 + +// I2S0 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S0 +// Default: DISABLE +#define RTE_I2S0_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] + +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] +// Configuration settings for Driver_SAI1 in component ::Drivers:SAI +#define RTE_I2S1 1 + +#if RTE_I2S1 + +// I2S1 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S1 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S1_WSS_CLOCK_CYCLES 2 + +// I2S1 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S1 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S1_SCLKG_CLOCK_CYCLES 0 + +// I2S1 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S1_RX_TRIG_LVL 7 + +// I2S1 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S1_TX_TRIG_LVL 8 + +// I2S1 IRQ priority <0-255> +// Defines I2S1 Interrupt priority +// Default: 1 +#define RTE_I2S1_IRQ_PRI 1 + +// I2S1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S1 +// Default: ENABLE +#define RTE_I2S1_DMA_ENABLE 0 + +// I2S1 DMA IRQ priority <0-255> +// Defines I2S1 DMA Interrupt priority +// Default: 0 +#define RTE_I2S1_DMA_IRQ_PRI 0 + +// I2S1 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S1 +// Default: DISABLE +#define RTE_I2S1_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] + +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] +// Configuration settings for Driver_SAI2 in component ::Drivers:SAI +#define RTE_I2S2 1 + +#if RTE_I2S2 + +// I2S2 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S2 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S2_WSS_CLOCK_CYCLES 2 + +// I2S2 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S2 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S2_SCLKG_CLOCK_CYCLES 0 + +// I2S2 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S2_RX_TRIG_LVL 7 + +// I2S2 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S2_TX_TRIG_LVL 8 + +// I2S2 IRQ priority <0-255> +// Defines I2S2 Interrupt priority +// Default: 0 +#define RTE_I2S2_IRQ_PRI 10 + +// I2S2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S2 +// Default: ENABLE +#define RTE_I2S2_DMA_ENABLE 0 + +// I2S2 DMA IRQ priority <0-255> +// Defines I2S2 DMA Interrupt priority +// Default: 0 +#define RTE_I2S2_DMA_IRQ_PRI 0 + +// I2S2 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S2 +// Default: DISABLE +#define RTE_I2S2_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] + +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] +// Configuration settings for Driver_SAI3 in component ::Drivers:SAI +#define RTE_I2S3 1 + +#if RTE_I2S3 + +// I2S3 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S3 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S3_WSS_CLOCK_CYCLES 2 + +// I2S3 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S3 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S3_SCLKG_CLOCK_CYCLES 0 + +// I2S3 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S3_RX_TRIG_LVL 7 + +// I2S3 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S3_TX_TRIG_LVL 8 + +// I2S3 IRQ priority <0-255> +// Defines I2S3 Interrupt priority +// Default: 0 +#define RTE_I2S3_IRQ_PRI 0 + +// I2S3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S3 +// Default: ENABLE +#define RTE_I2S3_DMA_ENABLE 0 + +// I2S3 DMA IRQ priority <0-255> +// Defines I2S3 DMA Interrupt priority +// Default: 0 +#define RTE_I2S3_DMA_IRQ_PRI 0 + +// I2S3 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S3 +// Default: DISABLE +#define RTE_I2S3_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// Configuration settings for Driver_SAILP in component ::Drivers:SAI +#if defined(RTSS_HE) + +#define RTE_LPI2S 1 + +#if RTE_LPI2S + +// LPI2S WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines LPI2S size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_LPI2S_WSS_CLOCK_CYCLES 2 + +// LPI2S SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines LPI2S SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_LPI2S_SCLKG_CLOCK_CYCLES 0 + +// LPI2S RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_LPI2S_RX_TRIG_LVL 7 + +// LPI2S TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_LPI2S_TX_TRIG_LVL 8 + +// LPI2S IRQ priority <0-255> +// Defines LPI2S Interrupt priority +// Default: 1 +#define RTE_LPI2S_IRQ_PRI 1 + +// LPI2S DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI2S +// Default: ENABLE +#define RTE_LPI2S_DMA_ENABLE 0 +#if RTE_LPI2S_DMA_ENABLE + +// LPI2S DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPI2S. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPI2S_SELECT_DMA0 0 +#endif + +// LPI2S DMA IRQ priority <0-255> +// Defines LPI2S DMA Interrupt priority +// Default: 0 +#define RTE_LPI2S_DMA_IRQ_PRI 0 + +// LPI2S Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPI2S +// Default: DISABLE +#define RTE_LPI2S_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPI2S +#endif // defined(RTSS_HE) + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// I2S (Integrated Interchip Sound) + +// WM8904 Codec [Driver_WM8904] +// Configuration settings for Driver_WM8904 in component ::Drivers:WM8904 +#define RTE_WM8904_CODEC 1 + +#if RTE_WM8904_CODEC + +// Select WM8904 i2c instance +// Defines WM8904 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 0 +#define RTE_WM8904_CODEC_I2C_INSTANCE 0 +#endif + +// WM8904 Codec [Driver_WM8904] + +// UART (Universal asynchronous receiver transmitter) +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_UART0 1 + +#if RTE_UART0 + +// UART0 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART0 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART0_RX_TRIG_LVL 0 + +// UART0 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART0 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART0_TX_TRIG_LVL 0 + +// UART0 IRQ priority <0-255> +// Defines Interrupt priority for UART0. +// Default: 0 +#define RTE_UART0_IRQ_PRI 0 + +// UART0 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART0 clock source. +// Default: CLK_100MHz +#define RTE_UART0_CLK_SOURCE 1 + +// UART0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART0 +// Default: DISABLE +#define RTE_UART0_DMA_ENABLE 0 + +// UART0 DMA IRQ priority <0-255> +// Defines UART0 DMA Interrupt priority +// Default: 0 +#define RTE_UART0_DMA_IRQ_PRI 0 + +// UART0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART0 +// Default: DISABLE +#define RTE_UART0_BLOCKING_MODE_ENABLE 0 + +#endif // UART0 + +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_UART1 1 + +#if RTE_UART1 + +// UART1 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART1 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART1_RX_TRIG_LVL 0 + +// UART1 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART1 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART1_TX_TRIG_LVL 0 + +// UART1 IRQ priority <0-255> +// Defines Interrupt priority for UART1. +// Default: 0 +#define RTE_UART1_IRQ_PRI 0 + +// UART1 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART1 clock source. +// Default: CLK_100MHz +#define RTE_UART1_CLK_SOURCE 1 + +// UART1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART1 +// Default: DISABLE +#define RTE_UART1_DMA_ENABLE 0 + +// UART1 DMA IRQ priority <0-255> +// Defines UART1 DMA Interrupt priority +// Default: 0 +#define RTE_UART1_DMA_IRQ_PRI 0 + +// UART1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART1 +// Default: DISABLE +#define RTE_UART1_BLOCKING_MODE_ENABLE 0 + +#endif // UART1 + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::Drivers:USART +#define RTE_UART2 1 + +#if RTE_UART2 + +// UART2 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART2 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART2_RX_TRIG_LVL 0 + +// UART2 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART2 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART2_TX_TRIG_LVL 0 + +// UART2 IRQ priority <0-255> +// Defines Interrupt priority for UART2. +// Default: 0 +#define RTE_UART2_IRQ_PRI 0 + +// UART2 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART2 clock source. +// Default: CLK_100MHz +#define RTE_UART2_CLK_SOURCE 1 + +// UART2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART2 +// Default: DISABLE +#define RTE_UART2_DMA_ENABLE 0 + +// UART2 DMA IRQ priority <0-255> +// Defines UART2 DMA Interrupt priority +// Default: 0 +#define RTE_UART2_DMA_IRQ_PRI 0 + +// UART2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART2 +// Default: DISABLE +#define RTE_UART2_BLOCKING_MODE_ENABLE 0 + +#endif // UART2 + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::Drivers:USART +#define RTE_UART3 1 + +#if RTE_UART3 + +// UART3 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART3 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART3_RX_TRIG_LVL 0 + +// UART3 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART3 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART3_TX_TRIG_LVL 0 + +// UART3 IRQ priority <0-255> +// Defines Interrupt priority for UART3. +// Default: 0 +#define RTE_UART3_IRQ_PRI 0 + +// UART3 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART3 clock source. +// Default: CLK_100MHz +#define RTE_UART3_CLK_SOURCE 1 + +// UART3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART3 +// Default: DISABLE +#define RTE_UART3_DMA_ENABLE 0 + +// UART3 DMA IRQ priority <0-255> +// Defines UART3 DMA Interrupt priority +// Default: 0 +#define RTE_UART3_DMA_IRQ_PRI 0 + +// UART3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART3 +// Default: DISABLE +#define RTE_UART3_BLOCKING_MODE_ENABLE 0 + +#endif // UART3 + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::Drivers:USART +#define RTE_UART4 1 + +#if RTE_UART4 + +// UART4 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART4 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART4_RX_TRIG_LVL 0 + +// UART4 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART4 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART4_TX_TRIG_LVL 0 + +// UART4 IRQ priority <0-255> +// Defines Interrupt priority for UART4. +// Default: 0 +#define RTE_UART4_IRQ_PRI 0 + +// UART4 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART4 clock source. +// Default: CLK_100MHz +#define RTE_UART4_CLK_SOURCE 1 + +#define RTE_UART4_RS485_ENABLE 0 +#if RTE_UART4_RS485_ENABLE +#define RTE_UART4_RS485_TRANSFER_MODE 2 +#define RTE_UART4_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART4_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART4 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART4 +// Default: DISABLE +#define RTE_UART4_DMA_ENABLE 0 + +// UART4 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART4. By default DMA0 will be considered. +// Default: DMA0 +#define RTE_UART4_SELECT_DMA0 1 + +// UART4 DMA IRQ priority <0-255> +// Defines UART4 DMA Interrupt priority +// Default: 0 +#define RTE_UART4_DMA_IRQ_PRI 0 + +// UART4 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART4 +// Default: DISABLE +#define RTE_UART4_BLOCKING_MODE_ENABLE 0 + +#endif // UART4 + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::Drivers:USART +#define RTE_UART5 1 + +#if RTE_UART5 + +// UART5 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART5 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART5_RX_TRIG_LVL 0 + +// UART5 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART5 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART5_TX_TRIG_LVL 0 + +// UART5 IRQ priority <0-255> +// Defines Interrupt priority for UART5. +// Default: 0 +#define RTE_UART5_IRQ_PRI 0 + +// UART5 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART5 clock source. +// Default: CLK_100MHz +#define RTE_UART5_CLK_SOURCE 1 + +#define RTE_UART5_RS485_ENABLE 0 +#if RTE_UART5_RS485_ENABLE +#define RTE_UART5_RS485_TRANSFER_MODE 2 +#define RTE_UART5_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART5_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART5 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART5 +// Default: DISABLE +#define RTE_UART5_DMA_ENABLE 0 + +// UART5 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART5. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART5_SELECT_DMA0 1 + +// UART5 DMA IRQ priority <0-255> +// Defines UART5 DMA Interrupt priority +// Default: 0 +#define RTE_UART5_DMA_IRQ_PRI 0 + +// UART5 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART5 +// Default: DISABLE +#define RTE_UART5_BLOCKING_MODE_ENABLE 0 + +#endif // UART5 + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::Drivers:USART +#define RTE_UART6 1 + +#if RTE_UART6 + +// UART6 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART6 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART6_RX_TRIG_LVL 0 + +// UART6 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART6 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART6_TX_TRIG_LVL 0 + +// UART6 IRQ priority <0-255> +// Defines Interrupt priority for UART6. +// Default: 0 +#define RTE_UART6_IRQ_PRI 0 + +// UART6 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART6 clock source. +// Default: CLK_100MHz +#define RTE_UART6_CLK_SOURCE 1 + +#define RTE_UART6_RS485_ENABLE 0 +#if RTE_UART6_RS485_ENABLE +#define RTE_UART6_RS485_TRANSFER_MODE 2 +#define RTE_UART6_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART6_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART6 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART6 +// Default: DISABLE +#define RTE_UART6_DMA_ENABLE 0 + +// UART6 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART6. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART6_SELECT_DMA0 1 + +// UART6 DMA IRQ priority <0-255> +// Defines UART6 DMA Interrupt priority +// Default: 0 +#define RTE_UART6_DMA_IRQ_PRI 0 + +// UART6 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART6 +// Default: DISABLE +#define RTE_UART6_BLOCKING_MODE_ENABLE 0 + +#endif // UART6 + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::Drivers:USART +#define RTE_UART7 1 + +#if RTE_UART7 + +// UART7 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART7 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART7_RX_TRIG_LVL 0 + +// UART7 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART7 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART7_TX_TRIG_LVL 0 + +// UART7 IRQ priority <0-255> +// Defines Interrupt priority for UART7. +// Default: 0 +#define RTE_UART7_IRQ_PRI 0 + +// UART7 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART7 clock source. +// Default: CLK_100MHz +#define RTE_UART7_CLK_SOURCE 1 + +#define RTE_UART7_RS485_ENABLE 0 +#if RTE_UART7_RS485_ENABLE +#define RTE_UART7_RS485_TRANSFER_MODE 2 +#define RTE_UART7_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART7_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART7 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART7 +// Default: DISABLE +#define RTE_UART7_DMA_ENABLE 0 + +// UART7 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART7. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART7_SELECT_DMA0 1 + +// UART7 DMA IRQ priority <0-255> +// Defines UART7 DMA Interrupt priority +// Default: 0 +#define RTE_UART7_DMA_IRQ_PRI 0 + +// UART7 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART7 +// Default: DISABLE +#define RTE_UART7_BLOCKING_MODE_ENABLE 0 + +#endif // UART7 + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// Configuration settings for Driver_USARTLP in component ::Drivers:USART +#if defined(RTSS_HE) +#define RTE_LPUART 1 +#endif + +#if RTE_LPUART + +// LPUART RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines LPUART receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_LPUART_RX_TRIG_LVL 0 + +// LPUART TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines LPUART transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_LPUART_TX_TRIG_LVL 0 + +// LPUART IRQ priority <0-255> +// Defines Interrupt priority for LPUART. +// Default: 0 +#define RTE_LPUART_IRQ_PRI 0 + +// LPUART DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPUART +// Default: DISABLE +#define RTE_LPUART_DMA_ENABLE 0 + +// LPUART DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPUART. By default DMA0 will be considered +// Default: DMA0 +#define RTE_LPUART_SELECT_DMA0 1 + +// LPUART DMA IRQ priority <0-255> +// Defines LPUART DMA Interrupt priority +// Default: 0 +#define RTE_LPUART_DMA_IRQ_PRI 0 + +// LPUART blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPUART +// Default: DISABLE +#define RTE_LPUART_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPUART + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// UART (Universal asynchronous receiver transmitter) + +// LPTIMER (Low power timer) +// LPTIMER (Low power timer) [Driver_LPTIMER] +// Configuration settings for Driver_LPTIMER in component ::Drivers:LPTIMER +#define RTE_LPTIMER 1 + +#if RTE_LPTIMER + +// LPTIMER CHANNEL 0 +// Configuration settings for Driver_LPTIMER channel 0 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL0 1 + +// CHANNEL0 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 0. +// Default: 0 +#define RTE_LPTIMER_CHANNEL0_IRQ_PRIORITY (0) + +// CHANNEL0 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel0. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL0_FREE_RUN_MODE (0) + +// CHANNEL0 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel0. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL0_CLK_SRC (0) +// LPTIMER CHANNEL 0 + +// LPTIMER CHANNEL 1 +// Configuration settings for Driver_LPTIMER channel 1 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL1 1 + +// CHANNEL1 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 1. +// Default: 0 +#define RTE_LPTIMER_CHANNEL1_IRQ_PRIORITY (0) + +// CHANNEL1 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel1. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL1_FREE_RUN_MODE (0) + +// CHANNEL1 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel1. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL1_CLK_SRC (0) +// LPTIMER CHANNEL 1 + +// LPTIMER CHANNEL 2 +// Configuration settings for Driver_LPTIMER channel 2 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL2 1 + +// CHANNEL2 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 2. +// Default: 0 +#define RTE_LPTIMER_CHANNEL2_IRQ_PRIORITY (0) + +// CHANNEL2 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel2. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL2_FREE_RUN_MODE (0) + +// CHANNEL2 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel2. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL2_CLK_SRC (0) +// LPTIMER CHANNEL 2 + +// LPTIMER CHANNEL 3 +// Configuration settings for Driver_LPTIMER channel 3 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL3 1 + +// CHANNEL3 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 3. +// Default: 0 +#define RTE_LPTIMER_CHANNEL3_IRQ_PRIORITY (0) + +// CHANNEL3 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel3. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL3_FREE_RUN_MODE (0) + +// CHANNEL3 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel3. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL3_CLK_SRC (0) +// LPTIMER CHANNEL 3 +#endif /* RTE_LPTIMER */ +// LPTIMER (Low power timer) [Driver_LPTIMER] +// LPTIMER (Low power timer) + +// RTC (Real time clock) +// RTC0 (Real time clock) [Driver_RTC0] +// Configuration settings for Driver_RTC0 in component ::Drivers:RTC +#define RTE_RTC0 1 + +#if RTE_RTC0 + +// RTC0 IRQ priority <0-255> +// Defines Interrupt priority for RTC0. +// Default: 0 +#define RTE_RTC0_IRQ_PRI 0 +#endif +// RTC0 (Real time clock) [Driver_RTC0] +// RTC (Real time clock) + +// WDT (Watchdog Timer) +// WDT0 (Watchdog Timer) [Driver_WDT0] +// Configuration settings for Driver_WDT0 in component ::Drivers:WDT +#define RTE_WDT0 1 +// WDT0 (Watchdog Timer) [Driver_WDT0] +// WDT (Watchdog Timer) + +// UTIMER (Universal Timer) +// UTIMER (Universal Timer) [Driver_UTIMER] +// Configuration settings for Driver_UTIMER in component ::Drivers:UTIMER +#define RTE_UTIMER 1 + +#if RTE_UTIMER + +// UTIMER CHANNEL 0 +// Configuration settings for UTIMER channel 0 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL0 1 + +// CHANNEL0 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_FIXED_BUFFER 0 + +// CHANNEL0 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DMA_CLEAR_ENABLE 0 + +// CHANNEL0 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 0. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL0_FAULT_TYPE 0 + +// CHANNEL0 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 0. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 + +// CHANNEL0 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_A 1 + +// CHANNEL0 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_B 0 + +// CHANNEL0 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_START_STATE 0 + +// CHANNEL0 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_STOP_STATE 0 + +// CHANNEL0 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL0 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_START_STATE 0 + +// CHANNEL0 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_STOP_STATE 0 + +// CHANNEL0 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL0 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_CREST 1 + +// CHANNEL0 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_TROUGH 0 + +// CHANNEL0 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 0. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE 0 + +// CHANNEL0 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 0. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL0_BUFFER_OPERATION 0 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_A 2 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_B 0 + +// CHANNEL0 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL0 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 + +// CHANNEL0 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 0 + +// UTIMER CHANNEL 1 +// Configuration settings for UTIMER channel 1 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL1 1 + +// CHANNEL1 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_FIXED_BUFFER 0 + +// CHANNEL1 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DMA_CLEAR_ENABLE 0 + +// CHANNEL1 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 1. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL1_FAULT_TYPE 0 + +// CHANNEL1 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 + +// CHANNEL1 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_A 0 + +// CHANNEL1 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_B 0 + +// CHANNEL1 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_START_STATE 0 + +// CHANNEL1 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_STOP_STATE 0 + +// CHANNEL1 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL1 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_START_STATE 0 + +// CHANNEL1 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_STOP_STATE 0 + +// CHANNEL1 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL1 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_CREST 1 + +// CHANNEL1 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_TROUGH 0 + +// CHANNEL1 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 1. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE 1 + +// CHANNEL1 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 1. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL1_BUFFER_OPERATION 1 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_A 0 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_B 0 + +// CHANNEL1 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL1 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 + +// CHANNEL1 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 1 + +// UTIMER CHANNEL 2 +// Configuration settings for UTIMER channel 2 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL2 1 + +// CHANNEL2 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_FIXED_BUFFER 0 + +// CHANNEL2 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DMA_CLEAR_ENABLE 0 + +// CHANNEL2 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 2. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL2_FAULT_TYPE 0 + +// CHANNEL2 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 2. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 + +// CHANNEL2 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_A 0 + +// CHANNEL2 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_B 0 + +// CHANNEL2 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_START_STATE 0 + +// CHANNEL2 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_STOP_STATE 0 + +// CHANNEL2 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL2 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_START_STATE 0 + +// CHANNEL2 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_STOP_STATE 0 + +// CHANNEL2 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL2 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_CREST 1 + +// CHANNEL2 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_TROUGH 0 + +// CHANNEL2 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 2. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE 1 + +// CHANNEL2 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 2. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL2_BUFFER_OPERATION 1 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_A 2 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_B 0 + +// CHANNEL2 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel2 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL2 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 + +// CHANNEL2 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 2 + +// UTIMER CHANNEL 3 +// Configuration settings for UTIMER channel 3 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL3 1 + +// CHANNEL3 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_FIXED_BUFFER 0 + +// CHANNEL3 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DMA_CLEAR_ENABLE 0 + +// CHANNEL3 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 3. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL3_FAULT_TYPE 0 + +// CHANNEL3 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 3. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL3_BUF_TROUGH_N_CREST 0 + +// CHANNEL3 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_A 0 + +// CHANNEL3 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_B 0 + +// CHANNEL3 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_START_STATE 0 + +// CHANNEL3 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_STOP_STATE 0 + +// CHANNEL3 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL3 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_START_STATE 0 + +// CHANNEL3 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_STOP_STATE 0 + +// CHANNEL3 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL3 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_CREST 1 + +// CHANNEL3 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_TROUGH 0 + +// CHANNEL3 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 3. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE 0 + +// CHANNEL3 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 3. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL3_BUFFER_OPERATION 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_A 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_B 0 + +// CHANNEL3 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL3 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_ENABLE 0 + +// CHANNEL3 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 3 + +// UTIMER CHANNEL 4 +// Configuration settings for UTIMER channel 4 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL4 1 + +// CHANNEL4 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_FIXED_BUFFER 0 + +// CHANNEL4 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DMA_CLEAR_ENABLE 0 + +// CHANNEL4 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 4. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL4_FAULT_TYPE 0 + +// CHANNEL4 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL4_BUF_TROUGH_N_CREST 0 + +// CHANNEL4 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_A 1 + +// CHANNEL4 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_B 0 + +// CHANNEL4 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_START_STATE 0 + +// CHANNEL4 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_STOP_STATE 0 + +// CHANNEL4 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL4 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_START_STATE 0 + +// CHANNEL4 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_STOP_STATE 0 + +// CHANNEL4 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL4 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_CREST 1 + +// CHANNEL4 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_TROUGH 1 + +// CHANNEL4 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 4. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE 1 + +// CHANNEL4 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 4. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL4_BUFFER_OPERATION 1 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_A 2 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_B 2 + +// CHANNEL4 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL4 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_ENABLE 0 + +// CHANNEL4 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 4 + +// UTIMER CHANNEL 5 +// Configuration settings for UTIMER channel 5 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL5 1 + +// CHANNEL5 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_FIXED_BUFFER 0 + +// CHANNEL5 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DMA_CLEAR_ENABLE 0 + +// CHANNEL5 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 5. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL5_FAULT_TYPE 0 + +// CHANNEL5 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 5. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL5_BUF_TROUGH_N_CREST 0 + +// CHANNEL5 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_A 1 + +// CHANNEL5 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_B 0 + +// CHANNEL5 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_START_STATE 0 + +// CHANNEL5 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_STOP_STATE 0 + +// CHANNEL5 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL5 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL5 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_START_STATE 0 + +// CHANNEL5 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_STOP_STATE 0 + +// CHANNEL5 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL5 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL5 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_CREST 1 + +// CHANNEL5 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_TROUGH 0 + +// CHANNEL5 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 5. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE 1 + +// CHANNEL5 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 5. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL5_BUFFER_OPERATION 1 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_A 2 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_B 0 + +// CHANNEL5 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL5 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_ENABLE 0 + +// CHANNEL5 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 5 + +// UTIMER CHANNEL 6 +// Configuration settings for UTIMER channel 6 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL6 1 + +// CHANNEL6 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_FIXED_BUFFER 0 + +// CHANNEL6 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DMA_CLEAR_ENABLE 0 + +// CHANNEL6 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 6. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL6_FAULT_TYPE 0 + +// CHANNEL6 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 6. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL6_BUF_TROUGH_N_CREST 0 + +// CHANNEL6 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_A 1 + +// CHANNEL6 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_B 0 + +// CHANNEL6 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_START_STATE 0 + +// CHANNEL6 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_STOP_STATE 0 + +// CHANNEL6 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL6 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL6 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_START_STATE 0 + +// CHANNEL6 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_STOP_STATE 0 + +// CHANNEL6 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL6 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL6 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_CREST 1 + +// CHANNEL6 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_TROUGH 0 + +// CHANNEL6 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 6. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE 0 + +// CHANNEL6 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 6. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL6_BUFFER_OPERATION 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_A 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_B 0 + +// CHANNEL6 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL6 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_ENABLE 0 + +// CHANNEL6 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 6 + +// UTIMER CHANNEL 7 +// Configuration settings for UTIMER channel 7 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL7 1 + +// CHANNEL7 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_FIXED_BUFFER 0 + +// CHANNEL7 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DMA_CLEAR_ENABLE 0 + +// CHANNEL7 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 7. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL7_FAULT_TYPE 0 + +// CHANNEL7 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 7. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL7_BUF_TROUGH_N_CREST 0 + +// CHANNEL7 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_A 0 + +// CHANNEL7 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_B 0 + +// CHANNEL7 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_START_STATE 0 + +// CHANNEL7 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_STOP_STATE 0 + +// CHANNEL7 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL7 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_START_STATE 0 + +// CHANNEL7 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_STOP_STATE 0 + +// CHANNEL7 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL7 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_CREST 1 + +// CHANNEL7 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_TROUGH 0 + +// CHANNEL7 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 7. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE 1 + +// CHANNEL7 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 7. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL7_BUFFER_OPERATION 1 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_A 2 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_B 0 + +// CHANNEL7 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL7 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_ENABLE 0 + +// CHANNEL7 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 7 + +// UTIMER CHANNEL 8 +// Configuration settings for UTIMER channel 8 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL8 1 + +// CHANNEL8 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_FIXED_BUFFER 0 + +// CHANNEL8 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DMA_CLEAR_ENABLE 0 + +// CHANNEL8 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 8. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL8_FAULT_TYPE 0 + +// CHANNEL8 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 8. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL8_BUF_TROUGH_N_CREST 0 + +// CHANNEL8 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_A 1 + +// CHANNEL8 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_B 0 + +// CHANNEL8 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_START_STATE 0 + +// CHANNEL8 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_STOP_STATE 0 + +// CHANNEL8 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL8 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL8 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_START_STATE 0 + +// CHANNEL8 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_STOP_STATE 0 + +// CHANNEL8 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL8 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL8 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_CREST 1 + +// CHANNEL8 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_TROUGH 0 + +// CHANNEL8 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 8. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE 0 + +// CHANNEL8 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 8. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL8_BUFFER_OPERATION 0 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_A 2 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_B 0 + +// CHANNEL8 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL8 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_ENABLE 0 + +// CHANNEL8 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 8 + +// UTIMER CHANNEL 9 +// Configuration settings for UTIMER channel 9 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL9 1 + +// CHANNEL9 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_FIXED_BUFFER 0 + +// CHANNEL9 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DMA_CLEAR_ENABLE 0 + +// CHANNEL9 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 9. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL9_FAULT_TYPE 0 + +// CHANNEL9 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 9. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL9_BUF_TROUGH_N_CREST 0 + +// CHANNEL9 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_A 0 + +// CHANNEL9 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_B 1 + +// CHANNEL9 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_START_STATE 0 + +// CHANNEL9 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_STOP_STATE 0 + +// CHANNEL9 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL9 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL9 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_START_STATE 0 + +// CHANNEL9 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_STOP_STATE 0 + +// CHANNEL9 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_MATCH_COUNT 1 + +// CHANNEL9 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_CYCLE_END 2 + +// CHANNEL9 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_CREST 1 + +// CHANNEL9 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_TROUGH 0 + +// CHANNEL9 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 9. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE 0 + +// CHANNEL9 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 9. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL9_BUFFER_OPERATION 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_A 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_B 0 + +// CHANNEL9 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL9 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_ENABLE 0 + +// CHANNEL9 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 9 + +// UTIMER CHANNEL 10 +// Configuration settings for UTIMER channel 10 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL10 1 + +// CHANNEL10 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_FIXED_BUFFER 0 + +// CHANNEL10 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DMA_CLEAR_ENABLE 0 + +// CHANNEL10 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 10. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL10_FAULT_TYPE 0 + +// CHANNEL10 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 10. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL10_BUF_TROUGH_N_CREST 0 + +// CHANNEL10 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_A 1 + +// CHANNEL10 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_B 0 + +// CHANNEL10 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_START_STATE 0 + +// CHANNEL10 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_STOP_STATE 0 + +// CHANNEL10 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL10 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL10 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_START_STATE 0 + +// CHANNEL10 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_STOP_STATE 0 + +// CHANNEL10 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL10 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL10 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_CREST 1 + +// CHANNEL10 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_TROUGH 0 + +// CHANNEL10 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 10. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE 0 + +// CHANNEL10 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 10. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL10_BUFFER_OPERATION 0 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_A 2 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_B 0 + +// CHANNEL10 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL10 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_ENABLE 0 + +// CHANNEL10 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 10 + +// UTIMER CHANNEL 11 +// Configuration settings for UTIMER channel 11 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL11 1 + +// CHANNEL11 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_FIXED_BUFFER 0 + +// CHANNEL11 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DMA_CLEAR_ENABLE 0 + +// CHANNEL11 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 11. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL11_FAULT_TYPE 0 + +// CHANNEL11 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 11. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL11_BUF_TROUGH_N_CREST 0 + +// CHANNEL11 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_A 0 + +// CHANNEL11 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_B 0 + +// CHANNEL11 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_START_STATE 0 + +// CHANNEL11 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_STOP_STATE 0 + +// CHANNEL11 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL11 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_START_STATE 0 + +// CHANNEL11 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_STOP_STATE 0 + +// CHANNEL11 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL11 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_CREST 1 + +// CHANNEL11 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_TROUGH 0 + +// CHANNEL11 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 11. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE 1 + +// CHANNEL11 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 11. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL11_BUFFER_OPERATION 1 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_A 2 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_B 0 + +// CHANNEL11 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL11 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_ENABLE 0 +// UTIMER CHANNEL 11 + +// UTIMER CHANNEL 12 +// Configuration settings for UTIMER channel 12 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL12 1 + +// CHANNEL11 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_VALUE 0 + +// CHANNEL12 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_FIXED_BUFFER 0 + +// CHANNEL12 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DMA_CLEAR_ENABLE 0 + +// CHANNEL12 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 12. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL12_FAULT_TYPE 0 + +// CHANNEL12 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 12. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL12_BUF_TROUGH_N_CREST 0 + +// CHANNEL12 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_A 1 + +// CHANNEL12 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_B 0 + +// CHANNEL12 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_START_STATE 0 + +// CHANNEL12 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_STOP_STATE 0 + +// CHANNEL12 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL12 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_START_STATE 0 + +// CHANNEL12 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_STOP_STATE 0 + +// CHANNEL12 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL12 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_CREST 1 + +// CHANNEL12 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_TROUGH 0 + +// CHANNEL12 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 12. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE 0 + +// CHANNEL12 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 12. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL12_BUFFER_OPERATION 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_A 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_B 0 + +// CHANNEL12 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL12 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_ENABLE 0 + +// CHANNEL12 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 12 + +// UTIMER CHANNEL 13 +// Configuration settings for UTIMER channel 13 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL13 1 + +// CHANNEL13 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_FIXED_BUFFER 0 + +// CHANNEL13 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DMA_CLEAR_ENABLE 0 + +// CHANNEL13 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 13. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL13_FAULT_TYPE 0 + +// CHANNEL13 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 13. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL13_BUF_TROUGH_N_CREST 0 + +// CHANNEL13 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_A 1 + +// CHANNEL13 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_B 0 + +// CHANNEL13 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_START_STATE 0 + +// CHANNEL13 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_STOP_STATE 0 + +// CHANNEL13 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL13 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_START_STATE 0 + +// CHANNEL13 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_STOP_STATE 0 + +// CHANNEL13 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL13 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_CREST 1 + +// CHANNEL13 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_TROUGH 0 + +// CHANNEL13 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 13. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE 0 + +// CHANNEL13 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 13. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL13_BUFFER_OPERATION 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_A 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_B 0 + +// CHANNEL13 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL13 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_ENABLE 0 + +// CHANNEL13 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 13 + +// UTIMER CHANNEL 14 +// Configuration settings for UTIMER channel 14 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL14 1 + +// CHANNEL14 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_FIXED_BUFFER 0 + +// CHANNEL14 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DMA_CLEAR_ENABLE 0 + +// CHANNEL14 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 14. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL14_FAULT_TYPE 0 + +// CHANNEL14 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 14. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL14_BUF_TROUGH_N_CREST 0 + +// CHANNEL14 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_A 1 + +// CHANNEL14 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_B 0 + +// CHANNEL14 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_START_STATE 0 + +// CHANNEL14 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_STOP_STATE 0 + +// CHANNEL14 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL14 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_START_STATE 0 + +// CHANNEL14 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_STOP_STATE 0 + +// CHANNEL14 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL14 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_CREST 1 + +// CHANNEL14 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_TROUGH 0 + +// CHANNEL14 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 14. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE 0 + +// CHANNEL14 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 14. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL14_BUFFER_OPERATION 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_A 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_B 0 + +// CHANNEL14 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL14 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_ENABLE 0 + +// CHANNEL14 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 14 + +// UTIMER CHANNEL 15 +// Configuration settings for UTIMER channel 15 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL15 1 + +// CHANNEL15 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_FIXED_BUFFER 0 + +// CHANNEL15 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DMA_CLEAR_ENABLE 0 + +// CHANNEL15 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 15. +// Default: LOW_UNTIL_CYCLE_END +#define RTE_UTIMER_CHANNEL15_FAULT_TYPE 0 + +// CHANNEL15 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 15. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL15_BUF_TROUGH_N_CREST 0 + +// CHANNEL15 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_A 1 + +// CHANNEL15 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_B 0 + +// CHANNEL15 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_START_STATE 0 + +// CHANNEL15 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_STOP_STATE 0 + +// CHANNEL15 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL15 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_START_STATE 0 + +// CHANNEL15 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_STOP_STATE 0 + +// CHANNEL15 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL15 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_CREST 1 + +// CHANNEL15 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_TROUGH 0 + +// CHANNEL15 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 15. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE 0 + +// CHANNEL15 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 15. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL15_BUFFER_OPERATION 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_A 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_B 0 + +// CHANNEL15 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL15 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_ENABLE 0 + +// CHANNEL15 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 15 +#endif /*RTE_UTIMER*/ +// UTIMER (Universal timer) [Driver_UTIMER] +// UTIMER (Universal Timer) + +// DAC (Digital to analog converter ) +// DAC0 (Digital to analog converter ) [Driver_DAC0] +// Configuration settings for Driver_DAC0 in component ::Drivers:DAC +#define RTE_DAC0 1 +#if RTE_DAC0 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC0_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC0_TWOSCOMP_EN 0 +#endif +// DAC0 (Digital to analog converter) [Driver_DAC0] + +// DAC1 (Digital to analog converter ) [Driver_DAC1] +// Configuration settings for Driver_DAC1 in component ::Drivers:DAC +#define RTE_DAC1 1 +#if RTE_DAC1 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC1_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC1_TWOSCOMP_EN 0 +#endif +// DAC1 (Digital to Analog converter) [Driver_DAC1] +// DAC(Digital to analog converter) + +// ADC (Analog to Digital Converter) +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] +// Configuration settings for Driver_ADC120 in component ::Drivers:ADC12 +#define RTE_ADC120 1 +#if RTE_ADC120 +#define RTE_ADC120_IRQ_PRIORITY 0 + +// ADC120 DONE0 IRQ PRIORITY <0-225> +// defines ADC120 done0 interrupt priority +// default: 0 +#define RTE_ADC120_DONE0_IRQ_PRIORITY 0 + +// ADC120 DONE1 IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_DONE1_IRQ_PRIORITY 0 + +// ADC120 CMPA IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPA_IRQ_PRIORITY 0 + +// ADC120 CMPB IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC120_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC120_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC120_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC120_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC120_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC120_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC120_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC120_DIFFERENTIAL_EN 0 + +// Enable PGA +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC120 PGA enable +// Default: DISABLE +#define RTE_ADC120_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC120_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_BIAS 2 + +#endif +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] + +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] +// Configuration settings for Driver_ADC121 in component ::Drivers:ADC +#define RTE_ADC121 1 +#if RTE_ADC121 + +// ADC121 DONE0 IRQ PRIORITY <0-225> +// defines ADC121 done0 interrupt priority +// default: 0 +#define RTE_ADC121_DONE0_IRQ_PRIORITY 0 + +// ADC121 DONE1 IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_DONE1_IRQ_PRIORITY 0 + +// ADC121 CMPA IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPA_IRQ_PRIORITY 0 + +// ADC121 CMPB IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC121_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC121_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC121_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC121_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC121_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC121_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC121_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC121_DIFFERENTIAL_EN 0 + +// Pga enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC121 using PGA gain +// Default: DISABLE +#define RTE_ADC121_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC121_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_BIAS 2 + +#endif +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] + +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] +// Configuration settings for Driver_ADC122 in component ::Drivers:ADC +#define RTE_ADC122 1 +#if RTE_ADC122 + +// ADC122 DONE0 IRQ PRIORITY <0-225> +// defines ADC122 done0 interrupt priority +// default: 0 +#define RTE_ADC122_DONE0_IRQ_PRIORITY 0 + +// ADC122 DONE1 IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_DONE1_IRQ_PRIORITY 0 + +// ADC122 CMPA IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPA_IRQ_PRIORITY 0 + +// ADC122 CMPB IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC122_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC122_CLOCK_DIV (2) + +// Sample Width <2-32> +// defines Width in divided clocks of the sample output signal +// default: 16 +#define RTE_ADC122_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC122_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC122_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC122_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC122_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC122_DIFFERENTIAL_EN 0 + +// Enable PGA ADC122 +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC122 using PGA gain +// Default: DISABLE +#define RTE_ADC122_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC122_PGA_GAIN (0) +// RTE_ADC122_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_BIAS 2 + +#endif +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] + +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// Configuration settings for Driver_ADC24 in component ::Drivers:ADC +#define RTE_ADC24 1 +#if RTE_ADC24 + +// ADC24 DONE0 IRQ PRIORITY <0-225> +// defines ADC24 done0 interrupt priority +// default: 0 +#define RTE_ADC24_DONE0_IRQ_PRIORITY 0 + +// ADC24 DONE1 IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_DONE1_IRQ_PRIORITY 0 + +// ADC24 CMPA IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPA_IRQ_PRIORITY 0 + +// ADC24 CMPB IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-4> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC24_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC24_CLOCK_DIV (2) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC24_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC24_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC24_SHIFT_LEFT_OR_RIGHT (1) + +// Ouput rate select +// <0=> 1 KS/s +// <1=> 2 KS/s +// <2=> 4 KS/s +// <3=> 8 KS/s +// <4=> 16 KS/s +// Defines Select adc24 output rate +// Default: 0 +#define RTE_ADC24_OUTPUT_RATE (0) + +// PGA enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable PGA to set PGA gain +// Default: DISABLE +#define RTE_ADC24_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC24_PGA_GAIN (0) + +// Bias Control +// <0=> 5 uA +// <1=> 6.25 uA +// <3=> 7.5 uA +// <7=> 8.75 uA +// Defines Bias control +// Default: 3 +#define RTE_ADC24_BIAS (3) + +#endif +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// ADC (Analog to Digital Converter) + +// CRC (Cyclic Redundancy Check) +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] +// Configuration settings for Driver_CRC0 in component ::Drivers:CRC +#define RTE_CRC0 1 +#if RTE_CRC0 + +// CRC0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC0 +// Default: 0 +#define RTE_CRC0_DMA_ENABLE 0 +#if RTE_CRC0_DMA_ENABLE + +// CRC0 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC0. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC0_SELECT_DMA 0 +#endif + +// CRC0 DMA IRQ priority <0-255> +// Defines CRC0 DMA Interrupt priority +// Default: 0 +#define RTE_CRC0_DMA_IRQ_PRI 0 +#endif +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] + +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// Configuration settings for Driver_CRC1 in component ::Drivers:CRC +#define RTE_CRC1 1 +#if RTE_CRC1 + +// CRC1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC1 +// Default: 0 +#define RTE_CRC1_DMA_ENABLE 0 +#if RTE_CRC1_DMA_ENABLE + +// CRC1 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC1. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC1_SELECT_DMA 0 +#endif + +// CRC1 DMA IRQ priority <0-255> +// Defines CRC1 DMA Interrupt priority +// Default: 0 +#define RTE_CRC1_DMA_IRQ_PRI 0 +#endif +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// + +// HWSEM (Hardware Semaphore) +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] +// Configuration settings for Driver_HWSEM0 in component ::Drivers:HWSEM +#define RTE_HWSEM0 1 +#if RTE_HWSEM0 + +// HWSEM0 IRQ priority <0-255> +// Defines HWSEM0 Interrupt priority +// Default: 0 +#define RTE_HWSEM0_IRQPRIORITY 0 +#endif + +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] +// Configuration settings for Driver_HWSEM1 in component ::Drivers:HWSEM +#define RTE_HWSEM1 0 +#if RTE_HWSEM1 + +// HWSEM1 IRQ priority <0-255> +// Defines HWSEM1 Interrupt priority +// Default: 0 +#define RTE_HWSEM1_IRQPRIORITY 0 +#endif + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] +// Configuration settings for Driver_HWSEM2 in component ::Drivers:HWSEM +#define RTE_HWSEM2 0 +#if RTE_HWSEM2 + +// HWSEM2 IRQ priority <0-255> +// Defines HWSEM2 Interrupt priority +// Default: 0 +#define RTE_HWSEM2_IRQPRIORITY 0 +#endif + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] +// Configuration settings for Driver_HWSEM3 in component ::Drivers:HWSEM +#define RTE_HWSEM3 0 +#if RTE_HWSEM3 + +// HWSEM3 IRQ priority <0-255> +// Defines HWSEM3 Interrupt priority +// Default: 0 +#define RTE_HWSEM3_IRQPRIORITY 0 +#endif + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] +// Configuration settings for Driver_HWSEM4 in component ::Drivers:HWSEM +#define RTE_HWSEM4 0 +#if RTE_HWSEM4 + +// HWSEM4 IRQ priority <0-255> +// Defines HWSEM4 Interrupt priority +// Default: 0 +#define RTE_HWSEM4_IRQPRIORITY 0 +#endif + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] +// Configuration settings for Driver_HWSEM5 in component ::Drivers:HWSEM +#define RTE_HWSEM5 0 +#if RTE_HWSEM5 + +// HWSEM5 IRQ priority <0-255> +// Defines HWSEM5 Interrupt priority +// Default: 0 +#define RTE_HWSEM5_IRQPRIORITY 0 +#endif + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] +// Configuration settings for Driver_HWSEM6 in component ::Drivers:HWSEM +#define RTE_HWSEM6 0 +#if RTE_HWSEM6 + +// HWSEM6 IRQ priority <0-255> +// Defines HWSEM6 Interrupt priority +// Default: 0 +#define RTE_HWSEM6_IRQPRIORITY 0 +#endif + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] +// Configuration settings for Driver_HWSEM7 in component ::Drivers:HWSEM +#define RTE_HWSEM7 0 +#if RTE_HWSEM7 + +// HWSEM7 IRQ priority <0-255> +// Defines HWSEM7 Interrupt priority +// Default: 0 +#define RTE_HWSEM7_IRQPRIORITY 0 +#endif + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] +// Configuration settings for Driver_HWSEM8 in component ::Drivers:HWSEM +#define RTE_HWSEM8 0 +#if RTE_HWSEM8 + +// HWSEM8 IRQ priority <0-255> +// Defines HWSEM8 Interrupt priority +// Default: 0 +#define RTE_HWSEM8_IRQPRIORITY 0 +#endif + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] +// Configuration settings for Driver_HWSEM9 in component ::Drivers:HWSEM +#define RTE_HWSEM9 0 +#if RTE_HWSEM9 + +// HWSEM9 IRQ priority <0-255> +// Defines HWSEM9 Interrupt priority +// Default: 0 +#define RTE_HWSEM9_IRQPRIORITY 0 +#endif + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] +// Configuration settings for Driver_HWSEM10 in component ::Drivers:HWSEM +#define RTE_HWSEM10 0 +#if RTE_HWSEM10 + +// HWSEM10 IRQ priority <0-255> +// Defines HWSEM10 Interrupt priority +// Default: 0 +#define RTE_HWSEM10_IRQPRIORITY 0 +#endif + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] +// Configuration settings for Driver_HWSEM11 in component ::Drivers:HWSEM +#define RTE_HWSEM11 0 +#if RTE_HWSEM11 + +// HWSEM11 IRQ priority <0-255> +// Defines HWSEM11 Interrupt priority +// Default: 0 +#define RTE_HWSEM11_IRQPRIORITY 0 +#endif + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] +// Configuration settings for Driver_HWSEM12 in component ::Drivers:HWSEM +#define RTE_HWSEM12 0 +#if RTE_HWSEM12 + +// HWSEM12 IRQ priority <0-255> +// Defines HWSEM12 Interrupt priority +// Default: 0 +#define RTE_HWSEM12_IRQPRIORITY 0 +#endif + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] +// Configuration settings for Driver_HWSEM13 in component ::Drivers:HWSEM +#define RTE_HWSEM13 0 +#if RTE_HWSEM13 + +// HWSEM13 IRQ priority <0-255> +// Defines HWSEM13 Interrupt priority +// Default: 0 +#define RTE_HWSEM13_IRQPRIORITY 0 +#endif + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] +// Configuration settings for Driver_HWSEM14 in component ::Drivers:HWSEM +#define RTE_HWSEM14 0 +#if RTE_HWSEM14 + +// HWSEM14 IRQ priority <0-255> +// Defines HWSEM14 Interrupt priority +// Default: 0 +#define RTE_HWSEM14_IRQPRIORITY 0 +#endif + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// Configuration settings for Driver_HWSEM15 in component ::Drivers:HWSEM +#define RTE_HWSEM15 0 +#if RTE_HWSEM15 + +// HWSEM15 IRQ priority <0-255> +// Defines HWSEM15 Interrupt priority +// Default: 0 +#define RTE_HWSEM15_IRQPRIORITY 0 +#endif + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// + +// High speed Analog Comparator +// CMP0 (Analog Comparator ) [Driver_CMP0] +// Configuration settings for Driver_CMP0 in component ::Drivers:Comparator +#define RTE_HSCMP0 1 +#if RTE_HSCMP0 + +// CMP0 IRQ priority <0-255> +// Defines Interrupt priority for CMP0. +// Default: 0 +#define RTE_CMP0_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_0 +// <1=> PIN_P0_6 +// <2=> PIN_P1_4 +// <3=> PIN_P0_4 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_0; 01 = P0_6; 10 = P1_4; 11 = P0_4 +// Default : 0 +#define RTE_CMP0_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP0_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP0_SEL_HYSTERISIS 7 + +#endif +// CMP0 (Analog Comparator) [Driver_CMP0] + +// CMP1 (Analog Comparator ) [Driver_CMP1] +// Configuration settings for Driver_CMP1 in component ::Drivers:Comparator +#define RTE_HSCMP1 1 +#if RTE_HSCMP1 + +// CMP1 IRQ priority <0-255> +// Defines Interrupt priority for CMP1. +// Default: 0 +#define RTE_CMP1_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_1 +// <1=> PIN_P0_7 +// <2=> PIN_P1_5 +// <3=> PIN_P0_5 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_1; 01 = P0_7; 10 = P1_5; 11 = P0_5 +// Default : 0 +#define RTE_CMP1_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP1_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP1_SEL_HYSTERISIS 7 + +#endif +// CMP1 (Analog Comparator) [Driver_CMP1] + +// CMP2 (Analog Comparator ) [Driver_CMP2] +// Configuration settings for Driver_CMP2 in component ::Drivers:Comparator +#define RTE_HSCMP2 1 +#if RTE_HSCMP2 + +// CMP2 IRQ priority <0-255> +// Defines Interrupt priority for CMP2. +// Default: 0 +#define RTE_CMP2_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_2 +// <1=> PIN_P1_0 +// <2=> PIN_P1_6 +// <3=> PIN_P1_2 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_2; 01 = P1_0; 10 = P1_6; 11 = P1_2 +// Default : 0 +#define RTE_CMP2_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP2_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP2_SEL_HYSTERISIS 7 + +#endif +// CMP2 (Analog Comparator) [Driver_CMP2] + +// CMP3 (Analog Comparator ) [Driver_CMP3] +// Configuration settings for Driver_CMP3 in component ::Drivers:Comparator +#define RTE_HSCMP3 1 +#if RTE_HSCMP3 + +// CMP3 IRQ priority <0-255> +// Defines Interrupt priority for CMP3. +// Default: 0 +#define RTE_CMP3_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_3 +// <1=> PIN_P1_1 +// <2=> PIN_P1_7 +// <3=> PIN_P1_3 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_3; 01 = P1_1; 10 = P1_7; 11 = P1_3 +// Default : 0 +#define RTE_CMP3_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP3_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP3_SEL_HYSTERISIS 7 + +#endif +// CMP3 (Analog Comparator) [Driver_CMP3] + +#if defined(RTSS_HE) +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +// Configuration settings for Driver_LPCMP in component ::Drivers:LPCMP +#define RTE_LPCMP 1 + +#if RTE_LPCMP + +// LPCMP IRQ priority <0-255> +// Defines Interrupt priority for LPCMP. +// Default: 0 +#define RTE_LPCMP_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P2_4 +// <1=> PIN_P2_5 +// <2=> PIN_P2_6 +// <3=> PIN_P2_7 +// Defines:select input to the positive terminal of LPCMP; +// 00 = P2_4; 01 = P2_5; 10 = P2_6; 11 = P2_7 +// Default : 0 +#define RTE_LPCMP_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> AON_VREF +// <1=> PIN_P2_0 +// <2=> PIN_P2_1 +// <3=> PIN_P2_2 +// Defines: select input to the negative terminal of LPCMP; +// 00 = AON Vref(0.8v); 01 = P2_0; 10 = P2_1 Vref; 11 = P2_2 +// Default : 0 +#define RTE_LPCMP_SEL_NEGATIVE 0 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select LPCMP hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_LPCMP_SEL_HYSTERISIS 7 + +#endif +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +#endif // defined(RTSS_HE) +// CMP (Analog Comparator) + +// I2C (Inter Integrated Circuit) +// I2C (Inter Integrated Circuit) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#if RTE_I2C0 + +// I2C0 IRQ priority <0-255> +// Defines Interrupt priority for I2C0. +// Default: 0 +#define RTE_I2C0_IRQ_PRIORITY 0 +// I2C0 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C0. +// Default: 16 +#define RTE_I2C0_TX_FIFO_THRESHOLD 16 + +// I2C0 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C0. +// Default: 0 +#define RTE_I2C0_RX_FIFO_THRESHOLD 0 + +// I2C0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C0 +// Default: DISABLE +#define RTE_I2C0_DMA_ENABLE 0 +#if RTE_I2C0_DMA_ENABLE + +// I2C0 DMA IRQ priority <0-255> +// Defines I2C0 DMA Interrupt priority +// Default: 0 +#define RTE_I2C0_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C0] + +// I2C (Inter Integrated Circuit) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#if RTE_I2C1 + +// I2C1 IRQ priority <0-255> +// Defines Interrupt priority for I2C1. +// Default: 0 +#define RTE_I2C1_IRQ_PRIORITY 0 +// I2C1 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C1. +// Default: 16 +#define RTE_I2C1_TX_FIFO_THRESHOLD 16 + +// I2C1 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C1. +// Default: 0 +#define RTE_I2C1_RX_FIFO_THRESHOLD 0 + +// I2C1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C1 +// Default: DISABLE +#define RTE_I2C1_DMA_ENABLE 0 +#if RTE_I2C1_DMA_ENABLE + +// I2C1 DMA IRQ priority <0-255> +// Defines I2C1 DMA Interrupt priority +// Default: 0 +#define RTE_I2C1_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C1] + +// I2C (Inter Integrated Circuit) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C + +#define RTE_I2C2 1 +#if RTE_I2C2 + +// I2C2 IRQ priority <0-255> +// Defines Interrupt priority for I2C2. +// Default: 0 +#define RTE_I2C2_IRQ_PRIORITY 0 +// I2C2 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C2. +// Default: 16 +#define RTE_I2C2_TX_FIFO_THRESHOLD 16 + +// I2C2 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C2. +// Default: 0 +#define RTE_I2C2_RX_FIFO_THRESHOLD 0 + +// I2C2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C2 +// Default: DISABLE +#define RTE_I2C2_DMA_ENABLE 0 +#if RTE_I2C2_DMA_ENABLE + +// I2C2 DMA IRQ priority <0-255> +// Defines I2C2 DMA Interrupt priority +// Default: 0 +#define RTE_I2C2_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C2] + +// I2C (Inter Integrated Circuit) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C + +#define RTE_I2C3 1 + +#if RTE_I2C3 + +// I2C3 IRQ priority <0-255> +// Defines Interrupt priority for I2C3. +// Default: 0 +#define RTE_I2C3_IRQ_PRIORITY 0 +// I2C3 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C3. +// Default: 16 +#define RTE_I2C3_TX_FIFO_THRESHOLD 16 + +// I2C3 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C3. +// Default: 0 +#define RTE_I2C3_RX_FIFO_THRESHOLD 0 + +// I2C3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C3 +// Default: DISABLE +#define RTE_I2C3_DMA_ENABLE 0 +#if RTE_I2C3_DMA_ENABLE + +// I2C3 DMA IRQ priority <0-255> +// Defines I2C3 DMA Interrupt priority +// Default: 0 +#define RTE_I2C3_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C3] + +// LPI2C0 (Low Power Inter-Integrated Circuit) [Driver_LPI2C0] +// Configuration settings for Driver_LPI2C0 in component ::Drivers:LPI2C +#if defined(RTSS_HE) +#define RTE_LPI2C0 1 +#if RTE_LPI2C0 + +// LPI2C0 IRQ PRIORITY <0-225> +// defines LPI2C0 interrupt priority +// default: 0 +#define RTE_LPI2C0_IRQ_PRIORITY 0 + +// LPI2C0 Bus-Speed <1-400000> +// defines LPI2C0 Bus-Speed - It is used for Bit-time calculation in driver +// default: 400KHz +#define RTE_LPI2C0_BUS_SPEED 400000 + +#endif +// LPI2C0(Low Power Inter-Integrated Circuit) [Driver_LPI2C0] +#endif // defined(RTSS_HE) +// + +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] +// Configuration settings for Driver_DMA0 in component ::Drivers:DMA +#define RTE_DMA0 1 +#if RTE_DMA0 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA0_APB_INTERFACE 0 +// DMA0 Abort interrupt priority <0-255> +// Defines DMA0 Abort interrupt priority. +// Default: 0 +#define RTE_DMA0_ABORT_IRQ_PRI 0 +// DMA0 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_IRQ_NS_STATE 0 +// DMA0 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_PERIPH_NS_STATE 0 +#endif +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] + +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] +#if defined(RTSS_HP) + +// Configuration settings for Driver_DMA1 in component ::Drivers:DMA +#define RTE_DMA1 1 +#if RTE_DMA1 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA1_APB_INTERFACE 0 +// DMA1 Abort interrupt priority <0-255> +// Defines DMA1 Abort interrupt priority. +// Default: 0 +#define RTE_DMA1_ABORT_IRQ_PRI 0 +// DMA1 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_IRQ_NS_STATE 0 +// DMA1 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] + +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] +// Configuration settings for Driver_DMA2 in component ::Drivers:DMA +#if defined(RTSS_HE) + +#define RTE_DMA2 1 +#if RTE_DMA2 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA2_APB_INTERFACE 0 +// DMA2 Abort interrupt priority <0-255> +// Defines DMA2 Abort interrupt priority. +// Default: 0 +#define RTE_DMA2_ABORT_IRQ_PRI 0 +// DMA2 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_IRQ_NS_STATE 0 +// DMA2 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] + +// GPIO (general purpose input and output) +// GPIO0 +// Configuration settings for Driver_GPIO0 in component ::Drivers:GPIO +#define RTE_GPIO0 1 + +#if RTE_GPIO0 + +// GPIO0 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO0. +// Default: 0 +#define RTE_GPIO0_DB_CLK_DIV 1 + +// GPIO0_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN0. +// Default: 0 +#define RTE_GPIO0_PIN0_IRQ_PRIORITY 0 + +// GPIO0_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN1. +// Default: 0 +#define RTE_GPIO0_PIN1_IRQ_PRIORITY 0 + +// GPIO0_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN2. +// Default: 0 +#define RTE_GPIO0_PIN2_IRQ_PRIORITY 0 + +// GPIO0_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN3. +// Default: 0 +#define RTE_GPIO0_PIN3_IRQ_PRIORITY 0 + +// GPIO0_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN4. +// Default: 0 +#define RTE_GPIO0_PIN4_IRQ_PRIORITY 0 + +// GPIO0_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN5. +// Default: 0 +#define RTE_GPIO0_PIN5_IRQ_PRIORITY 0 + +// GPIO0_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN6. +// Default: 0 +#define RTE_GPIO0_PIN6_IRQ_PRIORITY 0 + +// GPIO0_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN7. +// Default: 0 +#define RTE_GPIO0_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO0 + +// GPIO1 +// Configuration settings for Driver_GPIO1 in component ::Drivers:GPIO +#define RTE_GPIO1 1 + +#if RTE_GPIO1 + +// GPIO1 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO1. +// Default: 0 +#define RTE_GPIO1_DB_CLK_DIV 1 + +// GPIO1_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN0. +// Default: 0 +#define RTE_GPIO1_PIN0_IRQ_PRIORITY 0 + +// GPIO1_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN1. +// Default: 0 +#define RTE_GPIO1_PIN1_IRQ_PRIORITY 0 + +// GPIO1_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN2. +// Default: 0 +#define RTE_GPIO1_PIN2_IRQ_PRIORITY 0 + +// GPIO1_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO1_PIN3_IRQ_PRIORITY 0 + +// GPIO1_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN4. +// Default: 0 +#define RTE_GPIO1_PIN4_IRQ_PRIORITY 0 + +// GPIO1_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN5. +// Default: 0 +#define RTE_GPIO1_PIN5_IRQ_PRIORITY 0 + +// GPIO1_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN6. +// Default: 0 +#define RTE_GPIO1_PIN6_IRQ_PRIORITY 0 + +// GPIO1_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN7. +// Default: 0 +#define RTE_GPIO1_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO1 + +// GPIO2 +// Configuration settings for Driver_GPIO2 in component ::Drivers:GPIO +#define RTE_GPIO2 1 + +#if RTE_GPIO2 + +// GPIO2 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO2. +// Default: 0 +#define RTE_GPIO2_DB_CLK_DIV 1 + +// GPIO2_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN0. +// Default: 0 +#define RTE_GPIO2_PIN0_IRQ_PRIORITY 0 + +// GPIO2_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN1. +// Default: 0 +#define RTE_GPIO2_PIN1_IRQ_PRIORITY 0 + +// GPIO2_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN2. +// Default: 0 +#define RTE_GPIO2_PIN2_IRQ_PRIORITY 0 + +// GPIO2_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO2_PIN3_IRQ_PRIORITY 0 + +// GPIO2_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN4. +// Default: 0 +#define RTE_GPIO2_PIN4_IRQ_PRIORITY 0 + +// GPIO2_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN5. +// Default: 0 +#define RTE_GPIO2_PIN5_IRQ_PRIORITY 0 + +// GPIO2_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN6. +// Default: 0 +#define RTE_GPIO2_PIN6_IRQ_PRIORITY 0 + +// GPIO2_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN7. +// Default: 0 +#define RTE_GPIO2_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO2 + +// GPIO3 +// Configuration settings for Driver_GPIO3 in component ::Drivers:GPIO +#define RTE_GPIO3 1 + +#if RTE_GPIO3 + +// GPIO3 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO3. +// Default: 0 +#define RTE_GPIO3_DB_CLK_DIV 1 + +// GPIO3_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN0. +// Default: 0 +#define RTE_GPIO3_PIN0_IRQ_PRIORITY 0 + +// GPIO3_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN1. +// Default: 0 +#define RTE_GPIO3_PIN1_IRQ_PRIORITY 0 + +// GPIO3_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN2. +// Default: 0 +#define RTE_GPIO3_PIN2_IRQ_PRIORITY 0 + +// GPIO3_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN3. +// Default: 0 +#define RTE_GPIO3_PIN3_IRQ_PRIORITY 0 + +// GPIO3_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN4. +// Default: 0 +#define RTE_GPIO3_PIN4_IRQ_PRIORITY 0 + +// GPIO3_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN5. +// Default: 0 +#define RTE_GPIO3_PIN5_IRQ_PRIORITY 0 + +// GPIO3_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN6. +// Default: 0 +#define RTE_GPIO3_PIN6_IRQ_PRIORITY 0 + +// GPIO3_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN7. +// Default: 0 +#define RTE_GPIO3_PIN7_IRQ_PRIORITY 0 + +// GPIO3_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO3 + +// GPIO4 +// Configuration settings for Driver_GPIO4 in component ::Drivers:GPIO +#define RTE_GPIO4 1 + +#if RTE_GPIO4 + +// GPIO4 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO4. +// Default: 0 +#define RTE_GPIO4_DB_CLK_DIV 1 + +// GPIO4_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN0. +// Default: 0 +#define RTE_GPIO4_PIN0_IRQ_PRIORITY 0 + +// GPIO4_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN1. +// Default: 0 +#define RTE_GPIO4_PIN1_IRQ_PRIORITY 0 + +// GPIO4_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN2. +// Default: 0 +#define RTE_GPIO4_PIN2_IRQ_PRIORITY 0 + +// GPIO4_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN3. +// Default: 0 +#define RTE_GPIO4_PIN3_IRQ_PRIORITY 0 + +// GPIO4_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN4. +// Default: 0 +#define RTE_GPIO4_PIN4_IRQ_PRIORITY 0 + +// GPIO4_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN5. +// Default: 0 +#define RTE_GPIO4_PIN5_IRQ_PRIORITY 0 + +// GPIO4_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN6. +// Default: 0 +#define RTE_GPIO4_PIN6_IRQ_PRIORITY 0 + +// GPIO4_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN7. +// Default: 0 +#define RTE_GPIO4_PIN7_IRQ_PRIORITY 0 + +// GPIO4_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// GPIO4 + +// GPIO5 +// Configuration settings for Driver_GPIO5 in component ::Drivers:GPIO +#define RTE_GPIO5 1 + +#if RTE_GPIO5 + +// GPIO5 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO5. +// Default: 0 +#define RTE_GPIO5_DB_CLK_DIV 1 + +// GPIO5_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN0. +// Default: 0 +#define RTE_GPIO5_PIN0_IRQ_PRIORITY 0 + +// GPIO5_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN1. +// Default: 0 +#define RTE_GPIO5_PIN1_IRQ_PRIORITY 0 + +// GPIO5_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN2. +// Default: 0 +#define RTE_GPIO5_PIN2_IRQ_PRIORITY 0 + +// GPIO5_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN3. +// Default: 0 +#define RTE_GPIO5_PIN3_IRQ_PRIORITY 0 + +// GPIO5_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN4. +// Default: 0 +#define RTE_GPIO5_PIN4_IRQ_PRIORITY 0 + +// GPIO5_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN5. +// Default: 0 +#define RTE_GPIO5_PIN5_IRQ_PRIORITY 0 + +// GPIO5_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN6. +// Default: 0 +#define RTE_GPIO5_PIN6_IRQ_PRIORITY 0 + +// GPIO5_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN7. +// Default: 0 +#define RTE_GPIO5_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO5 + +// GPIO6 +// Configuration settings for Driver_GPIO6 in component ::Drivers:GPIO +#define RTE_GPIO6 1 + +#if RTE_GPIO6 + +// GPIO6 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO6. +// Default: 0 +#define RTE_GPIO6_DB_CLK_DIV 1 + +// GPIO6_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN0. +// Default: 0 +#define RTE_GPIO6_PIN0_IRQ_PRIORITY 0 + +// GPIO6_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN1. +// Default: 0 +#define RTE_GPIO6_PIN1_IRQ_PRIORITY 0 + +// GPIO6_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN2. +// Default: 0 +#define RTE_GPIO6_PIN2_IRQ_PRIORITY 0 + +// GPIO6_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN3. +// Default: 0 +#define RTE_GPIO6_PIN3_IRQ_PRIORITY 0 + +// GPIO6_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN4. +// Default: 0 +#define RTE_GPIO6_PIN4_IRQ_PRIORITY 0 + +// GPIO6_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN5. +// Default: 0 +#define RTE_GPIO6_PIN5_IRQ_PRIORITY 0 + +// GPIO6_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN6. +// Default: 0 +#define RTE_GPIO6_PIN6_IRQ_PRIORITY 0 + +// GPIO6_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN7. +// Default: 0 +#define RTE_GPIO6_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO6 + +// GPIO7 +// Configuration settings for Driver_GPIO7 in component ::Drivers:GPIO +#define RTE_GPIO7 1 + +#if RTE_GPIO7 + +// GPIO7 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO7. +// Default: 0 +#define RTE_GPIO7_DB_CLK_DIV 1 + +// GPIO7_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN0. +// Default: 0 +#define RTE_GPIO7_PIN0_IRQ_PRIORITY 0 + +// GPIO7_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN1. +// Default: 0 +#define RTE_GPIO7_PIN1_IRQ_PRIORITY 0 + +// GPIO7_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN2. +// Default: 0 +#define RTE_GPIO7_PIN2_IRQ_PRIORITY 0 + +// GPIO7_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN3. +// Default: 0 +#define RTE_GPIO7_PIN3_IRQ_PRIORITY 0 + +// GPIO7_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN4. +// Default: 0 +#define RTE_GPIO7_PIN4_IRQ_PRIORITY 0 + +// GPIO7_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN5. +// Default: 0 +#define RTE_GPIO7_PIN5_IRQ_PRIORITY 0 + +// GPIO7_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN6. +// Default: 0 +#define RTE_GPIO7_PIN6_IRQ_PRIORITY 0 + +// GPIO7_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN7. +// Default: 0 +#define RTE_GPIO7_PIN7_IRQ_PRIORITY 0 + +// GPIO7_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO7 + +// GPIO8 +// Configuration settings for Driver_GPIO8 in component ::Drivers:GPIO +#define RTE_GPIO8 1 + +#if RTE_GPIO8 + +// GPIO8 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO8. +// Default: 0 +#define RTE_GPIO8_DB_CLK_DIV 1 + +// GPIO8_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN0. +// Default: 0 +#define RTE_GPIO8_PIN0_IRQ_PRIORITY 0 + +// GPIO8_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN1. +// Default: 0 +#define RTE_GPIO8_PIN1_IRQ_PRIORITY 0 + +// GPIO8_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN2. +// Default: 0 +#define RTE_GPIO8_PIN2_IRQ_PRIORITY 0 + +// GPIO8_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN3. +// Default: 0 +#define RTE_GPIO8_PIN3_IRQ_PRIORITY 0 + +// GPIO8_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN4. +// Default: 0 +#define RTE_GPIO8_PIN4_IRQ_PRIORITY 0 + +// GPIO8_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN5. +// Default: 0 +#define RTE_GPIO8_PIN5_IRQ_PRIORITY 0 + +// GPIO8_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN6. +// Default: 0 +#define RTE_GPIO8_PIN6_IRQ_PRIORITY 0 + +// GPIO8_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN7. +// Default: 0 +#define RTE_GPIO8_PIN7_IRQ_PRIORITY 0 + +// GPIO8_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO8 + +// GPIO9 +// Configuration settings for Driver_GPIO9 in component ::Drivers:GPIO +#define RTE_GPIO9 1 + +#if RTE_GPIO9 + +// GPIO9 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO9. +// Default: 0 +#define RTE_GPIO9_DB_CLK_DIV 1 + +// GPIO9_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN0. +// Default: 0 +#define RTE_GPIO9_PIN0_IRQ_PRIORITY 0 + +// GPIO9_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN1. +// Default: 0 +#define RTE_GPIO9_PIN1_IRQ_PRIORITY 0 + +// GPIO9_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN2. +// Default: 0 +#define RTE_GPIO9_PIN2_IRQ_PRIORITY 0 + +// GPIO9_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN3. +// Default: 0 +#define RTE_GPIO9_PIN3_IRQ_PRIORITY 0 + +// GPIO9_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN4. +// Default: 0 +#define RTE_GPIO9_PIN4_IRQ_PRIORITY 0 + +// GPIO9_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN5. +// Default: 0 +#define RTE_GPIO9_PIN5_IRQ_PRIORITY 0 + +// GPIO9_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN6. +// Default: 0 +#define RTE_GPIO9_PIN6_IRQ_PRIORITY 0 + +// GPIO9_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN7. +// Default: 0 +#define RTE_GPIO9_PIN7_IRQ_PRIORITY 0 + +// GPIO9_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO9 + +// GPIO10 +// Configuration settings for Driver_GPIO10 in component ::Drivers:GPIO +#define RTE_GPIO10 1 + +#if RTE_GPIO10 + +// GPIO10 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO10. +// Default: 0 +#define RTE_GPIO10_DB_CLK_DIV 1 + +// GPIO10_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN0. +// Default: 0 +#define RTE_GPIO10_PIN0_IRQ_PRIORITY 0 + +// GPIO10_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN1. +// Default: 0 +#define RTE_GPIO10_PIN1_IRQ_PRIORITY 0 + +// GPIO10_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN2. +// Default: 0 +#define RTE_GPIO10_PIN2_IRQ_PRIORITY 0 + +// GPIO10_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN3. +// Default: 0 +#define RTE_GPIO10_PIN3_IRQ_PRIORITY 0 + +// GPIO10_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN4. +// Default: 0 +#define RTE_GPIO10_PIN4_IRQ_PRIORITY 0 + +// GPIO10_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN5. +// Default: 0 +#define RTE_GPIO10_PIN5_IRQ_PRIORITY 0 + +// GPIO10_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN6. +// Default: 0 +#define RTE_GPIO10_PIN6_IRQ_PRIORITY 0 + +// GPIO10_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN7. +// Default: 0 +#define RTE_GPIO10_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO10 + +// GPIO11 +// Configuration settings for Driver_GPIO11 in component ::Drivers:GPIO +#define RTE_GPIO11 1 + +#if RTE_GPIO11 + +// GPIO11 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO11. +// Default: 0 +#define RTE_GPIO11_DB_CLK_DIV 1 + +// GPIO11_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN0. +// Default: 0 +#define RTE_GPIO11_PIN0_IRQ_PRIORITY 0 + +// GPIO11_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN1. +// Default: 0 +#define RTE_GPIO11_PIN1_IRQ_PRIORITY 0 + +// GPIO11_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN2. +// Default: 0 +#define RTE_GPIO11_PIN2_IRQ_PRIORITY 0 + +// GPIO11_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN3. +// Default: 0 +#define RTE_GPIO11_PIN3_IRQ_PRIORITY 0 + +// GPIO11_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN4. +// Default: 0 +#define RTE_GPIO11_PIN4_IRQ_PRIORITY 0 + +// GPIO11_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN5. +// Default: 0 +#define RTE_GPIO11_PIN5_IRQ_PRIORITY 0 + +// GPIO11_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN6. +// Default: 0 +#define RTE_GPIO11_PIN6_IRQ_PRIORITY 0 + +// GPIO11_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN7. +// Default: 0 +#define RTE_GPIO11_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO11 + +// GPIO12 +// Configuration settings for Driver_GPIO12 in component ::Drivers:GPIO +#define RTE_GPIO12 1 + +#if RTE_GPIO12 + +// GPIO12 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO12. +// Default: 0 +#define RTE_GPIO12_DB_CLK_DIV 1 + +// GPIO12_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN0. +// Default: 0 +#define RTE_GPIO12_PIN0_IRQ_PRIORITY 0 + +// GPIO12_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN1. +// Default: 0 +#define RTE_GPIO12_PIN1_IRQ_PRIORITY 0 + +// GPIO12_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN2. +// Default: 0 +#define RTE_GPIO12_PIN2_IRQ_PRIORITY 0 + +// GPIO12_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN3. +// Default: 0 +#define RTE_GPIO12_PIN3_IRQ_PRIORITY 0 + +// GPIO12_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN4. +// Default: 0 +#define RTE_GPIO12_PIN4_IRQ_PRIORITY 0 + +// GPIO12_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN5. +// Default: 0 +#define RTE_GPIO12_PIN5_IRQ_PRIORITY 0 + +// GPIO12_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN6. +// Default: 0 +#define RTE_GPIO12_PIN6_IRQ_PRIORITY 0 + +// GPIO12_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN7. +// Default: 0 +#define RTE_GPIO12_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO12 + +// GPIO13 +// Configuration settings for Driver_GPIO13 in component ::Drivers:GPIO +#define RTE_GPIO13 1 + +#if RTE_GPIO13 + +// GPIO13 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO13. +// Default: 0 +#define RTE_GPIO13_DB_CLK_DIV 1 + +// GPIO13_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN0. +// Default: 0 +#define RTE_GPIO13_PIN0_IRQ_PRIORITY 0 + +// GPIO13_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN1. +// Default: 0 +#define RTE_GPIO13_PIN1_IRQ_PRIORITY 0 + +// GPIO13_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN2. +// Default: 0 +#define RTE_GPIO13_PIN2_IRQ_PRIORITY 0 + +// GPIO13_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN3. +// Default: 0 +#define RTE_GPIO13_PIN3_IRQ_PRIORITY 0 + +// GPIO13_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN4. +// Default: 0 +#define RTE_GPIO13_PIN4_IRQ_PRIORITY 0 + +// GPIO13_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN5. +// Default: 0 +#define RTE_GPIO13_PIN5_IRQ_PRIORITY 0 + +// GPIO13_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN6. +// Default: 0 +#define RTE_GPIO13_PIN6_IRQ_PRIORITY 0 + +// GPIO13_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN7. +// Default: 0 +#define RTE_GPIO13_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO13 + +// GPIO14 +// Configuration settings for Driver_GPIO14 in component ::Drivers:GPIO +#define RTE_GPIO14 1 + +#if RTE_GPIO14 + +// GPIO14 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO14. +// Default: 0 +#define RTE_GPIO14_DB_CLK_DIV 1 + +// GPIO14_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN0. +// Default: 0 +#define RTE_GPIO14_PIN0_IRQ_PRIORITY 0 + +// GPIO14_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN1. +// Default: 0 +#define RTE_GPIO14_PIN1_IRQ_PRIORITY 0 + +// GPIO14_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN2. +// Default: 0 +#define RTE_GPIO14_PIN2_IRQ_PRIORITY 0 + +// GPIO14_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN3. +// Default: 0 +#define RTE_GPIO14_PIN3_IRQ_PRIORITY 0 + +// GPIO14_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN4. +// Default: 0 +#define RTE_GPIO14_PIN4_IRQ_PRIORITY 0 + +// GPIO14_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN5. +// Default: 0 +#define RTE_GPIO14_PIN5_IRQ_PRIORITY 0 + +// GPIO14_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN6. +// Default: 0 +#define RTE_GPIO14_PIN6_IRQ_PRIORITY 0 + +// GPIO14_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN7. +// Default: 0 +#define RTE_GPIO14_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO14 + +// LPGPIO +// Configuration settings for Driver_LPGPIO in component ::Drivers:GPIO +#define RTE_LPGPIO 1 + +#if RTE_LPGPIO + +// LPGPIO_PIN0 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN0. +// Default: 0 +#define RTE_LPGPIO_PIN0_IRQ_PRIORITY 0 + +// LPGPIO_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN1 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN1. +// Default: 0 +#define RTE_LPGPIO_PIN1_IRQ_PRIORITY 0 + +// LPGPIO_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN2 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN2. +// Default: 0 +#define RTE_LPGPIO_PIN2_IRQ_PRIORITY 0 + +// LPGPIO_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN3 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN3. +// Default: 0 +#define RTE_LPGPIO_PIN3_IRQ_PRIORITY 0 + +// LPGPIO_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN4 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN4. +// Default: 0 +#define RTE_LPGPIO_PIN4_IRQ_PRIORITY 0 + +// LPGPIO_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN5 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN5. +// Default: 0 +#define RTE_LPGPIO_PIN5_IRQ_PRIORITY 0 + +// LPGPIO_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN6 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN6. +// Default: 0 +#define RTE_LPGPIO_PIN6_IRQ_PRIORITY 0 + +// LPGPIO_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN7 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN7. +// Default: 0 +#define RTE_LPGPIO_PIN7_IRQ_PRIORITY 0 + +// LPGPIO_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// LPGPIO + +// GPIO (general purpose input and output) + +// PDM(Pulse Density Modulation) +// PDM (Pulse density modulation) [Driver_PDM] +// Configuration settings for Driver_PDM in component ::Drivers:PDM +#define RTE_PDM 1 +#if RTE_PDM + +// PDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for PDM +// Default: ENABLE +#define RTE_PDM_DMA_ENABLE 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_PDM_DMA_IRQ_PRIORITY 0 + +// PDM IRQ priority <0-255> +// Defines Interrupt priority for PDM. +// Default: 0 +#define RTE_PDM_IRQ_PRIORITY 0 + +// PDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_PDM_FIFO_WATERMARK 5 + +#endif +// PDM (Pulse density modulation) [Driver_PDM] + +// PDM (Pulse density modulation) + +#if defined(RTSS_HE) +// LPPDM(Low Power Pulse Density Modulation) +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +// Configuration settings for Driver_LPPDM in component ::Drivers:LPPDM +#define RTE_LPPDM 1 + +#if RTE_LPPDM + +// LPPDM IRQ priority <0-255> +// Defines Interrupt priority for LPPDM. +// Default: 0 +#define RTE_LPPDM_IRQ_PRIORITY 0 + +// LPPDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_LPPDM_FIFO_WATERMARK 5 + +// LPPDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPPDM +// Default: ENABLE +#define RTE_LPPDM_DMA_ENABLE 0 +#if RTE_LPPDM_DMA_ENABLE + +// LPPDM DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPPDM. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPPDM_SELECT_DMA0 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_LPPDM_DMA_IRQ_PRIORITY 0 +#endif +#endif +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +#endif // defined(RTSS_HE) +// LPPDM (Low Power Pulse density modulation) + +// CANFD (Controller Area Network - Fast Mode) +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// Configuration settings for Driver_CANFD0 in component ::Drivers:CANFD +#define RTE_CANFD0 1 + +#if RTE_CANFD0 + +// CANFD0 IRQ priority <0-255> +// Defines Interrupt priority for CANFD0. +// Default: 0 +#define RTE_CANFD0_IRQ_PRIORITY 0 + +// CANFD0 Clock Source +// <0=> 38.4 MHz Clock +// <1=> 160 MHz Clock +// Defines Clock Source for CANFD0. +// Default: 160 MHz +#define RTE_CANFD0_CLK_SOURCE 1 + +// CANFD0 Clock Speed (Hz) <160000-80000000> +// Defines Clock Speed for CANFD0. +// Maximum Clock speed is 80MHz +// Recommended speeds with 160MHz clock source: 20MHz, 40MHz, 80MHz +// Default: 20MHz +#define RTE_CANFD0_CLK_SPEED 20000000 + +// CANFD0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for CANFD0 +// Default: DISABLE +#define RTE_CANFD0_BLOCKING_MODE_ENABLE 0 + +#endif +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// CANFD (Controller Area Network - Fast Mode) + +// SDC (Secure Digital Controller) +// SDC (Secure Digital Controller 0) [Driver_SDC0] +// Configuration settings for Driver_SDC0 in component ::Drivers:SDC +#define RTE_SDC 1 + +#if RTE_SDC + +// SDC BUS WIDTH SELECT +// <0=> BUS_WIDTH_1BIT +// <1=> BUS_WIDTH_4BIT +// Defines SDC0 size of bus width +// Default: BUS_WIDTH_4BIT +#define RTE_SDC_BUS_WIDTH 1 + +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz +// Default: 25MHz +#define RTE_SDC_CLOCK_SELECT 25000000 + +// SDC DMA SELECT +// <0=> SDMA +// <1=> ADMA2 +// Defines SDC0 DMA select +// Default: ADMA2 +#define RTE_SDC_DMA_SELECT 1 + +// SDC IRQ MODE SELECT +// <0=> Polling Mode +// <1=> IRQ Mode +// Defines SDC IRQ MODE select +// Default: IRQ MODE +#define RTE_SDC_IRQ_MODE_SELECT 1 + +// SDC IRQ priority <0-255> +// Defines SDC Interrupt priority +// Default: 0 +#define RTE_SDC_IRQ_PRI 0 + +// SDC WAKEUP IRQ priority <0-255> +// Defines SDC Wakeup Interrupt priority +// Default: 0 +#define RTE_SDC_WAKEUP_IRQ_PRI 0 + +#endif +// SDC0 (Secure Digital Controller 0) [Driver_SDC0] +// SDC (Secure Digital Controller) + +// ETH_MAC (Ethernet MAC) +// ETH_MAC (Ethernet MAC) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:ETH_MAC +#define RTE_ETH_MAC 1 + +#if RTE_ETH_MAC + +// ETH MAC IRQ priority <0-255> +// Defines ETH MAC Interrupt priority +// Default: 0 +#define RTE_ETH_MAC_IRQ_PRIORITY 0 + +#endif +// ETH (Ethernet MAC) [Driver_ETH_MAC0] +// ETH (Ethernet MAC) + +// Power Management (PM) +// Handle Spurious Wakeup +// <0=> Disable +// <1=> Enable +// define Handle Spurious Wakeup +// default: Enable +#define PM_HANDLE_SPURIOUS_WAKEUP 1 +// Power Management (PM) + +#endif /* __RTE_DEVICE_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h new file mode 100644 index 0000000..0ae4502 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h @@ -0,0 +1,197 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +#ifndef APP_MEM_REGIONS_H +#define APP_MEM_REGIONS_H + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// MRAM XIP Configuration +// ======================= +// RTSS HE Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0x80000000 +#define APP_MRAM_HE_BASE 0x80000000 +// RTSS HE Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_MRAM_HE_SIZE 0x00200000 +// RTSS HP Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_MRAM_HP_BASE 0x80200000 +// RTSS HP Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_MRAM_HP_SIZE 0x00200000 +// + +// MRAM User Configuration +// ======================= +// MRAM User Region +// User Base address <0x80000000-0x8057FFFF:8> +// Defines base address of MRAM user region +#define APP_MRAM_USER_BASE 0x80400000 + +// User Region size [bytes] <0x0-0x00580000:8> +// Defines size of MRAM user region +#define APP_MRAM_USER_SIZE 0x00180000 // 1.5 MB + +// Application executable MRAM region (before USER area) +#define APP_CODE_MRAM_SIZE (APP_MRAM_USER_BASE - APP_MRAM_HP_BASE) +// + +// RAM Configuration +// ======================= +// SRAM0 +// Base address <0x02000000-0x023FFFFF:8> +// Defines base address of SRAM0 memory region. +// Default: 0x02000000 +#define APP_SRAM0_BASE 0x02000000 +// Region size [bytes] <0x0-0x00400000:8> +// Defines size of SRAM0 memory region. +// Default: 0x00400000 +#define APP_SRAM0_SIZE 0x00400000 +// No zero initialize +// Excludes SRAM0 region from zero initialization. +#define APP_SRAM0_NOINIT 1 +// + +// SRAM1 +// Base address <0x08000000-0x0827FFFF:8> +// Defines base address of SRAM1 memory region. +// Default: 0x08000000 +#define APP_SRAM1_BASE 0x08000000 +// Region size [bytes] <0x0-0x00280000:8> +// Defines size of SRAM1 memory region. +// Default: 0x00280000 +#define APP_SRAM1_SIZE 0x00280000 +// No zero initialize +// Excludes SRAM1 region from zero initialization. +#define APP_SRAM1_NOINIT 1 +// + +// SRAM2 +// Base address <0x50000000-0x5003FFFF:8> +// Defines base address of SRAM2 memory region. +// Default: 0x50000000 +#define APP_SRAM2_BASE 0x50000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM2 memory region. +// Default: 0x00040000 +#define APP_SRAM2_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM2 region from zero initialization. +#define APP_SRAM2_NOINIT 0 +// + +// SRAM3 +// Base address <0x50800000-0x508FFFFF:8> +// Defines base address of SRAM3 memory region. +// Default: 0x50800000 +#define APP_SRAM3_BASE 0x50800000 +// Region size [bytes] <0x0-0x00100000:8> +// Defines size of SRAM3 memory region. +// Default: 0x00100000 +#define APP_SRAM3_SIZE 0x00100000 +// No zero initialize +// Excludes SRAM3 region from zero initialization. +#define APP_SRAM3_NOINIT 0 +// + +// SRAM4 +// Base address <0x58000000-0x5803FFFF:8> +// Defines base address of SRAM4 memory region. +// Default: 0x58000000 +#define APP_SRAM4_BASE 0x58000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM4 memory region. +// Default: 0x00040000 +#define APP_SRAM4_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM4 region from zero initialization. +#define APP_SRAM4_NOINIT 0 +// + +// SRAM5 +// Base address <0x58800000-0x5883FFFF:8> +// Defines base address of SRAM5 memory region. +// Default: 0x58800000 +#define APP_SRAM5_BASE 0x58800000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM5 memory region. +// Default: 0x00040000 +#define APP_SRAM5_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM5 region from zero initialization. +#define APP_SRAM5_NOINIT 0 +// + +// + +// Stack / Heap Configuration + +// RTSS HE +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HE_STACK_SIZE 0x00002000 +#define APP_HE_HEAP_SIZE 0x00004000 +// + +// RTSS HP +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HP_STACK_SIZE 0x00002000 +#define APP_HP_HEAP_SIZE 0x00004000 +// + +// + +// ITCM & DTCM Base Address +// ITCM Base address <0x0-0x400000:8> +// DTCM Base address <0x20000000-0x400000:8> +#define APP_ITCM_BASE 0x00000000 +#define APP_DTCM_BASE 0x20000000 +// + +// OSPI XIP Configuration +// ======================= +// Boot from OSPI +// Enable XIP from OSPI +#define APP_BOOT_OSPI_FLASH 0 +// RTSS HE Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0xC0000000 +#define APP_OSPI_FLASH_HE_BASE 0xC0000000 +// RTSS HE Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HE_SIZE 0x00200000 +// RTSS HP Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_OSPI_FLASH_HP_BASE 0xC0200000 +// RTSS HP Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HP_SIZE 0x00200000 +// + +#define APP_HE_ITCM_SIZE APP_SRAM4_SIZE +#define APP_HE_DTCM_SIZE APP_SRAM5_SIZE + +#define APP_HP_ITCM_SIZE APP_SRAM2_SIZE +#define APP_HP_DTCM_SIZE APP_SRAM3_SIZE + +#define TGU_BLOCK_SIZE 16384 + +#define __HAS_BULK_SRAM 1 + +#endif /* APP_MEM_REGIONS_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h.base@3.0.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h.base@3.0.0 new file mode 100644 index 0000000..0ae4502 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_mem_regions.h.base@3.0.0 @@ -0,0 +1,197 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +#ifndef APP_MEM_REGIONS_H +#define APP_MEM_REGIONS_H + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// MRAM XIP Configuration +// ======================= +// RTSS HE Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0x80000000 +#define APP_MRAM_HE_BASE 0x80000000 +// RTSS HE Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_MRAM_HE_SIZE 0x00200000 +// RTSS HP Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_MRAM_HP_BASE 0x80200000 +// RTSS HP Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_MRAM_HP_SIZE 0x00200000 +// + +// MRAM User Configuration +// ======================= +// MRAM User Region +// User Base address <0x80000000-0x8057FFFF:8> +// Defines base address of MRAM user region +#define APP_MRAM_USER_BASE 0x80400000 + +// User Region size [bytes] <0x0-0x00580000:8> +// Defines size of MRAM user region +#define APP_MRAM_USER_SIZE 0x00180000 // 1.5 MB + +// Application executable MRAM region (before USER area) +#define APP_CODE_MRAM_SIZE (APP_MRAM_USER_BASE - APP_MRAM_HP_BASE) +// + +// RAM Configuration +// ======================= +// SRAM0 +// Base address <0x02000000-0x023FFFFF:8> +// Defines base address of SRAM0 memory region. +// Default: 0x02000000 +#define APP_SRAM0_BASE 0x02000000 +// Region size [bytes] <0x0-0x00400000:8> +// Defines size of SRAM0 memory region. +// Default: 0x00400000 +#define APP_SRAM0_SIZE 0x00400000 +// No zero initialize +// Excludes SRAM0 region from zero initialization. +#define APP_SRAM0_NOINIT 1 +// + +// SRAM1 +// Base address <0x08000000-0x0827FFFF:8> +// Defines base address of SRAM1 memory region. +// Default: 0x08000000 +#define APP_SRAM1_BASE 0x08000000 +// Region size [bytes] <0x0-0x00280000:8> +// Defines size of SRAM1 memory region. +// Default: 0x00280000 +#define APP_SRAM1_SIZE 0x00280000 +// No zero initialize +// Excludes SRAM1 region from zero initialization. +#define APP_SRAM1_NOINIT 1 +// + +// SRAM2 +// Base address <0x50000000-0x5003FFFF:8> +// Defines base address of SRAM2 memory region. +// Default: 0x50000000 +#define APP_SRAM2_BASE 0x50000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM2 memory region. +// Default: 0x00040000 +#define APP_SRAM2_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM2 region from zero initialization. +#define APP_SRAM2_NOINIT 0 +// + +// SRAM3 +// Base address <0x50800000-0x508FFFFF:8> +// Defines base address of SRAM3 memory region. +// Default: 0x50800000 +#define APP_SRAM3_BASE 0x50800000 +// Region size [bytes] <0x0-0x00100000:8> +// Defines size of SRAM3 memory region. +// Default: 0x00100000 +#define APP_SRAM3_SIZE 0x00100000 +// No zero initialize +// Excludes SRAM3 region from zero initialization. +#define APP_SRAM3_NOINIT 0 +// + +// SRAM4 +// Base address <0x58000000-0x5803FFFF:8> +// Defines base address of SRAM4 memory region. +// Default: 0x58000000 +#define APP_SRAM4_BASE 0x58000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM4 memory region. +// Default: 0x00040000 +#define APP_SRAM4_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM4 region from zero initialization. +#define APP_SRAM4_NOINIT 0 +// + +// SRAM5 +// Base address <0x58800000-0x5883FFFF:8> +// Defines base address of SRAM5 memory region. +// Default: 0x58800000 +#define APP_SRAM5_BASE 0x58800000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM5 memory region. +// Default: 0x00040000 +#define APP_SRAM5_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM5 region from zero initialization. +#define APP_SRAM5_NOINIT 0 +// + +// + +// Stack / Heap Configuration + +// RTSS HE +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HE_STACK_SIZE 0x00002000 +#define APP_HE_HEAP_SIZE 0x00004000 +// + +// RTSS HP +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HP_STACK_SIZE 0x00002000 +#define APP_HP_HEAP_SIZE 0x00004000 +// + +// + +// ITCM & DTCM Base Address +// ITCM Base address <0x0-0x400000:8> +// DTCM Base address <0x20000000-0x400000:8> +#define APP_ITCM_BASE 0x00000000 +#define APP_DTCM_BASE 0x20000000 +// + +// OSPI XIP Configuration +// ======================= +// Boot from OSPI +// Enable XIP from OSPI +#define APP_BOOT_OSPI_FLASH 0 +// RTSS HE Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0xC0000000 +#define APP_OSPI_FLASH_HE_BASE 0xC0000000 +// RTSS HE Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HE_SIZE 0x00200000 +// RTSS HP Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_OSPI_FLASH_HP_BASE 0xC0200000 +// RTSS HP Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HP_SIZE 0x00200000 +// + +#define APP_HE_ITCM_SIZE APP_SRAM4_SIZE +#define APP_HE_DTCM_SIZE APP_SRAM5_SIZE + +#define APP_HP_ITCM_SIZE APP_SRAM2_SIZE +#define APP_HP_DTCM_SIZE APP_SRAM3_SIZE + +#define TGU_BLOCK_SIZE 16384 + +#define __HAS_BULK_SRAM 1 + +#endif /* APP_MEM_REGIONS_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h new file mode 100644 index 0000000..cc156f1 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h @@ -0,0 +1,1288 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_TZ_H +#define APP_TZ_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &Image$$NS_REGION_0$$Base +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_start; +#define SAU_INIT_START0 (uint32_t) &__ns_region_0_start +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &NS_REGION_0$$Base +#else +#error Unknown compiler. +#endif + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0_PAD$$Base; +#define SAU_INIT_END0 ((uint32_t) &Image$$NS_REGION_0_PAD$$Base - 1) +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_end; +#define SAU_INIT_END0 ((uint32_t) &__ns_region_0_end - 1) +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Limit; +#define SAU_INIT_END0 ((uint32_t) &NS_REGION_0$$Limit - 1) +#else +#error Unknown compiler. +#endif + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 0 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + do { \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U; \ + } while (0) + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup(void) +{ + +#if defined(__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + +#if defined(SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); +#endif + +#if defined(SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); +#endif + +#if defined(SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); +#endif + +#if defined(SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); +#endif + +#if defined(SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); +#endif + +#if defined(SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); +#endif + +#if defined(SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); +#endif + +#if defined(SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); +#endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +#if defined(SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk); +#endif + +#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = + (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); +#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + +#if (((defined(__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = + (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = + (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); +#endif + +#if defined(NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; +#endif + +#if defined(NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; +#endif + +#if defined(NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; +#endif + +#if defined(NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; +#endif + +#if defined(NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; +#endif + +#if defined(NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; +#endif + +#if defined(NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; +#endif + +#if defined(NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; +#endif + +#if defined(NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; +#endif + +#if defined(NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; +#endif + +#if defined(NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; +#endif + +#if defined(NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; +#endif + +#if defined(NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; +#endif + +#if defined(NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; +#endif + +#if defined(NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; +#endif + +#if defined(NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; +#endif + + /* repeat this for all possible ITNS elements */ +} + +#endif /* APP_TZ_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h.base@2.1.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h.base@2.1.0 new file mode 100644 index 0000000..cc156f1 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/app_tz.h.base@2.1.0 @@ -0,0 +1,1288 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_TZ_H +#define APP_TZ_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &Image$$NS_REGION_0$$Base +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_start; +#define SAU_INIT_START0 (uint32_t) &__ns_region_0_start +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &NS_REGION_0$$Base +#else +#error Unknown compiler. +#endif + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0_PAD$$Base; +#define SAU_INIT_END0 ((uint32_t) &Image$$NS_REGION_0_PAD$$Base - 1) +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_end; +#define SAU_INIT_END0 ((uint32_t) &__ns_region_0_end - 1) +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Limit; +#define SAU_INIT_END0 ((uint32_t) &NS_REGION_0$$Limit - 1) +#else +#error Unknown compiler. +#endif + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 0 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + do { \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U; \ + } while (0) + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup(void) +{ + +#if defined(__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + +#if defined(SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); +#endif + +#if defined(SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); +#endif + +#if defined(SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); +#endif + +#if defined(SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); +#endif + +#if defined(SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); +#endif + +#if defined(SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); +#endif + +#if defined(SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); +#endif + +#if defined(SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); +#endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +#if defined(SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk); +#endif + +#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = + (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); +#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + +#if (((defined(__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = + (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = + (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); +#endif + +#if defined(NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; +#endif + +#if defined(NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; +#endif + +#if defined(NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; +#endif + +#if defined(NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; +#endif + +#if defined(NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; +#endif + +#if defined(NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; +#endif + +#if defined(NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; +#endif + +#if defined(NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; +#endif + +#if defined(NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; +#endif + +#if defined(NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; +#endif + +#if defined(NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; +#endif + +#if defined(NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; +#endif + +#if defined(NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; +#endif + +#if defined(NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; +#endif + +#if defined(NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; +#endif + +#if defined(NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; +#endif + + /* repeat this for all possible ITNS elements */ +} + +#endif /* APP_TZ_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h new file mode 100644 index 0000000..7950fe8 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h @@ -0,0 +1,43 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __CORE_CONFIG_H +#define __CORE_CONFIG_H + +// Map Global to Local address of TCM Alias +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable this to return aliased address in GlobalToLocal function +// Default: 0 +#define CONFIG_MAP_GLOBAL_TO_LOCAL_TCM_ALIAS 0 + +// Prefetch Control +// Prefetch Control values for Performance Improvement + +// Maximum Outstanding Line-fills <1-6> +// Defines Maximum Outstanding line-fills issued on AXI +// Default: 5 +#define MEMSYSCTL_PFCR_MAX_OS_DEFAULT_VALUE 5 + +// Maximum Look Ahead Distance <0-6> +// Defines Maximum Look Ahead distance +// Default: 6 +#define MEMSYSCTL_PFCR_MAX_LA_DEFAULT_VALUE 6 + +// Minimum Look Ahead Distance <0-6> +// Defines Minimum Look Ahead distance +// Default: 2 +#define MEMSYSCTL_PFCR_MIN_LA_DEFAULT_VALUE 2 + +// Prefetch Control + +#endif /* __CORE_CONFIG_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h.base@2.1.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h.base@2.1.0 new file mode 100644 index 0000000..7950fe8 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/core_config.h.base@2.1.0 @@ -0,0 +1,43 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __CORE_CONFIG_H +#define __CORE_CONFIG_H + +// Map Global to Local address of TCM Alias +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable this to return aliased address in GlobalToLocal function +// Default: 0 +#define CONFIG_MAP_GLOBAL_TO_LOCAL_TCM_ALIAS 0 + +// Prefetch Control +// Prefetch Control values for Performance Improvement + +// Maximum Outstanding Line-fills <1-6> +// Defines Maximum Outstanding line-fills issued on AXI +// Default: 5 +#define MEMSYSCTL_PFCR_MAX_OS_DEFAULT_VALUE 5 + +// Maximum Look Ahead Distance <0-6> +// Defines Maximum Look Ahead distance +// Default: 6 +#define MEMSYSCTL_PFCR_MAX_LA_DEFAULT_VALUE 6 + +// Minimum Look Ahead Distance <0-6> +// Defines Minimum Look Ahead distance +// Default: 2 +#define MEMSYSCTL_PFCR_MIN_LA_DEFAULT_VALUE 2 + +// Prefetch Control + +#endif /* __CORE_CONFIG_H */ diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct new file mode 100644 index 0000000..ecf1f17 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE APP_CODE_MRAM_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + + MRAM_USER APP_MRAM_USER_BASE APP_MRAM_USER_SIZE { + * (.mram_user) + * (.mram_user_bss) + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct.base@2.2.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct.base@2.2.0 new file mode 100644 index 0000000..ecf1f17 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_mram.sct.base@2.2.0 @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE APP_CODE_MRAM_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + + MRAM_USER APP_MRAM_USER_BASE APP_MRAM_USER_SIZE { + * (.mram_user) + * (.mram_user_bss) + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct new file mode 100644 index 0000000..f0a07a0 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct @@ -0,0 +1,114 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_OSPI_FLASH_HP_BASE +#define __ROM_SIZE APP_OSPI_FLASH_HP_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 new file mode 100644 index 0000000..f0a07a0 --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 @@ -0,0 +1,114 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_OSPI_FLASH_HP_BASE +#define __ROM_SIZE APP_OSPI_FLASH_HP_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct new file mode 100644 index 0000000..6521f7b --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct @@ -0,0 +1,109 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_ITCM_BASE +#define __ROM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + * (.rodata.usbd0_device_descriptor) + * (.rodata.usbd0_device_qualifier_hs) + * (.rodata.usbd0_config_descriptor_hs) + * (.rodata.usbd0_other_speed_config_descriptor_hs) + * (.rodata.usbd0_string_descriptor) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } +#endif +} diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct.base@2.1.0 b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct.base@2.1.0 new file mode 100644 index 0000000..6521f7b --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/linker_ac6_tcm.sct.base@2.1.0 @@ -0,0 +1,109 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_ITCM_BASE +#define __ROM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + * (.rodata.usbd0_device_descriptor) + * (.rodata.usbd0_device_qualifier_hs) + * (.rodata.usbd0_config_descriptor_hs) + * (.rodata.usbd0_other_speed_config_descriptor_hs) + * (.rodata.usbd0_string_descriptor) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } +#endif +} diff --git a/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/regions_AppKit-E7-AIML.h b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/regions_AppKit-E7-AIML.h new file mode 100644 index 0000000..44948fd --- /dev/null +++ b/board/AppKit-E7/RTE/Device/AE722F80F55D5LS_M55_HP/regions_AppKit-E7-AIML.h @@ -0,0 +1,113 @@ +#ifndef REGIONS_APPKIT_E7_AIML_H +#define REGIONS_APPKIT_E7_AIML_H + + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// Auto-generated using information from packs +// Device Family Pack (DFP): AlifSemiconductor::Ensemble@2.2.0 +// Board Support Pack (BSP): AlifSemiconductor::Ensemble@2.2.0 + +// ROM Configuration +// ======================= +// __ROM0 (is rx memory: MRAM from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x80000000 +// Contains Startup and Vector Table +#define __ROM0_BASE 0x80000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00580000 +#define __ROM0_SIZE 0x00580000 +// + +// __ROM1 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __ROM1_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM1_SIZE 0x0 +// + +// __ROM2 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __ROM2_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM2_SIZE 0x0 +// + +// __ROM3 (unused) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +#define __ROM3_BASE 0x0 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM3_SIZE 0x0 +// + +// + +// RAM Configuration +// ======================= +// __RAM0 (is rwx memory: SRAM0 from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x02000000 +// Contains uninitialized RAM, Stack, and Heap +#define __RAM0_BASE 0x02000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00400000 +#define __RAM0_SIZE 0x00400000 +// + +// __RAM1 (is rwx memory: SRAM1 from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x08000000 +#define __RAM1_BASE 0x08000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00280000 +#define __RAM1_SIZE 0x00280000 +// + +// __RAM2 (is rwx memory: SRAM2 from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x50000000 +#define __RAM2_BASE 0x50000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00040000 +#define __RAM2_SIZE 0x00040000 +// + +// __RAM3 (is rwx memory: SRAM3 from DFP) +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. Default: 0x50800000 +#define __RAM3_BASE 0x50800000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. Default: 0x00100000 +#define __RAM3_SIZE 0x00100000 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 +// + +// Resources that are not allocated to linker regions +// rwx RAM: SRAM4 from DFP: BASE: 0x58000000 SIZE: 0x00040000 +// rwx RAM: SRAM5 from DFP: BASE: 0x58800000 SIZE: 0x00040000 +// rwx RAM: SRAM6_A from DFP: BASE: 0x62000000 SIZE: 0x00100000 +// rwx RAM: SRAM6_B from DFP: BASE: 0x62400000 SIZE: 0x00100000 +// rwx RAM: SRAM7 from DFP: BASE: 0x63000000 SIZE: 0x00080000 +// rwx RAM: SRAM8 from DFP: BASE: 0x63200000 SIZE: 0x00200000 +// rwx RAM: SRAM9 from DFP: BASE: 0x60000000 SIZE: 0x000C0000 +// rwx RAM: ITCM_HP from DFP: BASE: 0x00000000 SIZE: 0x00040000 Pname: M55_HP +// rwx RAM: DTCM_HP from DFP: BASE: 0x20000000 SIZE: 0x00100000 Pname: M55_HP + + +#endif /* REGIONS_APPKIT_E7_AIML_H */ diff --git a/board/AppKit-E7/RTE/SDS/sds_config.h b/board/AppKit-E7/RTE/SDS/sds_config.h new file mode 100644 index 0000000..ecd50a5 --- /dev/null +++ b/board/AppKit-E7/RTE/SDS/sds_config.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2025-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: sds_config.h + * Purpose: SDS configuration options + * Rev.: V3.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// SDS System Configuration + +// Maximum concurrent streams <1-31> +// Default: 16 +#define SDS_MAX_STREAMS 16U + +// Internal buffer size for I/O transfers +// Default: 8192 +#define SDS_BUF_SIZE 8192U + +// + +//------------- <<< end of configuration section >>> --------------------------- + +// SDS system thread stack size +#define SDS_THREAD_STACK_SIZE 1024 + +// SDS system thread priority +#define SDS_THREAD_PRIORITY osPriorityNormal1 + +// SDS stream open timeout in kernel ticks +#define SDS_OPEN_TIMEOUT 3000U + +// SDS stream close timeout in kernel ticks +#define SDS_CLOSE_TIMEOUT 3000U + +// Optimal I/O transfer size (read/write) +// Default: 8192 +// Select a value appropriate for the underlying I/O interface (e.g., socket, USART, VCOM, file system) +// to ensure efficient read/write performance +#define SDS_IO_TRANSFER_SIZE 8192U diff --git a/board/AppKit-E7/RTE/SDS/sds_config.h.base@3.1.0 b/board/AppKit-E7/RTE/SDS/sds_config.h.base@3.1.0 new file mode 100644 index 0000000..ecd50a5 --- /dev/null +++ b/board/AppKit-E7/RTE/SDS/sds_config.h.base@3.1.0 @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2025-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: sds_config.h + * Purpose: SDS configuration options + * Rev.: V3.1.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// SDS System Configuration + +// Maximum concurrent streams <1-31> +// Default: 16 +#define SDS_MAX_STREAMS 16U + +// Internal buffer size for I/O transfers +// Default: 8192 +#define SDS_BUF_SIZE 8192U + +// + +//------------- <<< end of configuration section >>> --------------------------- + +// SDS system thread stack size +#define SDS_THREAD_STACK_SIZE 1024 + +// SDS system thread priority +#define SDS_THREAD_PRIORITY osPriorityNormal1 + +// SDS stream open timeout in kernel ticks +#define SDS_OPEN_TIMEOUT 3000U + +// SDS stream close timeout in kernel ticks +#define SDS_CLOSE_TIMEOUT 3000U + +// Optimal I/O transfer size (read/write) +// Default: 8192 +// Select a value appropriate for the underlying I/O interface (e.g., socket, USART, VCOM, file system) +// to ensure efficient read/write performance +#define SDS_IO_TRANSFER_SIZE 8192U diff --git a/board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h b/board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h new file mode 100644 index 0000000..2441362 --- /dev/null +++ b/board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: sdsio_client_usb_mdk_config.h + * Purpose: SDSIO via USB (Keil::USB:Device:Custom) configuration options + * Rev.: V3.0.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// SDSIO via USB (Keil::USB:Device:Custom Class) +// SDSIO using SDSIO-Client to communicate with SDSIO-Server via the USB Interface + +// USB Device index <0-3> +// Index of USB Device +// Default: 0 +#define SDSIO_USB_DEVICE_INDEX 0 + +// USB Device Custom Class instance <0-3> +// Index of Custom Class +// Default: 0 +#define SDSIO_USB_INSTANCE 0 + +// USB transfer timeout +// USB transfer timeout in kernel ticks +// Default: 3000 +#define SDSIO_USB_TIMEOUT 3000U + +// USB Bulk OUT buffer size +// Size of the internal USB Bulk OUT buffer in bytes +// Must be a multiple of endpoint maximum packet size (64 bytes for full speed, 512 bytes for high speed) +// Default: 8192 +#define SDSIO_USB_BULK_OUT_BUF_SIZE 8192U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h.base@3.0.0 b/board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h.base@3.0.0 new file mode 100644 index 0000000..2441362 --- /dev/null +++ b/board/AppKit-E7/RTE/SDS/sdsio_client_usb_mdk_config.h.base@3.0.0 @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2025-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: sdsio_client_usb_mdk_config.h + * Purpose: SDSIO via USB (Keil::USB:Device:Custom) configuration options + * Rev.: V3.0.0 + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// SDSIO via USB (Keil::USB:Device:Custom Class) +// SDSIO using SDSIO-Client to communicate with SDSIO-Server via the USB Interface + +// USB Device index <0-3> +// Index of USB Device +// Default: 0 +#define SDSIO_USB_DEVICE_INDEX 0 + +// USB Device Custom Class instance <0-3> +// Index of Custom Class +// Default: 0 +#define SDSIO_USB_INSTANCE 0 + +// USB transfer timeout +// USB transfer timeout in kernel ticks +// Default: 3000 +#define SDSIO_USB_TIMEOUT 3000U + +// USB Bulk OUT buffer size +// Size of the internal USB Bulk OUT buffer in bytes +// Must be a multiple of endpoint maximum packet size (64 bytes for full speed, 512 bytes for high speed) +// Default: 8192 +#define SDSIO_USB_BULK_OUT_BUF_SIZE 8192U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/board/AppKit-E7/RTE/USB/USBD_Config_0.h b/board/AppKit-E7/RTE/USB/USBD_Config_0.h new file mode 100644 index 0000000..5d1addb --- /dev/null +++ b/board/AppKit-E7/RTE/USB/USBD_Config_0.h @@ -0,0 +1,150 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Device + * Copyright (c) 2004-2024 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBD_Config_0.h + * Purpose: USB Device Configuration + * Rev.: V8.0.0 + *------------------------------------------------------------------------------ + * Use the following configuration settings in the Device Class configuration + * files to assign a Device Class to this USB Device 0. + * + * Configuration Setting Value + * --------------------- ----- + * Assign Device Class to USB Device # = 0 + *----------------------------------------------------------------------------*/ + +#ifdef CMSIS_target_header +#include CMSIS_target_header +#endif + +#ifndef CMSIS_DRIVER_USBD +#define CMSIS_DRIVER_USBD 0 +#endif +#ifndef CMSIS_DRIVER_USBD_HS +#define CMSIS_DRIVER_USBD_HS 0 +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device 0 +// Connect to hardware via Driver_USBD# +// Select driver control block for hardware interface. +#define USBD0_PORT CMSIS_DRIVER_USBD + +// High-speed +// Enable High-speed functionality (if device supports it). +#define USBD0_HS CMSIS_DRIVER_USBD_HS + +// Device Settings +// These settings are used to create the Device Descriptor +// Max Endpoint 0 Packet Size +// Maximum packet size for Endpoint 0 (bMaxPacketSize0). +// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes +#define USBD0_MAX_PACKET0 64 + +// Vendor ID <0x0000-0xFFFF> +// Vendor ID assigned by USB-IF (idVendor). +#define USBD0_DEV_DESC_IDVENDOR 0xC251 + +// Product ID <0x0000-0xFFFF> +// Product ID assigned by manufacturer (idProduct). +#define USBD0_DEV_DESC_IDPRODUCT 0x8007 + +// Device Release Number <0x0000-0xFFFF> +// Device Release Number in binary-coded decimal (bcdDevice). +#define USBD0_DEV_DESC_BCDDEVICE 0x0100 + +// + +// Configuration Settings +// These settings are used to create the Configuration Descriptor. +// Power +// Default Power Setting (D6: of bmAttributes). +// <0=>Bus-powered +// <1=>Self-powered +// Remote Wakeup +// Configuration support for Remote Wakeup (D5: of bmAttributes). +#define USBD0_CFG_DESC_BMATTRIBUTES 0x80 + +// Maximum Power Consumption (in mA) <0-510><#/2> +// Maximum Power Consumption of USB Device from bus in this +// specific configuration when device is fully operational (bMaxPower). +#define USBD0_CFG_DESC_BMAXPOWER 250 + +// + +// String Settings +// These settings are used to create the String Descriptor. +// Language ID <0x0000-0xFCFF> +// English (United States) = 0x0409. +#define USBD0_STR_DESC_LANGID 0x0409 + +// Manufacturer String +// String Descriptor describing Manufacturer. +#define USBD0_STR_DESC_MAN_RAW "Keil Software" + +// Product String +// String Descriptor describing Product. +#define USBD0_STR_DESC_PROD_RAW "SDSIO-Client" + +// Serial Number String +// Enable Serial Number String. +// If disabled Serial Number String will not be assigned to USB Device. +#define USBD0_STR_DESC_SER_EN 1 + +// Default value +// Default device's Serial Number String. +#define USBD0_STR_DESC_SER_RAW "0001A0000000" + +// Maximum Length (in characters) <0-126> +// Specifies the maximum number of Serial Number String characters that can be set at run-time. +// Maximum value is 126. Use value 0 to disable RAM allocation for string. +#define USBD0_STR_DESC_SER_MAX_LEN 16 + +// +// + +// Microsoft OS Descriptors Settings +// These settings are used to create the Microsoft OS Descriptors. +// OS String +// Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors. +#define USBD0_OS_DESC_EN 1 + +// Vendor Code <0x01-0xFF> +// Specifies Vendor Code used to retrieve OS Feature Descriptors. +#define USBD0_OS_DESC_VENDOR_CODE 0x01 + +// +// + +// Control Transfer Buffer Size <64-65536:64> +// Specifies size of buffer used for Control Transfers. +// It should be at least as big as maximum packet size for Endpoint 0. +#define USBD0_EP0_BUF_SIZE 128 + +// Data Buffers +// Locate +// Specifies if the USB data buffers are located in a specific memory +// (via the linker script). +#define USBD0_BUF_MEM_LOCATE 1 + +// Section Name +// Specifies the section name for the USB data buffers +// (for positioning via the linker script). +#define USBD0_BUF_MEM_SECTION_NAME ".driver.usbd0" + +// +// + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <64-65536> +#define USBD0_CORE_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal + +// +// diff --git a/board/AppKit-E7/RTE/USB/USBD_Config_0.h.base@8.0.0 b/board/AppKit-E7/RTE/USB/USBD_Config_0.h.base@8.0.0 new file mode 100644 index 0000000..876dceb --- /dev/null +++ b/board/AppKit-E7/RTE/USB/USBD_Config_0.h.base@8.0.0 @@ -0,0 +1,139 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Device + * Copyright (c) 2004-2024 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBD_Config_0.h + * Purpose: USB Device Configuration + * Rev.: V8.0.0 + *------------------------------------------------------------------------------ + * Use the following configuration settings in the Device Class configuration + * files to assign a Device Class to this USB Device 0. + * + * Configuration Setting Value + * --------------------- ----- + * Assign Device Class to USB Device # = 0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device 0 +// Connect to hardware via Driver_USBD# +// Select driver control block for hardware interface. +#define USBD0_PORT 0 + +// High-speed +// Enable High-speed functionality (if device supports it). +#define USBD0_HS 0 + +// Device Settings +// These settings are used to create the Device Descriptor +// Max Endpoint 0 Packet Size +// Maximum packet size for Endpoint 0 (bMaxPacketSize0). +// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes +#define USBD0_MAX_PACKET0 8 + +// Vendor ID <0x0000-0xFFFF> +// Vendor ID assigned by USB-IF (idVendor). +#define USBD0_DEV_DESC_IDVENDOR 0xC251 + +// Product ID <0x0000-0xFFFF> +// Product ID assigned by manufacturer (idProduct). +#define USBD0_DEV_DESC_IDPRODUCT 0x0000 + +// Device Release Number <0x0000-0xFFFF> +// Device Release Number in binary-coded decimal (bcdDevice). +#define USBD0_DEV_DESC_BCDDEVICE 0x0100 + +// + +// Configuration Settings +// These settings are used to create the Configuration Descriptor. +// Power +// Default Power Setting (D6: of bmAttributes). +// <0=>Bus-powered +// <1=>Self-powered +// Remote Wakeup +// Configuration support for Remote Wakeup (D5: of bmAttributes). +#define USBD0_CFG_DESC_BMATTRIBUTES 0x80 + +// Maximum Power Consumption (in mA) <0-510><#/2> +// Maximum Power Consumption of USB Device from bus in this +// specific configuration when device is fully operational (bMaxPower). +#define USBD0_CFG_DESC_BMAXPOWER 250 + +// + +// String Settings +// These settings are used to create the String Descriptor. +// Language ID <0x0000-0xFCFF> +// English (United States) = 0x0409. +#define USBD0_STR_DESC_LANGID 0x0409 + +// Manufacturer String +// String Descriptor describing Manufacturer. +#define USBD0_STR_DESC_MAN_RAW "Keil Software" + +// Product String +// String Descriptor describing Product. +#define USBD0_STR_DESC_PROD_RAW "Keil USB Device 0" + +// Serial Number String +// Enable Serial Number String. +// If disabled Serial Number String will not be assigned to USB Device. +#define USBD0_STR_DESC_SER_EN 1 + +// Default value +// Default device's Serial Number String. +#define USBD0_STR_DESC_SER_RAW "0001A0000000" + +// Maximum Length (in characters) <0-126> +// Specifies the maximum number of Serial Number String characters that can be set at run-time. +// Maximum value is 126. Use value 0 to disable RAM allocation for string. +#define USBD0_STR_DESC_SER_MAX_LEN 16 + +// +// + +// Microsoft OS Descriptors Settings +// These settings are used to create the Microsoft OS Descriptors. +// OS String +// Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors. +#define USBD0_OS_DESC_EN 1 + +// Vendor Code <0x01-0xFF> +// Specifies Vendor Code used to retrieve OS Feature Descriptors. +#define USBD0_OS_DESC_VENDOR_CODE 0x01 + +// +// + +// Control Transfer Buffer Size <64-65536:64> +// Specifies size of buffer used for Control Transfers. +// It should be at least as big as maximum packet size for Endpoint 0. +#define USBD0_EP0_BUF_SIZE 128 + +// Data Buffers +// Locate +// Specifies if the USB data buffers are located in a specific memory +// (via the linker script). +#define USBD0_BUF_MEM_LOCATE 0 + +// Section Name +// Specifies the section name for the USB data buffers +// (for positioning via the linker script). +#define USBD0_BUF_MEM_SECTION_NAME ".driver.usbd0" + +// +// + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <64-65536> +#define USBD0_CORE_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal + +// +// diff --git a/board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h b/board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h new file mode 100644 index 0000000..375c08e --- /dev/null +++ b/board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h @@ -0,0 +1,3772 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Device + * Copyright (c) 2004-2024 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBD_Config_CustomClass_0.h + * Purpose: USB Device Custom Class Configuration + * Rev.: V5.3.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device: Custom Class 0 +// Custom Class can be used to make support for Standard or Vendor-Specific Class +// Assign Device Class to USB Device # <0-3> +// Select USB Device that is used for this Device Class instance +#define USBD_CUSTOM_CLASS0_DEV 0 + +// Interface Association +// Used for grouping of multiple interfaces to a single class. +#define USBD_CUSTOM_CLASS0_IAD_EN 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IAD_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL 0x00 + +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF0_EN 1 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF0_NUM 0 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF0_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF0_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP0_EN 1 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP1_EN 1 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 0. +#define USBD_CUSTOM_CLASS0_IF0_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF0_STR_RAW "USB_CUSTOM_CLASS0_IF0" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN 1 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN 1 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF1_EN 0 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF1_NUM 1 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF1_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF1_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP0_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP1_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 1. +#define USBD_CUSTOM_CLASS0_IF1_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF1_STR_RAW "USB_CUSTOM_CLASS0_IF1" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN 0 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF2_EN 0 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF2_NUM 2 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF2_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF2_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP0_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP1_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 2. +#define USBD_CUSTOM_CLASS0_IF2_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF2_STR_RAW "USB_CUSTOM_CLASS0_IF2" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN 0 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF3_EN 0 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF3_NUM 3 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF3_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF3_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP0_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP1_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 3. +#define USBD_CUSTOM_CLASS0_IF3_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF3_STR_RAW "USB_CUSTOM_CLASS0_IF3" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN 0 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Endpoint 1 Thread Stack Size <64-65536> +// This setting is used if Endpoint 1 is enabled. +#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE 512 + +// Endpoint 1 Thread Priority +#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 2 Thread Stack Size <64-65536> +// This setting is used if Endpoint 2 is enabled. +#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE 512 + +// Endpoint 2 Thread Priority +#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 3 Thread Stack Size <64-65536> +// This setting is used if Endpoint 3 is enabled. +#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE 512 + +// Endpoint 3 Thread Priority +#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 4 Thread Stack Size <64-65536> +// This setting is used if Endpoint 4 is enabled. +#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE 512 + +// Endpoint 4 Thread Priority +#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 5 Thread Stack Size <64-65536> +// This setting is used if Endpoint 5 is enabled. +#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE 512 + +// Endpoint 5 Thread Priority +#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 6 Thread Stack Size <64-65536> +// This setting is used if Endpoint 6 is enabled. +#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE 512 + +// Endpoint 6 Thread Priority +#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 7 Thread Stack Size <64-65536> +// This setting is used if Endpoint 7 is enabled. +#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE 512 + +// Endpoint 7 Thread Priority +#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 8 Thread Stack Size <64-65536> +// This setting is used if Endpoint 8 is enabled. +#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE 512 + +// Endpoint 8 Thread Priority +#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 9 Thread Stack Size <64-65536> +// This setting is used if Endpoint 9 is enabled. +#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE 512 + +// Endpoint 9 Thread Priority +#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 10 Thread Stack Size <64-65536> +// This setting is used if Endpoint 10 is enabled. +#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE 512 + +// Endpoint 10 Thread Priority +#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 11 Thread Stack Size <64-65536> +// This setting is used if Endpoint 11 is enabled. +#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE 512 + +// Endpoint 11 Thread Priority +#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 12 Thread Stack Size <64-65536> +// This setting is used if Endpoint 12 is enabled. +#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE 512 + +// Endpoint 12 Thread Priority +#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 13 Thread Stack Size <64-65536> +// This setting is used if Endpoint 13 is enabled. +#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE 512 + +// Endpoint 13 Thread Priority +#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 14 Thread Stack Size <64-65536> +// This setting is used if Endpoint 14 is enabled. +#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE 512 + +// Endpoint 14 Thread Priority +#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 15 Thread Stack Size <64-65536> +// This setting is used if Endpoint 15 is enabled. +#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE 512 + +// Endpoint 15 Thread Priority +#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY osPriorityAboveNormal + +// +// diff --git a/board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h.base@5.3.1 b/board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h.base@5.3.1 new file mode 100644 index 0000000..80d8b05 --- /dev/null +++ b/board/AppKit-E7/RTE/USB/USBD_Config_CustomClass_0.h.base@5.3.1 @@ -0,0 +1,3772 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Device + * Copyright (c) 2004-2024 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBD_Config_CustomClass_0.h + * Purpose: USB Device Custom Class Configuration + * Rev.: V5.3.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device: Custom Class 0 +// Custom Class can be used to make support for Standard or Vendor-Specific Class +// Assign Device Class to USB Device # <0-3> +// Select USB Device that is used for this Device Class instance +#define USBD_CUSTOM_CLASS0_DEV 0 + +// Interface Association +// Used for grouping of multiple interfaces to a single class. +#define USBD_CUSTOM_CLASS0_IAD_EN 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IAD_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IAD_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IAD_PROTOCOL 0x00 + +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF0_EN 1 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF0_NUM 0 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF0_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF0_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF0_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF0_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP0_EN 1 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP1_EN 1 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF0_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF0_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF0_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF0_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 0. +#define USBD_CUSTOM_CLASS0_IF0_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF0_STR_RAW "USB_CUSTOM_CLASS0_IF0" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID_EN 1 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_EN 1 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF0_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF1_EN 0 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF1_NUM 1 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF1_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF1_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF1_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF1_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP0_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP1_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF1_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF1_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF1_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF1_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 1. +#define USBD_CUSTOM_CLASS0_IF1_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF1_STR_RAW "USB_CUSTOM_CLASS0_IF1" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID_EN 0 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF1_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF2_EN 0 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF2_NUM 2 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF2_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF2_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF2_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF2_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP0_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP1_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF2_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF2_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF2_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF2_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 2. +#define USBD_CUSTOM_CLASS0_IF2_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF2_STR_RAW "USB_CUSTOM_CLASS0_IF2" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID_EN 0 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF2_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// Interface +#define USBD_CUSTOM_CLASS0_IF3_EN 0 + +// Interface Settings +// The Interface Settings are used to create the Interface Descriptor. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about the Interface Descriptor. + +// Interface Number <0-255> +// Defines the value for bInterfaceNumber +// Each USB Device Interface has a sequential Interface Number starting with 0. +// Several Interfaces may have the same Interface Number; in this case the value +// of Alternate Setting is used to differ between the Interfaces. For a +// composite device the Interface Numbers of the custom classes must be contiguous. +#define USBD_CUSTOM_CLASS0_IF3_NUM 3 + +// Alternate Setting <0=>0 <1=>1 <2=>2 <3=>3 +// Defines the value for bAlternateSetting +// A sequential number starting with 0 to identify the Interface Descriptors +// that share the same value for Interface Number. +#define USBD_CUSTOM_CLASS0_IF3_ALT 0 + +// Class Code +// Class Codes are defined by USB-IF. For more information refer to +// https://www.usb.org/defined-class-codes. +// <0x00=>0x00: Indicate a Null Class Code triple +// <0x01=>0x01: Audio +// <0x02=>0x02: Communications and CDC Control +// <0x03=>0x03: HID (Human Interface Device) +// <0x05=>0x05: Physical +// <0x06=>0x06: Image +// <0x07=>0x07: Printer +// <0x08=>0x08: Mass Storage +// <0x0A=>0x0A: CDC-Data +// <0x0B=>0x0B: Smart Card +// <0x0D=>0x0D: Content Security +// <0x0E=>0x0E: Video +// <0x0F=>0x0F: Personal Healthcare +// <0x10=>0x10: Audio/Video Devices +// <0xDC=>0xDC: Diagnostic Device +// <0xE0=>0xE0: Wireless Controller +// <0xEF=>0xEF: Miscellaneous +// <0xFE=>0xFE: Application Specific +// <0xFF=>0xFF: Vendor Specific +#define USBD_CUSTOM_CLASS0_IF3_CLASS 0xFF + +// Subclass Code <0x00-0xFF> +// The possible values depend on the Class Code: +// Class Code 0x00: Subclass Code must be 0 +// Class Code 0x01 .. 0xFE: Subclass Code is defined by USB-IF +// Class Code 0xFF: Subclass Code can be 0x00 .. 0xFF +#define USBD_CUSTOM_CLASS0_IF3_SUBCLASS 0x00 + +// Protocol Code <0x00-0xFF> +// The Protocol Code value defines the protocol used on this interface: +// Protocol Code 0x00: class-specific protocol not used +// Protocol Code 0x01 .. 0xFE: class-specific protocol used +// Protocol Code 0xFF: vendor-specific protocol used +#define USBD_CUSTOM_CLASS0_IF3_PROTOCOL 0x00 + +// + +// Endpoint Settings +// Following settings are used to create the Endpoint Descriptors. +// Refer to USB - USB Concepts - USB Descriptor in the MDK Components +// User's Guide for more information about Endpoint Descriptors. + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP0_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP0_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP0_BENDPOINTADDRESS 0x01 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP0_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP0_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP1_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP1_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP1_BENDPOINTADDRESS 0x81 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP1_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP1_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP2_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP2_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP2_BENDPOINTADDRESS 0x02 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP2_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP2_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP3_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP3_BMATTRIBUTES 0x03 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP3_BENDPOINTADDRESS 0x82 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP3_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP3_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP4_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP4_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP4_BENDPOINTADDRESS 0x03 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP4_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP4_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP5_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP5_BMATTRIBUTES 0x01 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP5_BENDPOINTADDRESS 0x83 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_WMAXPACKETSIZE 1023 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP5_FS_BINTERVAL 1 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_WMAXPACKETSIZE 1024 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP5_HS_BINTERVAL 1 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP6_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP6_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP6_BENDPOINTADDRESS 0x04 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP6_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP6_HS_BINTERVAL 0 + +// +// +// + +// Endpoint +// Enable Endpoint for this interface. +#define USBD_CUSTOM_CLASS0_IF3_EP7_EN 0 + +// Type +// Select Endpoint Type. +// Endpoint Descriptor: bmAttributes field bits 0 .. 1. +// If required, for Isochronous Endpoint, Synchronization and Usage Type +// can be set by manually editing define value of BMATTRIBUTES. +// <2=>Bulk +// <3=>Interrupt +// <1=>Isochronous +#define USBD_CUSTOM_CLASS0_IF3_EP7_BMATTRIBUTES 0x02 + +// Number +// Select Endpoint Number. +// Endpoint Descriptor: bEndpointAddress field bits 0 .. 3. +// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7 +// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15 +// Direction +// Select Endpoint Direction. +// Endpoint Descriptor: bEndpointAddress field bit 7. +// <0=>OUT +// <1=>IN +#define USBD_CUSTOM_CLASS0_IF3_EP7_BENDPOINTADDRESS 0x84 + +// Speed Settings +// Settings that are different depending on device operating speed. +// +// Full/Low-speed +// Parameters apply when device operates in Full/Low-speed. +// +// Maximum Packet Size <0-1023> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 8, 16, 32 or 64. +// For Interrupt Endpoint set value to 1 .. 64. +// For Isochronous Endpoint set value to 1 .. 1023. +#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_WMAXPACKETSIZE 64 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in ms). +// Endpoint Descriptor: bInterval field. +// Setting is not used for Bulk Endpoint (set value to 0). +// For Interrupt Endpoint set value to 1 .. 255 (polling interval). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP7_FS_BINTERVAL 0 + +// + +// High-speed +// Parameters apply when High-speed is enabled in corresponding USBD_Config_n.h +// (n is the index of device on which this interface will be used) and when +// device operates in High-speed. +// +// Maximum Packet Size <0-1024> +// Specifies the physical packet size used for information exchange (in bytes). +// Endpoint Descriptor: wMaxPacketSize field bits 0 .. 10. +// For Bulk Endpoint set value to 512. +// For Interrupt Endpoint set value to 1 .. 1024. +// For Isochronous Endpoint set value to 1 .. 1024. +// Additional Transactions per Microframe +// Specifies additional transactions per microframe to improve communication performance. +// Endpoint Descriptor: wMaxPacketSize field bits 11 .. 12. +// Relevant only if Endpoint Type is Isochronous or Interrupt. +// Value: None = 1 transaction per microframe +// Value: 1 additional = 2 transaction per microframe +// Value: 2 additional = 3 transaction per microframe +// <0=>None +// <1=>1 additional +// <2=>2 additional +#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_WMAXPACKETSIZE 512 + +// Endpoint Polling Interval <0-255> +// Specifies the frequency of requests initiated by USB Host (in 125 us units). +// Endpoint Descriptor: bInterval field. +// For Bulk Endpoint this setting represents maximum NAK rate, set value to 0 .. 255. +// For Interrupt Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +// For Isochronous Endpoint set value to 1 .. 16 (polling interval is 2^(value-1)). +#define USBD_CUSTOM_CLASS0_IF3_EP7_HS_BINTERVAL 0 + +// +// +// +// + +// String Settings +// Following settings are used to create String Descriptor(s) + +// Interface String Enable +// Enable Interface String. +// If disabled Interface String will not be assigned to USB Device Custom Class Interface 3. +#define USBD_CUSTOM_CLASS0_IF3_STR_EN 0 + +// Interface String +#define USBD_CUSTOM_CLASS0_IF3_STR_RAW "USB_CUSTOM_CLASS0_IF3" + +// +// + +// Microsoft OS Descriptor Settings +// Following settings are used to create Extended Compat ID OS Feature Descriptor + +// Extended Compat ID OS Feature Descriptor Function Section +// Enable creation of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID_EN 0 + +// compatibleID +// compatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_COMPAT_ID "WINUSB" + +// subCompatibleID +// subCompatibleID field of function section in Extended Compat ID OS Feature Descriptor for this interface. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_SUBCOMPAT_ID "" + +// + +// Extended Properties OS Feature Descriptor +// Custom Property Section 0 +// Enable creation of custom property 0 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 0 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_NAME_RAW "DeviceInterfaceGUID" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_STR_RAW "{7D9ADCFC-E570-4B38-BF4E-8F81F68964E0}" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP0_DATA_INT 0 + +// +// + +// Custom Property Section 1 +// Enable creation of custom property 1 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 1 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP1_DATA_INT 0 + +// +// + +// Custom Property Section 2 +// Enable creation of custom property 2 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 2 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP2_DATA_INT 0 + +// +// + +// Custom Property Section 3 +// Enable creation of custom property 3 section in Extended Properties OS Feature Descriptor. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_EN 0 + +// Data Type +// Specifies the dwPropertyDataType field of custom property 3 section in Extended Properties OS Feature Descriptor. +// Values 3 (Free-form binary) and 7 (Multiple Unicode Strings) are not supported. +// <1=>Unicode String (REG_SZ) +// <2=>Unicode String with environment variables (REG_EXPAND_SZ) +// <4=>Little-endian 32-bit integer (REG_DWORD_LITTLE_ENDIAN) +// <5=>Big-endian 32-bit integer (REG_DWORD_BIG_ENDIAN) +// <6=>Unicode String with symbolic link (REG_LINK) +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_TYP 1 + +// Name +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_NAME_RAW "" + +// Data +// Unicode String +// Property Data in case Data Type is selected as Unicode String. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_STR_RAW "" + +// 32-bit Integer +// Property Data in case Data Type is selected as Little/Big-endian 32-bit Integer. +#define USBD_CUSTOM_CLASS0_IF3_OS_EXT_PROP3_DATA_INT 0 + +// +// +// +// +// + + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Endpoint 1 Thread Stack Size <64-65536> +// This setting is used if Endpoint 1 is enabled. +#define USBD_CUSTOM_CLASS0_EP1_THREAD_STACK_SIZE 512 + +// Endpoint 1 Thread Priority +#define USBD_CUSTOM_CLASS0_EP1_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 2 Thread Stack Size <64-65536> +// This setting is used if Endpoint 2 is enabled. +#define USBD_CUSTOM_CLASS0_EP2_THREAD_STACK_SIZE 512 + +// Endpoint 2 Thread Priority +#define USBD_CUSTOM_CLASS0_EP2_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 3 Thread Stack Size <64-65536> +// This setting is used if Endpoint 3 is enabled. +#define USBD_CUSTOM_CLASS0_EP3_THREAD_STACK_SIZE 512 + +// Endpoint 3 Thread Priority +#define USBD_CUSTOM_CLASS0_EP3_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 4 Thread Stack Size <64-65536> +// This setting is used if Endpoint 4 is enabled. +#define USBD_CUSTOM_CLASS0_EP4_THREAD_STACK_SIZE 512 + +// Endpoint 4 Thread Priority +#define USBD_CUSTOM_CLASS0_EP4_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 5 Thread Stack Size <64-65536> +// This setting is used if Endpoint 5 is enabled. +#define USBD_CUSTOM_CLASS0_EP5_THREAD_STACK_SIZE 512 + +// Endpoint 5 Thread Priority +#define USBD_CUSTOM_CLASS0_EP5_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 6 Thread Stack Size <64-65536> +// This setting is used if Endpoint 6 is enabled. +#define USBD_CUSTOM_CLASS0_EP6_THREAD_STACK_SIZE 512 + +// Endpoint 6 Thread Priority +#define USBD_CUSTOM_CLASS0_EP6_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 7 Thread Stack Size <64-65536> +// This setting is used if Endpoint 7 is enabled. +#define USBD_CUSTOM_CLASS0_EP7_THREAD_STACK_SIZE 512 + +// Endpoint 7 Thread Priority +#define USBD_CUSTOM_CLASS0_EP7_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 8 Thread Stack Size <64-65536> +// This setting is used if Endpoint 8 is enabled. +#define USBD_CUSTOM_CLASS0_EP8_THREAD_STACK_SIZE 512 + +// Endpoint 8 Thread Priority +#define USBD_CUSTOM_CLASS0_EP8_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 9 Thread Stack Size <64-65536> +// This setting is used if Endpoint 9 is enabled. +#define USBD_CUSTOM_CLASS0_EP9_THREAD_STACK_SIZE 512 + +// Endpoint 9 Thread Priority +#define USBD_CUSTOM_CLASS0_EP9_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 10 Thread Stack Size <64-65536> +// This setting is used if Endpoint 10 is enabled. +#define USBD_CUSTOM_CLASS0_EP10_THREAD_STACK_SIZE 512 + +// Endpoint 10 Thread Priority +#define USBD_CUSTOM_CLASS0_EP10_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 11 Thread Stack Size <64-65536> +// This setting is used if Endpoint 11 is enabled. +#define USBD_CUSTOM_CLASS0_EP11_THREAD_STACK_SIZE 512 + +// Endpoint 11 Thread Priority +#define USBD_CUSTOM_CLASS0_EP11_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 12 Thread Stack Size <64-65536> +// This setting is used if Endpoint 12 is enabled. +#define USBD_CUSTOM_CLASS0_EP12_THREAD_STACK_SIZE 512 + +// Endpoint 12 Thread Priority +#define USBD_CUSTOM_CLASS0_EP12_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 13 Thread Stack Size <64-65536> +// This setting is used if Endpoint 13 is enabled. +#define USBD_CUSTOM_CLASS0_EP13_THREAD_STACK_SIZE 512 + +// Endpoint 13 Thread Priority +#define USBD_CUSTOM_CLASS0_EP13_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 14 Thread Stack Size <64-65536> +// This setting is used if Endpoint 14 is enabled. +#define USBD_CUSTOM_CLASS0_EP14_THREAD_STACK_SIZE 512 + +// Endpoint 14 Thread Priority +#define USBD_CUSTOM_CLASS0_EP14_THREAD_PRIORITY osPriorityAboveNormal + +// Endpoint 15 Thread Stack Size <64-65536> +// This setting is used if Endpoint 15 is enabled. +#define USBD_CUSTOM_CLASS0_EP15_THREAD_STACK_SIZE 512 + +// Endpoint 15 Thread Priority +#define USBD_CUSTOM_CLASS0_EP15_THREAD_PRIORITY osPriorityAboveNormal + +// +// diff --git a/board/AppKit-E7/RTE/USB/USB_Debug.h b/board/AppKit-E7/RTE/USB/USB_Debug.h new file mode 100644 index 0000000..0075b29 --- /dev/null +++ b/board/AppKit-E7/RTE/USB/USB_Debug.h @@ -0,0 +1,73 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB + * Copyright (c) 2004-2024 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USB_Debug.h + * Purpose: USB Host/Device Debug Configuration + * Rev.: V8.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device Debug +// Enable USB Device debugging with Event Recorder +#define USBD_DEBUG_EVR 0 + +// Core <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Core event recording +#define USBD_DEBUG_EVR_Core 1 + +// Driver <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Driver event recording +#define USBD_DEBUG_EVR_Driver 1 + +// Custom Class <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Custom Class event recording +#define USBD_DEBUG_EVR_CC 1 + +// Audio Device Class (ADC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Audio Device Class event recording +#define USBD_DEBUG_EVR_ADC 1 + +// Communication Device Class (CDC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Communication Device Class event recording +#define USBD_DEBUG_EVR_CDC 1 + +// Human Interface Device class (HID) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Human Interface Device class event recording +#define USBD_DEBUG_EVR_HID 1 + +// Mass Storage Class (MSC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Mass Storage Class event recording +#define USBD_DEBUG_EVR_MSC 1 +// + +// USB Host Debug +// Enable USB Host debugging with Event Recorder +#define USBH_DEBUG_EVR 0 + +// Core <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Core event recording +#define USBH_DEBUG_EVR_Core 1 + +// Driver <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Driver event recording +#define USBH_DEBUG_EVR_Driver 1 + +// Custom Class <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Custom Class event recording +#define USBH_DEBUG_EVR_CC 1 + +// Communication Device Class (CDC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Communication Device Class event recording +#define USBH_DEBUG_EVR_CDC 1 + +// Human Interface Device class (HID) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Human Interface Device class event recording +#define USBH_DEBUG_EVR_HID 1 + +// Mass Storage Class (MSC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Mass Storage Class event recording +#define USBH_DEBUG_EVR_MSC 1 +// diff --git a/board/AppKit-E7/RTE/USB/USB_Debug.h.base@8.0.0 b/board/AppKit-E7/RTE/USB/USB_Debug.h.base@8.0.0 new file mode 100644 index 0000000..0075b29 --- /dev/null +++ b/board/AppKit-E7/RTE/USB/USB_Debug.h.base@8.0.0 @@ -0,0 +1,73 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB + * Copyright (c) 2004-2024 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USB_Debug.h + * Purpose: USB Host/Device Debug Configuration + * Rev.: V8.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// USB Device Debug +// Enable USB Device debugging with Event Recorder +#define USBD_DEBUG_EVR 0 + +// Core <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Core event recording +#define USBD_DEBUG_EVR_Core 1 + +// Driver <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Driver event recording +#define USBD_DEBUG_EVR_Driver 1 + +// Custom Class <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Custom Class event recording +#define USBD_DEBUG_EVR_CC 1 + +// Audio Device Class (ADC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Audio Device Class event recording +#define USBD_DEBUG_EVR_ADC 1 + +// Communication Device Class (CDC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Communication Device Class event recording +#define USBD_DEBUG_EVR_CDC 1 + +// Human Interface Device class (HID) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Human Interface Device class event recording +#define USBD_DEBUG_EVR_HID 1 + +// Mass Storage Class (MSC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Device Mass Storage Class event recording +#define USBD_DEBUG_EVR_MSC 1 +// + +// USB Host Debug +// Enable USB Host debugging with Event Recorder +#define USBH_DEBUG_EVR 0 + +// Core <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Core event recording +#define USBH_DEBUG_EVR_Core 1 + +// Driver <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Driver event recording +#define USBH_DEBUG_EVR_Driver 1 + +// Custom Class <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Custom Class event recording +#define USBH_DEBUG_EVR_CC 1 + +// Communication Device Class (CDC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Communication Device Class event recording +#define USBH_DEBUG_EVR_CDC 1 + +// Human Interface Device class (HID) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Human Interface Device class event recording +#define USBH_DEBUG_EVR_HID 1 + +// Mass Storage Class (MSC) <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure USB Host Mass Storage Class event recording +#define USBH_DEBUG_EVR_MSC 1 +// diff --git a/board/AppKit-E7/board_display.c b/board/AppKit-E7/board_display.c new file mode 100644 index 0000000..6fb9c6f --- /dev/null +++ b/board/AppKit-E7/board_display.c @@ -0,0 +1,122 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * AppKit-E7 display bring-up through the pack's CDC200 driver, the sequence + * the pack's vStream VideoOut driver uses: Initialize, PowerControl, enable + * the start-of-frame event, configure the display (which also initialises + * the MIPI DSI link and the ILI9806E panel), set a frame buffer, Start. + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "Driver_CDC200.h" +#include "cdc.h" +#include "board_display.h" + +#include "RTE_Components.h" +#ifdef RTE_CMSIS_RTOS2 +#include "cmsis_os2.h" +#endif + +extern ARM_DRIVER_CDC200 Driver_CDC200; +static ARM_DRIVER_CDC200 *cdc = &Driver_CDC200; + +static volatile uint32_t frames_started; + +static void cdc_callback(uint32_t event) +{ + if (event & ARM_CDC_SCANLINE0_EVENT) { + frames_started++; + } +} + +int32_t display_init(void) +{ + int32_t status; + + status = cdc->Initialize(cdc_callback); + if (status != ARM_DRIVER_OK) { + return status; + } + status = cdc->PowerControl(ARM_POWER_FULL); + if (status != ARM_DRIVER_OK) { + return status; + } + status = cdc->Control(CDC200_SCANLINE0_EVENT, 1U); + if (status != ARM_DRIVER_OK) { + return status; + } + return cdc->Control(CDC200_CONFIGURE_DISPLAY, 0U); +} + +int32_t display_start(const void *fb) +{ + int32_t status = cdc->Control(CDC200_FRAMEBUF_UPDATE, (uint32_t)fb); + if (status != ARM_DRIVER_OK) { + return status; + } + return cdc->Start(); +} + +int32_t display_present(const void *fb) +{ + return cdc->Control(CDC200_FRAMEBUF_UPDATE_VSYNC, (uint32_t)fb); +} + +uint32_t display_frame_count(void) +{ + return frames_started; +} + +int32_t display_wait_frame(uint32_t count) +{ +#ifdef RTE_CMSIS_RTOS2 + /* Under the RTOS the wait gives the CPU away (another thread renders the + next frame meanwhile): poll once per tick, give up after four frames. */ + if (osKernelGetState() == osKernelRunning) { + for (uint32_t ticks = 0; ticks < 68U; ++ticks) { + if ((int32_t)(frames_started - count) > 0) { + return 0; + } + osDelay(1U); + } + return -1; + } +#endif + /* A 60 Hz frame is 16.7 ms; give up after roughly four of them. */ + for (uint32_t spins = 0; spins < 4000000U; ++spins) { + if ((int32_t)(frames_started - count) > 0) { + return 0; + } + } + return -1; +} + +int32_t display_wait_shown(const void *fb) +{ + /* The layer's frame buffer address is a shadowed register: it reads back + the working value, so it shows `fb` only once the reload at the start of + the vertical blanking has happened (hardware reference manual, "Shadowed + Registers Reload"). From then on the buffer shown before is not read any + more. A scanline-0 count cannot tell that: a request that arrives in the + blanking interval, after the reload point, takes one frame longer. + `fb` is in the bulk SRAM, where local and global addresses are equal. */ + const CDC_Type *regs = (const CDC_Type *)CDC_BASE; + + for (uint32_t ticks = 0; ticks < 68U; ++ticks) { + if (regs->CDC_LAYER_CFG[CDC_LAYER_1].CDC_L_CFB_ADDR == (uint32_t)fb) { + return 0; + } +#ifdef RTE_CMSIS_RTOS2 + if (osKernelGetState() == osKernelRunning) { + osDelay(1U); + continue; + } +#endif + for (volatile uint32_t spin = 0; spin < 60000U; ++spin) { + } + } + return -1; +} diff --git a/board/AppKit-E7/board_display.h b/board/AppKit-E7/board_display.h new file mode 100644 index 0000000..ea36053 --- /dev/null +++ b/board/AppKit-E7/board_display.h @@ -0,0 +1,43 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * AppKit-E7 display: the CDC200 display controller driving the ILI9806E + * 480x800 panel over MIPI DSI, configured by RTE_Device.h (RGB888, 60 fps). + * A thin wrapper over the pack's Driver_CDC200 for a double-buffered app. + *---------------------------------------------------------------------------*/ +#ifndef BOARD_DISPLAY_H_ +#define BOARD_DISPLAY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Bring up the controller, the DSI link and the panel; 0 on success. */ +int32_t display_init(void); + +/* Start scanning out from fb (RGB888, APP_DISPLAY_WIDTH x APP_DISPLAY_HEIGHT); 0 on success. */ +int32_t display_start(const void *fb); + +/* Switch to fb at the next vertical blanking; 0 on success. */ +int32_t display_present(const void *fb); + +/* Number of frames the controller has started scanning out (SCANLINE0 events). */ +uint32_t display_frame_count(void); + +/* Block until the frame count exceeds `count` (i.e. one more frame has started), + with a timeout of a few frames; returns 0 when it did, -1 on timeout. */ +int32_t display_wait_frame(uint32_t count); + +/* Block until the controller scans out `fb` (the buffer of the last + display_present()): the buffer shown before it is free from then on. + 0, or -1 on a timeout of a few frames. */ +int32_t display_wait_shown(const void *fb); + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_DISPLAY_H_ */ diff --git a/board/AppKit-E7/ethos_setup.c b/board/AppKit-E7/ethos_setup.c new file mode 100644 index 0000000..c077e48 --- /dev/null +++ b/board/AppKit-E7/ethos_setup.c @@ -0,0 +1,117 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025-2026 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + + #include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "ethosu_driver.h" +#include "main.h" + +#if defined(ETHOSU85) +/* Define Ethos-U NPU base address and interrupt handler */ +#define ETHOSU_BASE_ADDR NPU_HG_BASE +#define ETHOSU_IRQ_HANDLER IRQ366_Handler /* NPU_HG_IRQHandler */ +#define ETHOSU_IRQ_IRQn 366 /* NPU_HG_IRQn */ + +/* Define Ethos-U NPU cache buffer size */ +#ifndef ETHOS_CACHE_BUF_SIZE +#define ETHOS_CACHE_BUF_SIZE 0 +#endif + +/* Define Ethos-U cache buffer alignment */ +#ifndef ETHOS_CACHE_BUF_ALIGNMENT +#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#endif + +/* Define Ethos-U NPU cache buffer attributes */ +#ifndef ETHOS_CACHE_BUF_ATTRIBUTES +#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#endif + +#else /* Ethos-U55 */ +/* Define Ethos-U NPU base address and interrupt handler */ +#define ETHOSU_BASE_ADDR NPU_HP_BASE +#define ETHOSU_IRQ_HANDLER NPU_HP_IRQHandler +#define ETHOSU_IRQ_IRQn NPU_HP_IRQ_IRQn +#endif /* ETHOSU85 */ + +/* Define Ethos-U NPU security mode */ +#ifndef ETHOS_SECURE_ENABLE +#define ETHOS_SECURE_ENABLE 1 +#endif + +/* Define Ethos-U NPU privilege mode */ +#ifndef ETHOS_PRIVILEGE_ENABLE +#define ETHOS_PRIVILEGE_ENABLE 1 +#endif + +/* Ethos NPU driver instance. */ +static struct ethosu_driver EthosDriver; + +#if defined(ETHOSU85) +static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#endif + +/* + Ethos NPU interrupt handler. +*/ +void ETHOSU_IRQ_HANDLER(void) { + ethosu_irq_handler(&EthosDriver); +} + +/* + Initialize the Ethos NPU driver. +*/ +void ethos_setup (void) { + void *const ethos_base_addr = (void *)ETHOSU_BASE_ADDR; + int rval; + struct ethosu_hw_info hw_info; + + /* Initialize Ethos-U NPU driver. */ + rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ + ethos_base_addr, /* Ethos-U base address */ + #if (ETHOS_CACHE_BUF_SIZE > 0) + ethos_cache, /* Cache memory pointer */ + sizeof(ethos_cache), /* Cache memory size */ + #else + 0, /* Cache memory pointer */ + 0, /* Cache memory size */ + #endif + ETHOS_SECURE_ENABLE, /* Secure enable */ + ETHOS_PRIVILEGE_ENABLE); /* Privileged mode */ + if (rval != 0) { + printf("Failed to initialize Arm Ethos-U driver\n"); + /* Early return on error */ + return; + } + + NVIC_EnableIRQ(ETHOSU_IRQ_IRQn); + + /* Banner printed unconditionally (the pack layer prints it only with + DEBUG): the visible proof on the console that the NPU came up. */ + ethosu_get_hw_info(&EthosDriver, &hw_info); + + printf("Ethos-U version info:\n"); + printf("\tArch: v%u.%u.%u\n", hw_info.version.arch_major_rev, + hw_info.version.arch_minor_rev, + hw_info.version.arch_patch_rev); + printf("\tMACs/cc: %u\n", (uint32_t)(1 << hw_info.cfg.macs_per_cc)); + printf("\tCmd stream: v%u\n", hw_info.cfg.cmd_stream_version); +} diff --git a/board/AppKit-E7/ethosu_cb_dcache.c b/board/AppKit-E7/ethosu_cb_dcache.c new file mode 100644 index 0000000..19619f1 --- /dev/null +++ b/board/AppKit-E7/ethosu_cb_dcache.c @@ -0,0 +1,114 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include +#include CMSIS_device_header + +#include "ethosu_driver.h" +#include "app_mem_regions.h" + +typedef struct { + uint32_t start_addr; // Base address of a block + uint32_t end_addr; // End address of a block (inclusive) +} mem_block_t; + +// Regions the NPU reaches without going through the data cache (the device +// header already defines ITCM_BASE/DTCM_BASE; app_mem_regions.h has the +// application view used here). +const mem_block_t non_cached_memory[] = { + {APP_ITCM_BASE, APP_ITCM_BASE + APP_HP_ITCM_SIZE - 1}, + {APP_DTCM_BASE, APP_DTCM_BASE + APP_HP_DTCM_SIZE - 1}, + {APP_MRAM_HP_BASE, APP_MRAM_HP_BASE + APP_MRAM_HP_SIZE - 1} +}; + +/** + \brief Check if the memory region needs to be invalidated. + \param[in] p Pointer to the memory region start address. + \param[in] bytes Size of memory region in bytes. + \return true if an invalidate is required, false otherwise + */ +static bool check_mem_region(const void *p, size_t bytes) +{ + uint32_t n_blocks; + uint32_t block; + uint32_t mem_start; + uint32_t mem_end; + + mem_start = (uint32_t) p; + mem_end = mem_start + bytes - 1; + + n_blocks = sizeof(non_cached_memory) / sizeof(non_cached_memory[0]); + + for (block = 0; block < n_blocks; block++) { + /* Is current block within non-cacheable memory region */ + if (mem_start >= non_cached_memory[block].start_addr && + mem_end <= non_cached_memory[block].end_addr) { + /* No need for cache management */ + return false; + } + } + + return true; +} + +void ethosu_flush_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) +{ + for (int i = 0; i < num_base_addr; i++) { + if (check_mem_region((const void *)(uintptr_t)base_addr[i], base_addr_size[i])) { + /* Call CleanDCache instead of CleanDCache_by_Addr to avoid delays. */ + /* Memory regions size is usually large and calling by_Addr consumes time. */ + SCB_CleanDCache(); + + /* Cache is cleaned, return immediately */ + return; + } + } + + /* No cleaning, just ensure all memory accesses are completed before continuing */ + __DSB(); +} + +/* Set by an application whose CPU side never reads what the NPU writes (the + panel scans the NPU's output out of the scratch): the invalidate after a job + then only throws the working set of whatever else runs out of the data cache. + Lines the CPU wrote into the scratch before (the inputs) are written back by + the clean before the next job, whole lines at a time, so a stale copy of + them in the cache does no harm. */ +volatile bool ethosu_dcache_keep; + +void ethosu_invalidate_dcache(const uint64_t *base_addr, const size_t *base_addr_size, int num_base_addr) +{ + if (ethosu_dcache_keep) { + __DSB(); + return; + } + for (int i = 0; i < num_base_addr; i++) { + if (check_mem_region((const void *)(uintptr_t)base_addr[i], base_addr_size[i])) { + /* Call CleanInvalidateDCache instead of SCB_InvalidateDCache to avoid silently losing data. */ + /* This avoids losing dirty lines that the CPU has written but not yet committed to memory. */ + SCB_CleanInvalidateDCache(); + + /* Cache is cleaned and invalidated, return immediately */ + return; + } + } + + /* No invalidation, just ensure all memory accesses are completed before continuing */ + __DSB(); +} diff --git a/board/AppKit-E7/linker_ac6_traffic.sct.src b/board/AppKit-E7/linker_ac6_traffic.sct.src new file mode 100644 index 0000000..566bf90 --- /dev/null +++ b/board/AppKit-E7/linker_ac6_traffic.sct.src @@ -0,0 +1,123 @@ +; Preprocessed by the CMSIS-Toolbox, not by the armlink "#!" line: +; app_mem_regions.h (the RTE copy in this layer) is force-included by the +; CMSIS-Toolbox through the regions entry of the layer linker node, which +; also makes the toolbox preprocess this .src file with the project defines. + +/* ../DevKit-E8/linker_ac6_yolo.sct.src for the Ensemble E7 (AppKit-E7, + traffic/traffic.cproject.yml). The MRAM is laid out as on the E8: the + YOLO26n program is a 2.4 MB constant, more than the 2 MB HP region, so the + code region runs on into the MRAM user region (0x80400000, 1.5 MB) and ends + 64 kB below the top of the MRAM, where the Secure Enclave's application + package (the boot table and the debug stubs, .alif/) lives. + The E7's SRAM0 (4 MB at 0x02000000) and SRAM1 (2.5 MB at 0x08000000) are + two regions: SRAM0 holds the ExecuTorch pools, the thread stacks and both + frame buffers; SRAM1, not initialised by the C library (the application + asks the Secure Enclave to power it before the first use), the camera's + raw frames and the model input slots (.bss.sram1). The first 4 kB of SRAM0 + stay free: the boot configuration loads the Cortex-A32 stub there. */ + +#define TRAFFIC_MRAM_END (APP_MRAM_USER_BASE + APP_MRAM_USER_SIZE - 0x10000) + +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE (TRAFFIC_MRAM_END - APP_MRAM_HP_BASE) + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE 0x00004000 /* 16 kB for main and the exception handlers; app_main runs in an RTX thread with its own 32 kB stack (main.c) */ +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ER_MODEL (AlignExpr(+0, 16)) { ; the YOLO26n program, after everything else read-only: + *model_pte.o (+RO) ; it is the part that runs on into the MRAM user region + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) ; USB EP0 buffer (USBD0_BUF_MEM_LOCATE) + ; The USB controller reads and writes the DTCM only inside this non-secure + ; region: everything the SDS link hands to the USB DMA goes here too. + *sdsio_client_usb_mdk.o (+RW +ZI) ; the bulk OUT buffer + *sdsio_client.o (+RW +ZI) ; error data sent with the info command + *sds.o (+RW +ZI) ; the stream data block + * (.bss.os) ; RTX dynamic memory: the SDS thread's stack holds the headers it sends + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + + RW_SRAM0 (APP_SRAM0_BASE + 0x1000) (APP_SRAM0_SIZE - 0x1000) { + * (.bss.ai_pool) ; ExecuTorch pools, stream buffers, thread stacks + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; the two LCD frame buffers + } + + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } + + ; Not initialised: the application powers SRAM1 before its first use. + RW_SRAM1 APP_SRAM1_BASE UNINIT APP_SRAM1_SIZE { + * (.bss.sram1) ; model input slots, the NPU scratch + } +} diff --git a/board/AppKit-E7/main.c b/board/AppKit-E7/main.c new file mode 100644 index 0000000..2686c40 --- /dev/null +++ b/board/AppKit-E7/main.c @@ -0,0 +1,139 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025-2026 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * AppKit-E7 (M55_HP) board bring-up for the traffic counter. Derived from the + * Ensemble pack's board layer main.c (the DevKit-E8's, which the AppKit-E7 + * layer follows): the Secure Enclave link, the clocks, the MIPI DPHY power for + * the panel and the camera, the USB PHY for SDS, then the application in an + * RTX thread. + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "board_config.h" +#include "main.h" + +#include "se_services_port.h" +#include "board_display.h" +#ifdef RTE_CMSIS_RTOS2 +#include "cmsis_os2.h" +#endif + +/* VBAT power control bits for the MIPI TX DPHY and its PLL (pack layer main.c) */ +#define VBAT_PWR_CTRL_TX_DPHY_PWR_MASK (1U << 0) /* Mask off the power supply for MIPI TX DPHY */ +#define VBAT_PWR_CTRL_TX_DPHY_ISO (1U << 1) /* Enable isolation for MIPI TX DPHY */ +#define VBAT_PWR_CTRL_RX_DPHY_PWR_MASK (1U << 4) /* Mask off the power supply for MIPI RX DPHY */ +#define VBAT_PWR_CTRL_RX_DPHY_ISO (1U << 5) /* Enable isolation for MIPI RX DPHY */ +#define VBAT_PWR_CTRL_DPHY_PLL_PWR_MASK (1U << 8) /* Mask off the power supply for MIPI PLL */ +#define VBAT_PWR_CTRL_DPHY_PLL_ISO (1U << 9) /* Enable isolation for MIPI PLL */ +#define VBAT_PWR_CTRL_DPHY_VPH_1P8_PWR_BYP_EN (1U << 12) /* dphy vph 1p8 power bypass enable */ + +/* + Power up the MIPI DPHY (the display's physical layer), as the pack's + DevKit-e8 layer does in its vbat_init(). +*/ +static void dphy_power_init(void) +{ + VBAT->PWR_CTRL &= ~(VBAT_PWR_CTRL_TX_DPHY_PWR_MASK | VBAT_PWR_CTRL_RX_DPHY_PWR_MASK | + VBAT_PWR_CTRL_DPHY_PLL_PWR_MASK | VBAT_PWR_CTRL_DPHY_VPH_1P8_PWR_BYP_EN); + VBAT->PWR_CTRL &= ~(VBAT_PWR_CTRL_TX_DPHY_ISO | VBAT_PWR_CTRL_RX_DPHY_ISO | VBAT_PWR_CTRL_DPHY_PLL_ISO); +} + +#ifdef RTE_SDS_IO_CLIENT_USB +#include "services_lib_api.h" +#include "aipm.h" +static void usb_power_init(void) +{ + uint32_t error_code = 0; + run_profile_t runp; + if (SERVICES_clocks_enable_clock(se_services_s_handle, CLKEN_CLK_20M, true, &error_code) != 0 || error_code != 0) { + return; + } + if (SERVICES_get_run_cfg(se_services_s_handle, &runp, &error_code) != 0) { + return; + } + runp.phy_pwr_gating |= USB_PHY_MASK; + SERVICES_set_run_cfg(se_services_s_handle, &runp, &error_code); +} +#endif + +#ifdef RTE_CMSIS_RTOS2 +#ifndef APP_THREAD_STACK_SIZE +#define APP_THREAD_STACK_SIZE 0x8000 +#endif +static uint64_t app_thread_stack[APP_THREAD_STACK_SIZE / 8] __attribute__((section(".bss.ai_pool"))); +static const osThreadAttr_t app_thread_attr = { + .name = "app", + .stack_mem = app_thread_stack, + .stack_size = sizeof(app_thread_stack), + .priority = osPriorityNormal, +}; + +static void app_thread(void *argument) +{ + (void)argument; + app_main(); + for (;;) { + osDelay(osWaitForever); + } +} +#endif + +int main(void) +{ + /* Apply the Conductor pin configuration (includes the UART4 console pins) */ + board_pins_config(); + + /* Apply the Conductor GPIO configuration */ + board_gpios_config(); + + /* Bring up the Secure Enclave services (MHU link to the SE) */ + se_services_port_init(); + + /* Request the clocks the SE has to enable for this core */ + board_clocks_config(CLKEN_HFOSC_MASK | CLKEN_CLK_100M_MASK); + + /* Power up the MIPI DPHY before the display driver touches it */ + dphy_power_init(); + +#ifdef RTE_SDS_IO_CLIENT_USB + /* The USB device (SDS over the User USB): its 20 MHz clock and the PHY's + power, through the Secure Enclave, as the pack's AppKit-E7 layer does. */ + usb_power_init(); +#endif + + /* Initialize STDIO (UART4 on the PRG USB connector) */ + stdio_init(); + + #if defined(ETHOSU_ARCH) + /* Initialize Ethos NPU */ + ethos_setup(); + #endif + +#ifdef RTE_CMSIS_RTOS2 + /* The application's threads and the SDS Stream component need + CMSIS-RTOS2: run the application in an RTX thread. Its stack lives in + the bulk SRAM next to the ExecuTorch pools. */ + osKernelInitialize(); + osThreadNew(app_thread, NULL, &app_thread_attr); + osKernelStart(); + for (;;) {} +#else + return app_main(); +#endif +} diff --git a/board/AppKit-E7/main.h b/board/AppKit-E7/main.h new file mode 100644 index 0000000..b387095 --- /dev/null +++ b/board/AppKit-E7/main.h @@ -0,0 +1,41 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#ifndef MAIN_H_ +#define MAIN_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Prototypes */ +extern int app_main(void); +extern int shield_setup(void); +extern int stdio_init(void); + +#if defined(ETHOSU_ARCH) +extern void ethos_setup (void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* MAIN_H_ */ diff --git a/board/AppKit-E7/retarget_stdio_log.c b/board/AppKit-E7/retarget_stdio_log.c new file mode 100644 index 0000000..a3eeba8 --- /dev/null +++ b/board/AppKit-E7/retarget_stdio_log.c @@ -0,0 +1,87 @@ +/*--------------------------------------------------------------------------- + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: retarget_stdio_log.c + * Purpose: Retarget stdio to a log buffer the debugger reads + * + * CMSIS-Compiler STDOUT/STDERR/STDIN:Custom backend for a board whose SW4 + * stays on SEUART, so that the Secure Enclave tools can program and reset it + * without anyone touching the board: UART4, the usual console, is then not + * connected to the host. Characters go into `console_log`, a ring buffer in + * the DTCM, which a debugger reads while the core runs (tools/console_log.py); + * the DTCM is not behind the data cache, so what is read is what was written. + *---------------------------------------------------------------------------*/ + +#include + +#define CONSOLE_LOG_SIZE 0x8000U + +/* `head` counts every character since start; text[head % size] is the next + one to be written, so a reader sees the last `size` characters. */ +struct console_log_s { + uint32_t magic; /* 'CLOG' */ + uint32_t size; + volatile uint32_t head; + char text[CONSOLE_LOG_SIZE]; +} console_log __attribute__((section(".bss.console_log"), used)); + +/** + Initialize stdio + + \return 0 on success, or -1 on error. +*/ +int stdio_init (void) { + console_log.magic = 0x474F4C43U; + console_log.size = CONSOLE_LOG_SIZE; + console_log.head = 0U; + return 0; +} + +static int log_putchar (int ch) { + console_log.text[console_log.head % CONSOLE_LOG_SIZE] = (char)ch; + console_log.head++; + return ch; +} + +/** + Put a character to the stderr + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stderr_putchar (int ch) { + return log_putchar(ch); +} + +/** + Put a character to the stdout + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stdout_putchar (int ch) { + return log_putchar(ch); +} + +/** + Get a character from the stdio + + \return The next character from the input, or -1 on read error. +*/ +int stdin_getchar (void) { + return -1; +} diff --git a/board/Corstone-300/Board-Traffic.clayer.yml b/board/Corstone-300/Board-Traffic.clayer.yml new file mode 100644 index 0000000..7ba01dc --- /dev/null +++ b/board/Corstone-300/Board-Traffic.clayer.yml @@ -0,0 +1,79 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# Corstone-300 (SSE-300) FVP board bring-up for the traffic counter +# (traffic/traffic.cproject.yml): the Cortex-M55 with an Ethos-U55-256, the +# NPU configuration of the Ensemble E7's HP core, so the AI layer of the +# AppKit-E7 runs unchanged. What the FVP has not, the application leaves out: +# no APP_HAS_CAMERA, APP_HAS_DISPLAY, APP_HAS_SDS or APP_HAS_JOYSTICK, so the +# input is the test image (traffic/test_image.c). TRAFFIC_FRAMES frames go +# through the detector and the tracker, each frame's detections are printed +# over semihosting on the model's stdout, and exit() ends the simulation. +# +# Memory: the program with the 2.3 MB YOLO26n .pte and the test image, the +# ExecuTorch pools, the NPU scratch and the input slots exceed the SRAMs, so +# code and data run from the DDR4 (regions_SSE-300.h). The FVP does not model +# memory timing; its NPU runs in fast mode (fvp_config.txt). +layer: + type: Board + description: Corstone-300 FVP board setup for the traffic counter on the Ethos-U55 + for-board: ARM::V2M-MPS3-SSE-300-FVP + for-device: ARM::SSE-300-MPS3 + + connections: + - connect: Corstone-300 + provides: + - STDIN + - STDOUT + - STDERR + - Heap: 98304 # __HEAP_SIZE in regions_SSE-300.h + + define: + - CMSIS_target_header: \"Corstone-300.h\" + - ETHOSU55 + # The application's ExecuTorch pools and the RTX thread stacks (the + # E7 puts them in its SRAM0; here they go with the rest into the DDR4). + - APP_POOL_SECTION: \".bss.ai_pool\" + - APP_THREAD_STACK_SIZE: 0x8000 + # The frames of the run on the test image (traffic/app_traffic.cpp). + - TRAFFIC_FRAMES: 3 + + packs: + - pack: ARM::CMSIS@^6.2.0 + - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::CMSIS-RTX@^5.9.1 + - pack: ARM::ethos-u-core-driver@^1.26.2 + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + + components: + - component: CMSIS:CORE + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:Custom + - component: CMSIS-Compiler:STDIN:Custom + - component: CMSIS-Compiler:STDOUT:Custom + + - component: Device:Definition + - component: Device:Startup&C Startup + # device_definition.c (Device:Definition) calls wait_us() of the Timeout driver. + - component: Device:Native Driver:SysCounter + - component: Device:Native Driver:SysTimer + - component: Device:Native Driver:Timeout + + # RTX5: app_main runs in an RTX thread (main.c), as on the E7. + - component: CMSIS:RTOS2:Keil RTX5&Source + - component: CMSIS:OS Tick:SysTick + + - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U55 + + groups: + - group: Board + files: + - file: ./main.c + - file: ./main.h + - file: ./Corstone-300.h + - file: ./ethos_setup.c + - file: ./retarget_stdio.c + + linker: + - regions: ./regions_SSE-300.h diff --git a/board/Corstone-300/Corstone-300.h b/board/Corstone-300/Corstone-300.h new file mode 100644 index 0000000..02a7ded --- /dev/null +++ b/board/Corstone-300/Corstone-300.h @@ -0,0 +1,26 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#ifndef CORSTONE_300_H_ +#define CORSTONE_300_H_ + +#ifdef CMSIS_shield_header +#include CMSIS_shield_header +#endif + +#endif /* CORSTONE_300_H_ */ diff --git a/board/Corstone-300/RTE/CMSIS/RTX_Config.c b/board/Corstone-300/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/board/Corstone-300/RTE/CMSIS/RTX_Config.c.base@5.2.0 b/board/Corstone-300/RTE/CMSIS/RTX_Config.c.base@5.2.0 new file mode 100644 index 0000000..d21fa0a --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS/RTX_Config.c.base@5.2.0 @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.2.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + case osRtxErrorSVC: + // Invalid SVC function called (function=object_id) + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/board/Corstone-300/RTE/CMSIS/RTX_Config.h b/board/Corstone-300/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..f8756c5 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/board/Corstone-300/RTE/CMSIS/RTX_Config.h.base@5.6.1 b/board/Corstone-300/RTE/CMSIS/RTX_Config.h.base@5.6.1 new file mode 100644 index 0000000..f8756c5 --- /dev/null +++ b/board/Corstone-300/RTE/CMSIS/RTX_Config.h.base@5.6.1 @@ -0,0 +1,663 @@ +/* + * Copyright (c) 2013-2026 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.6.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// Safety features (Source variant only) +// Enables FuSa related features. +// Requires RTX Source variant. +// Enables: +// - selected features from this group +// - Thread functions: osThreadProtectPrivileged +#ifndef OS_SAFETY_FEATURES +#define OS_SAFETY_FEATURES 0 +#endif + +// Safety Class +// Threads assigned to lower classes cannot modify higher class threads. +// Enables: +// - Object attributes: osSafetyClass +// - Kernel functions: osKernelProtect, osKernelDestroyClass +// - Thread functions: osThreadGetClass, osThreadSuspendClass, osThreadResumeClass +#ifndef OS_SAFETY_CLASS +#define OS_SAFETY_CLASS 1 +#endif + +// MPU Protected Zone +// Access protection via MPU (Spatial isolation). +// Enables: +// - Thread attributes: osThreadZone +// - Thread functions: osThreadGetZone, osThreadTerminateZone +// - Zone Management: osZoneSetup_Callback +#ifndef OS_EXECUTION_ZONE +#define OS_EXECUTION_ZONE 1 +#endif + +// Thread Watchdog +// Watchdog alerts ensure timing for critical threads (Temporal isolation). +// Enables: +// - Thread functions: osThreadFeedWatchdog +// - Handler functions: osWatchdogAlarm_Handler +#ifndef OS_THREAD_WATCHDOG +#define OS_THREAD_WATCHDOG 1 +#endif + +// Object Pointer checking +// Check object pointer alignment and memory region. +#ifndef OS_OBJ_PTR_CHECK +#define OS_OBJ_PTR_CHECK 0 +#endif + +// SVC Function Pointer checking +// Check SVC function pointer alignment and memory region. +// User needs to define a linker execution region RTX_SVC_VENEERS +// containing input sections: rtx_*.o (.text.os.svc.veneer.*) +#ifndef OS_SVC_PTR_CHECK +#define OS_SVC_PTR_CHECK 0 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Idle Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_IDLE_THREAD_CLASS +#define OS_IDLE_THREAD_CLASS 0 +#endif + +// Idle Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_IDLE_THREAD_ZONE +#define OS_IDLE_THREAD_ZONE 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Default Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Thread Safety Class <0-15> +// Defines the Safety Class number. +// Default: 0 +#ifndef OS_TIMER_THREAD_CLASS +#define OS_TIMER_THREAD_CLASS 0 +#endif + +// Timer Thread Zone <0-127> +// Defines Thread Zone. +// Default: 0 +#ifndef OS_TIMER_THREAD_ZONE +#define OS_TIMER_THREAD_ZONE 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src new file mode 100644 index 0000000..7820e1f --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/ac6_linker_script.sct.src @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* ---------------------------------------------------------------------------- + Stack seal size definition + *----------------------------------------------------------------------------*/ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define __STACKSEAL_SIZE 8 +#else +#define __STACKSEAL_SIZE 0 +#endif + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +LR_ROM0 __ROM0_BASE __ROM0_SIZE { + + ER_ROM0 __ROM0_BASE __ROM0_SIZE { + *.o (RESET, +First) + *(InRoot$$Sections) + *(+RO +XO) + } + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + ER_CMSE_VENEER AlignExpr(+0, 32) (__ROM0_SIZE - AlignExpr(ImageLength(ER_ROM0), 32)) { + *(Veneer$$CMSE) + } +#endif + + RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { + *.o(.bss.noinit) + *.o(.bss.noinit.*) + } + + RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP (AlignExpr(+0, 8)) EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK (__RAM0_BASE + __RAM0_SIZE - __STACKSEAL_SIZE) EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if __STACKSEAL_SIZE > 0 + STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack + } +#endif + +#if __RAM1_SIZE > 0 + RW_RAM1 __RAM1_BASE __RAM1_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM2_SIZE > 0 + RW_RAM2 __RAM2_BASE __RAM2_SIZE { + .ANY (+RW +ZI) + } +#endif + +#if __RAM3_SIZE > 0 + RW_RAM3 __RAM3_BASE __RAM3_SIZE { + .ANY (+RW +ZI) + } +#endif +} + +#if __ROM1_SIZE > 0 +LR_ROM1 __ROM1_BASE __ROM1_SIZE { + ER_ROM1 +0 __ROM1_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM2_SIZE > 0 +LR_ROM2 __ROM2_BASE __ROM2_SIZE { + ER_ROM2 +0 __ROM2_SIZE { + .ANY (+RO +XO) + } +} +#endif + +#if __ROM3_SIZE > 0 +LR_ROM3 __ROM3_BASE __ROM3_SIZE { + ER_ROM3 +0 __ROM3_SIZE { + .ANY (+RO +XO) + } +} +#endif diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h new file mode 100644 index 0000000..0e9746a --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + +#endif /* __DEVICE_CFG_H__ */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 new file mode 100644 index 0000000..0e9746a --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/device_cfg.h.base@1.1.4 @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020-2024 Arm Limited. All rights reserved. + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __DEVICE_CFG_H__ +#define __DEVICE_CFG_H__ + +/** + * \file device_cfg.h + * \brief Configuration file native driver re-targeting + * + * \details This file can be used to add native driver specific macro + * definitions to select which peripherals are available in the build. + * + * This is a default device configuration file with all peripherals enabled. + */ + +/* Secure only peripheral configuration */ + +/* ARM MPS3 IO SCC */ +#define MPS3_IO_S +#define MPS3_IO_DEV MPS3_IO_DEV_S + +/* I2C_SBCon */ +#define I2C0_SBCON_S +#define I2C0_SBCON_DEV I2C0_SBCON_DEV_S + +/* I2S */ +#define MPS3_I2S_S +#define MPS3_I2S_DEV MPS3_I2S_DEV_S + +/* ARM UART Controller PL011 */ +#define UART0_CMSDK_S +#define UART0_CMSDK_DEV UART0_CMSDK_DEV_S +#define UART1_CMSDK_S +#define UART1_CMSDK_DEV UART1_CMSDK_DEV_S + +#define DEFAULT_UART_BAUDRATE 115200U + +/* To be used as CODE and DATA sram */ +#define MPC_ISRAM0_S +#define MPC_ISRAM0_DEV MPC_ISRAM0_DEV_S + +#define MPC_ISRAM1_S +#define MPC_ISRAM1_DEV MPC_ISRAM0_DEV_S + +#define MPC_SRAM_S +#define MPC_SRAM_DEV MPC_SRAM_DEV_S + +#define MPC_QSPI_S +#define MPC_QSPI_DEV MPC_QSPI_DEV_S + +/** System Counter Armv8-M */ +#define SYSCOUNTER_CNTRL_ARMV8_M_S +#define SYSCOUNTER_CNTRL_ARMV8_M_DEV SYSCOUNTER_CNTRL_ARMV8_M_DEV_S + +#define SYSCOUNTER_READ_ARMV8_M_S +#define SYSCOUNTER_READ_ARMV8_M_DEV SYSCOUNTER_READ_ARMV8_M_DEV_S +/** + * Arbitrary scaling values for test purposes + */ +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE0_FRACT 0u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_INT 1u +#define SYSCOUNTER_ARMV8_M_DEFAULT_SCALE1_FRACT 0u + +/* System timer */ +#define SYSTIMER0_ARMV8_M_S +#define SYSTIMER0_ARMV8_M_DEV SYSTIMER0_ARMV8_M_DEV_S +#define SYSTIMER1_ARMV8_M_S +#define SYSTIMER1_ARMV8_M_DEV SYSTIMER1_ARMV8_M_DEV_S +#define SYSTIMER2_ARMV8_M_S +#define SYSTIMER2_ARMV8_M_DEV SYSTIMER2_ARMV8_M_DEV_S +#define SYSTIMER3_ARMV8_M_S +#define SYSTIMER3_ARMV8_M_DEV SYSTIMER3_ARMV8_M_DEV_S + +#define SYSTIMER0_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER1_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER2_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) +#define SYSTIMER3_ARMV8M_DEFAULT_FREQ_HZ (25000000ul) + +/* CMSDK GPIO driver structures */ +#define GPIO0_CMSDK_S +#define GPIO0_CMSDK_DEV GPIO0_CMSDK_DEV_S +#define GPIO1_CMSDK_S +#define GPIO1_CMSDK_DEV GPIO1_CMSDK_DEV_S +#define GPIO2_CMSDK_S +#define GPIO2_CMSDK_DEV GPIO2_CMSDK_DEV_S +#define GPIO3_CMSDK_S +#define GPIO3_CMSDK_DEV GPIO3_CMSDK_DEV_S + +/* System Watchdogs */ +#define SYSWDOG_ARMV8_M_S +#define SYSWDOG_ARMV8_M_DEV SYSWDOG_ARMV8_M_DEV_S + +/* ARM MPC SIE 300 driver structures */ +#define MPC_VM0_S +#define MPC_VM0_DEV MPC_VM0_DEV_S +#define MPC_VM1_S +#define MPC_VM1_DEV MPC_VM1_DEV_S +#define MPC_SSRAM2_S +#define MPC_SSRAM2_DEV MPC_SSRAM2_DEV_S +#define MPC_SSRAM3_S +#define MPC_SSRAM3_DEV MPC_SSRAM3_DEV_S + +/* ARM PPC driver structures */ +#define PPC_SSE300_MAIN0_S +#define PPC_SSE300_MAIN0_DEV PPC_SSE300_MAIN0_DEV_S +#define PPC_SSE300_MAIN_EXP0_S +#define PPC_SSE300_MAIN_EXP0_DEV PPC_SSE300_MAIN_EXP0_DEV_S +#define PPC_SSE300_MAIN_EXP1_S +#define PPC_SSE300_MAIN_EXP1_DEV PPC_SSE300_MAIN_EXP1_DEV_S +#define PPC_SSE300_MAIN_EXP2_S +#define PPC_SSE300_MAIN_EXP2_DEV PPC_SSE300_MAIN_EXP2_DEV_S +#define PPC_SSE300_MAIN_EXP3_S +#define PPC_SSE300_MAIN_EXP3_DEV PPC_SSE300_MAIN_EXP3_DEV_S +#define PPC_SSE300_PERIPH0_S +#define PPC_SSE300_PERIPH0_DEV PPC_SSE300_PERIPH0_DEV_S +#define PPC_SSE300_PERIPH1_S +#define PPC_SSE300_PERIPH1_DEV PPC_SSE300_PERIPH1_DEV_S +#define PPC_SSE300_PERIPH_EXP0_S +#define PPC_SSE300_PERIPH_EXP0_DEV PPC_SSE300_PERIPH_EXP0_DEV_S +#define PPC_SSE300_PERIPH_EXP1_S +#define PPC_SSE300_PERIPH_EXP1_DEV PPC_SSE300_PERIPH_EXP1_DEV_S +#define PPC_SSE300_PERIPH_EXP2_S +#define PPC_SSE300_PERIPH_EXP2_DEV PPC_SSE300_PERIPH_EXP2_DEV_S +#define PPC_SSE300_PERIPH_EXP3_S +#define PPC_SSE300_PERIPH_EXP3_DEV PPC_SSE300_PERIPH_EXP3_DEV_S + +/* ARM SPI PL022 */ +/* Invalid device stubs are not defined */ +#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */ +#define SPI1_PL022_S +#define SPI1_PL022_DEV SPI1_PL022_DEV_S + +#endif /* __DEVICE_CFG_H__ */ diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c new file mode 100644 index 0000000..b29bff1 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) +#ifdef CORSTONE300_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +#ifdef CORSTONE300_FVP + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..b29bff1 --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/startup_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,487 @@ +/* + * Copyright (c) 2022-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 startup_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; +extern uint32_t __STACK_LIMIT; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +extern uint64_t __STACK_SEAL; +#endif + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler (void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +#define DEFAULT_IRQ_HANDLER(handler_name) \ +void __NO_RETURN __WEAK handler_name(void); \ +void handler_name(void) { \ + while(1); \ +} + +/* Exceptions */ +DEFAULT_IRQ_HANDLER(NMI_Handler) +DEFAULT_IRQ_HANDLER(HardFault_Handler) +DEFAULT_IRQ_HANDLER(MemManage_Handler) +DEFAULT_IRQ_HANDLER(BusFault_Handler) +DEFAULT_IRQ_HANDLER(UsageFault_Handler) +DEFAULT_IRQ_HANDLER(SecureFault_Handler) +DEFAULT_IRQ_HANDLER(SVC_Handler) +DEFAULT_IRQ_HANDLER(DebugMon_Handler) +DEFAULT_IRQ_HANDLER(PendSV_Handler) +DEFAULT_IRQ_HANDLER(SysTick_Handler) + +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_RESET_REQ_Handler) +DEFAULT_IRQ_HANDLER(NONSEC_WATCHDOG_Handler) +DEFAULT_IRQ_HANDLER(SLOWCLK_Timer_Handler) +DEFAULT_IRQ_HANDLER(TFM_TIMER0_IRQ_Handler) +DEFAULT_IRQ_HANDLER(TIMER1_Handler) +DEFAULT_IRQ_HANDLER(TIMER2_Handler) +DEFAULT_IRQ_HANDLER(MPC_Handler) +DEFAULT_IRQ_HANDLER(PPC_Handler) +DEFAULT_IRQ_HANDLER(MSC_Handler) +DEFAULT_IRQ_HANDLER(BRIDGE_ERROR_Handler) +DEFAULT_IRQ_HANDLER(MGMT_PPU_Handler) +DEFAULT_IRQ_HANDLER(SYS_PPU_Handler) +DEFAULT_IRQ_HANDLER(CPU0_PPU_Handler) +DEFAULT_IRQ_HANDLER(DEBUG_PPU_Handler) +DEFAULT_IRQ_HANDLER(TIMER3_AON_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_0_Handler) +DEFAULT_IRQ_HANDLER(CPU0_CTI_1_Handler) + +DEFAULT_IRQ_HANDLER(System_Timestamp_Counter_Handler) +DEFAULT_IRQ_HANDLER(UARTRX0_Handler) +DEFAULT_IRQ_HANDLER(UARTTX0_Handler) +DEFAULT_IRQ_HANDLER(UARTRX1_Handler) +DEFAULT_IRQ_HANDLER(UARTTX1_Handler) +DEFAULT_IRQ_HANDLER(UARTRX2_Handler) +DEFAULT_IRQ_HANDLER(UARTTX2_Handler) +DEFAULT_IRQ_HANDLER(UARTRX3_Handler) +DEFAULT_IRQ_HANDLER(UARTTX3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX4_Handler) +DEFAULT_IRQ_HANDLER(UARTTX4_Handler) +DEFAULT_IRQ_HANDLER(UART0_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART1_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART2_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART3_Combined_Handler) +DEFAULT_IRQ_HANDLER(UART4_Combined_Handler) +DEFAULT_IRQ_HANDLER(UARTOVF_Handler) +DEFAULT_IRQ_HANDLER(ETHERNET_Handler) +DEFAULT_IRQ_HANDLER(I2S_Handler) +DEFAULT_IRQ_HANDLER(TOUCH_SCREEN_Handler) +DEFAULT_IRQ_HANDLER(USB_Handler) +DEFAULT_IRQ_HANDLER(SPI_ADC_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD0_Handler) +DEFAULT_IRQ_HANDLER(SPI_SHIELD1_Handler) +DEFAULT_IRQ_HANDLER(ETHOS_U55_Handler) +#ifdef CORSTONE300_AN547 +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_1_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_2_Combined_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Error_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Terminal_Count_Handler) +DEFAULT_IRQ_HANDLER(DMA_Ch_3_Combined_Handler) +#endif +DEFAULT_IRQ_HANDLER(GPIO0_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_Combined_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO0_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO1_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_3_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_4_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_5_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_6_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_7_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_8_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_9_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_10_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_11_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_12_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_13_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_14_Handler) +DEFAULT_IRQ_HANDLER(GPIO2_15_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_0_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_1_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_2_Handler) +DEFAULT_IRQ_HANDLER(GPIO3_3_Handler) +DEFAULT_IRQ_HANDLER(UARTRX5_Handler) +DEFAULT_IRQ_HANDLER(UARTTX5_Handler) +DEFAULT_IRQ_HANDLER(UART5_Handler) +#ifdef CORSTONE300_FVP +DEFAULT_IRQ_HANDLER(ARM_VSI0_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI1_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI2_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI3_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI4_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI5_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI6_Handler) +DEFAULT_IRQ_HANDLER(ARM_VSI7_Handler) +#endif +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[]; + const VECTOR_TABLE_Type __VECTOR_TABLE[] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14: NMI Handler */ + HardFault_Handler, /* -13: Hard Fault Handler */ + MemManage_Handler, /* -12: MPU Fault Handler */ + BusFault_Handler, /* -11: Bus Fault Handler */ + UsageFault_Handler, /* -10: Usage Fault Handler */ + SecureFault_Handler, /* -9: Secure Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5: SVCall Handler */ + DebugMon_Handler, /* -4: Debug Monitor Handler */ + 0, /* Reserved */ + PendSV_Handler, /* -2: PendSV Handler */ + SysTick_Handler, /* -1: SysTick Handler */ + + NONSEC_WATCHDOG_RESET_REQ_Handler, /* 0: Non-Secure Watchdog Reset Request Handler */ + NONSEC_WATCHDOG_Handler, /* 1: Non-Secure Watchdog Handler */ + SLOWCLK_Timer_Handler, /* 2: SLOWCLK Timer Handler */ + TFM_TIMER0_IRQ_Handler, /* 3: TIMER 0 Handler */ + TIMER1_Handler, /* 4: TIMER 1 Handler */ + TIMER2_Handler, /* 5: TIMER 2 Handler */ + 0, /* 6: Reserved */ + 0, /* 7: Reserved */ + 0, /* 8: Reserved */ + MPC_Handler, /* 9: MPC Combined (Secure) Handler */ + PPC_Handler, /* 10: PPC Combined (Secure) Handler */ + MSC_Handler, /* 11: MSC Combined (Secure) Handler */ + BRIDGE_ERROR_Handler, /* 12: Bridge Error (Secure) Handler */ + 0, /* 13: Reserved */ + MGMT_PPU_Handler, /* 14: MGMT PPU Handler */ + SYS_PPU_Handler, /* 15: SYS PPU Handler */ + CPU0_PPU_Handler, /* 16: CPU0 PPU Handler */ + 0, /* 17: Reserved */ + 0, /* 18: Reserved */ + 0, /* 19: Reserved */ + 0, /* 20: Reserved */ + 0, /* 21: Reserved */ + 0, /* 22: Reserved */ + 0, /* 23: Reserved */ + 0, /* 24: Reserved */ + 0, /* 25: Reserved */ + DEBUG_PPU_Handler, /* 26: DEBUG PPU Handler */ + TIMER3_AON_Handler, /* 27: TIMER 3 AON Handler */ + CPU0_CTI_0_Handler, /* 28: CPU0 CTI IRQ 0 Handler */ + CPU0_CTI_1_Handler, /* 29: CPU0 CTI IRQ 1 Handler */ + 0, /* 30: Reserved */ + 0, /* 31: Reserved */ + + /* External interrupts */ + System_Timestamp_Counter_Handler, /* 32: System timestamp counter Handler */ + UARTRX0_Handler, /* 33: UART 0 RX Handler */ + UARTTX0_Handler, /* 34: UART 0 TX Handler */ + UARTRX1_Handler, /* 35: UART 1 RX Handler */ + UARTTX1_Handler, /* 36: UART 1 TX Handler */ + UARTRX2_Handler, /* 37: UART 2 RX Handler */ + UARTTX2_Handler, /* 38: UART 2 TX Handler */ + UARTRX3_Handler, /* 39: UART 3 RX Handler */ + UARTTX3_Handler, /* 40: UART 3 TX Handler */ + UARTRX4_Handler, /* 41: UART 4 RX Handler */ + UARTTX4_Handler, /* 42: UART 4 TX Handler */ + UART0_Combined_Handler, /* 43: UART 0 Combined Handler */ + UART1_Combined_Handler, /* 44: UART 1 Combined Handler */ + UART2_Combined_Handler, /* 45: UART 2 Combined Handler */ + UART3_Combined_Handler, /* 46: UART 3 Combined Handler */ + UART4_Combined_Handler, /* 47: UART 4 Combined Handler */ + UARTOVF_Handler, /* 48: UART 0, 1, 2, 3, 4 & 5 Overflow Handler */ + ETHERNET_Handler, /* 49: Ethernet Handler */ + I2S_Handler, /* 50: Audio I2S Handler */ + TOUCH_SCREEN_Handler, /* 51: Touch Screen Handler */ + USB_Handler, /* 52: USB Handler */ + SPI_ADC_Handler, /* 53: SPI ADC Handler */ + SPI_SHIELD0_Handler, /* 54: SPI (Shield 0) Handler */ + SPI_SHIELD1_Handler, /* 55: SPI (Shield 0) Handler */ + ETHOS_U55_Handler, /* 56: Ethos-U55 Handler */ +#ifdef CORSTONE300_AN547 + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + DMA_Ch_1_Error_Handler, /* 60: DMA Ch1 Error Handler */ + DMA_Ch_1_Terminal_Count_Handler, /* 61: DMA Ch1 Terminal Count Handler */ + DMA_Ch_1_Combined_Handler, /* 62: DMA Ch1 Combined Handler */ + DMA_Ch_2_Error_Handler, /* 63: DMA Ch2 Error Handler */ + DMA_Ch_2_Terminal_Count_Handler, /* 64: DMA Ch2 Terminal Count Handler */ + DMA_Ch_2_Combined_Handler, /* 65: DMA Ch2 Combined Handler */ + DMA_Ch_3_Error_Handler, /* 66: DMA Ch3 Error Handler */ + DMA_Ch_3_Terminal_Count_Handler, /* 67: DMA Ch3 Terminal Count Handler */ + DMA_Ch_3_Combined_Handler, /* 68: DMA Ch3 Combined Handler */ +#else + 0, /* 57: Reserved */ + 0, /* 58: Reserved */ + 0, /* 59: Reserved */ + 0, /* 60: Reserved */ + 0, /* 61: Reserved */ + 0, /* 62: Reserved */ + 0, /* 63: Reserved */ + 0, /* 64: Reserved */ + 0, /* 65: Reserved */ + 0, /* 66: Reserved */ + 0, /* 67: Reserved */ + 0, /* 68: Reserved */ +#endif + GPIO0_Combined_Handler, /* 69: GPIO 0 Combined Handler */ + GPIO1_Combined_Handler, /* 70: GPIO 1 Combined Handler */ + GPIO2_Combined_Handler, /* 71: GPIO 2 Combined Handler */ + GPIO3_Combined_Handler, /* 72: GPIO 3 Combined Handler */ + GPIO0_0_Handler, /* 73: GPIO0 Pin 0 Handler */ + GPIO0_1_Handler, /* 74: GPIO0 Pin 1 Handler */ + GPIO0_2_Handler, /* 75: GPIO0 Pin 2 Handler */ + GPIO0_3_Handler, /* 76: GPIO0 Pin 3 Handler */ + GPIO0_4_Handler, /* 77: GPIO0 Pin 4 Handler */ + GPIO0_5_Handler, /* 78: GPIO0 Pin 5 Handler */ + GPIO0_6_Handler, /* 79: GPIO0 Pin 6 Handler */ + GPIO0_7_Handler, /* 80: GPIO0 Pin 7 Handler */ + GPIO0_8_Handler, /* 81: GPIO0 Pin 8 Handler */ + GPIO0_9_Handler, /* 82: GPIO0 Pin 9 Handler */ + GPIO0_10_Handler, /* 83: GPIO0 Pin 10 Handler */ + GPIO0_11_Handler, /* 84: GPIO0 Pin 11 Handler */ + GPIO0_12_Handler, /* 85: GPIO0 Pin 12 Handler */ + GPIO0_13_Handler, /* 86: GPIO0 Pin 13 Handler */ + GPIO0_14_Handler, /* 87: GPIO0 Pin 14 Handler */ + GPIO0_15_Handler, /* 88: GPIO0 Pin 15 Handler */ + GPIO1_0_Handler, /* 89: GPIO1 Pin 0 Handler */ + GPIO1_1_Handler, /* 90: GPIO1 Pin 1 Handler */ + GPIO1_2_Handler, /* 91: GPIO1 Pin 2 Handler */ + GPIO1_3_Handler, /* 92: GPIO1 Pin 3 Handler */ + GPIO1_4_Handler, /* 93: GPIO1 Pin 4 Handler */ + GPIO1_5_Handler, /* 94: GPIO1 Pin 5 Handler */ + GPIO1_6_Handler, /* 95: GPIO1 Pin 6 Handler */ + GPIO1_7_Handler, /* 96: GPIO1 Pin 7 Handler */ + GPIO1_8_Handler, /* 97: GPIO1 Pin 8 Handler */ + GPIO1_9_Handler, /* 98: GPIO1 Pin 9 Handler */ + GPIO1_10_Handler, /* 99: GPIO1 Pin 10 Handler */ + GPIO1_11_Handler, /* 100: GPIO1 Pin 11 Handler */ + GPIO1_12_Handler, /* 101: GPIO1 Pin 12 Handler */ + GPIO1_13_Handler, /* 102: GPIO1 Pin 13 Handler */ + GPIO1_14_Handler, /* 103: GPIO1 Pin 14 Handler */ + GPIO1_15_Handler, /* 104: GPIO1 Pin 15 Handler */ + GPIO2_0_Handler, /* 105: GPIO2 Pin 0 Handler */ + GPIO2_1_Handler, /* 106: GPIO2 Pin 1 Handler */ + GPIO2_2_Handler, /* 107: GPIO2 Pin 2 Handler */ + GPIO2_3_Handler, /* 108: GPIO2 Pin 3 Handler */ + GPIO2_4_Handler, /* 109: GPIO2 Pin 4 Handler */ + GPIO2_5_Handler, /* 110: GPIO2 Pin 5 Handler */ + GPIO2_6_Handler, /* 111: GPIO2 Pin 6 Handler */ + GPIO2_7_Handler, /* 112: GPIO2 Pin 7 Handler */ + GPIO2_8_Handler, /* 113: GPIO2 Pin 8 Handler */ + GPIO2_9_Handler, /* 114: GPIO2 Pin 9 Handler */ + GPIO2_10_Handler, /* 115: GPIO2 Pin 10 Handler */ + GPIO2_11_Handler, /* 116: GPIO2 Pin 11 Handler */ + GPIO2_12_Handler, /* 117: GPIO2 Pin 12 Handler */ + GPIO2_13_Handler, /* 118: GPIO2 Pin 13 Handler */ + GPIO2_14_Handler, /* 119: GPIO2 Pin 14 Handler */ + GPIO2_15_Handler, /* 120: GPIO2 Pin 15 Handler */ + GPIO3_0_Handler, /* 121: GPIO3 Pin 0 Handler */ + GPIO3_1_Handler, /* 122: GPIO3 Pin 1 Handler */ + GPIO3_2_Handler, /* 123: GPIO3 Pin 2 Handler */ + GPIO3_3_Handler, /* 124: GPIO3 Pin 3 Handler */ + UARTRX5_Handler, /* 125: UART 5 RX Interrupt */ + UARTTX5_Handler, /* 126: UART 5 TX Interrupt */ + UART5_Handler, /* 127: UART 5 combined Interrupt */ + 0, /* 128: Reserved */ + 0, /* 129: Reserved */ + 0, /* 130: Reserved */ +#ifdef CORSTONE300_FVP + 0, /* 131: Reserved */ + 0, /* 132: Reserved */ + 0, /* 133: Reserved */ + 0, /* 134: Reserved */ + 0, /* 135: Reserved */ + 0, /* 136: Reserved */ + 0, /* 137: Reserved */ + 0, /* 138: Reserved */ + 0, /* 139: Reserved */ + 0, /* 140: Reserved */ + 0, /* 141: Reserved */ + 0, /* 142: Reserved */ + 0, /* 143: Reserved */ + 0, /* 144: Reserved */ + 0, /* 145: Reserved */ + 0, /* 146: Reserved */ + 0, /* 147: Reserved */ + 0, /* 148: Reserved */ + 0, /* 149: Reserved */ + 0, /* 150: Reserved */ + 0, /* 151: Reserved */ + 0, /* 152: Reserved */ + 0, /* 153: Reserved */ + 0, /* 154: Reserved */ + 0, /* 155: Reserved */ + 0, /* 156: Reserved */ + 0, /* 157: Reserved */ + 0, /* 158: Reserved */ + 0, /* 159: Reserved */ + 0, /* 160: Reserved */ + 0, /* 161: Reserved */ + 0, /* 162: Reserved */ + 0, /* 163: Reserved */ + 0, /* 164: Reserved */ + 0, /* 165: Reserved */ + 0, /* 166: Reserved */ + 0, /* 167: Reserved */ + 0, /* 168: Reserved */ + 0, /* 169: Reserved */ + 0, /* 170: Reserved */ + 0, /* 171: Reserved */ + 0, /* 172: Reserved */ + 0, /* 173: Reserved */ + 0, /* 174: Reserved */ + 0, /* 175: Reserved */ + 0, /* 176: Reserved */ + 0, /* 177: Reserved */ + 0, /* 178: Reserved */ + 0, /* 179: Reserved */ + 0, /* 180: Reserved */ + 0, /* 181: Reserved */ + 0, /* 182: Reserved */ + 0, /* 183: Reserved */ + 0, /* 184: Reserved */ + 0, /* 185: Reserved */ + 0, /* 186: Reserved */ + 0, /* 187: Reserved */ + 0, /* 188: Reserved */ + 0, /* 189: Reserved */ + 0, /* 190: Reserved */ + 0, /* 191: Reserved */ + 0, /* 192: Reserved */ + 0, /* 193: Reserved */ + 0, /* 194: Reserved */ + 0, /* 195: Reserved */ + 0, /* 196: Reserved */ + 0, /* 197: Reserved */ + 0, /* 198: Reserved */ + 0, /* 199: Reserved */ + 0, /* 200: Reserved */ + 0, /* 201: Reserved */ + 0, /* 202: Reserved */ + 0, /* 203: Reserved */ + 0, /* 204: Reserved */ + 0, /* 205: Reserved */ + 0, /* 206: Reserved */ + 0, /* 207: Reserved */ + 0, /* 208: Reserved */ + 0, /* 209: Reserved */ + 0, /* 210: Reserved */ + 0, /* 211: Reserved */ + 0, /* 212: Reserved */ + 0, /* 213: Reserved */ + 0, /* 214: Reserved */ + 0, /* 215: Reserved */ + 0, /* 216: Reserved */ + 0, /* 217: Reserved */ + 0, /* 218: Reserved */ + 0, /* 219: Reserved */ + 0, /* 220: Reserved */ + 0, /* 221: Reserved */ + 0, /* 222: Reserved */ + 0, /* 223: Reserved */ + ARM_VSI0_Handler, /* 224: VSI 0 Handler */ + ARM_VSI1_Handler, /* 225: VSI 1 Handler */ + ARM_VSI2_Handler, /* 226: VSI 2 Handler */ + ARM_VSI3_Handler, /* 227: VSI 3 Handler */ + ARM_VSI4_Handler, /* 228: VSI 4 Handler */ + ARM_VSI5_Handler, /* 229: VSI 5 Handler */ + ARM_VSI6_Handler, /* 230: VSI 6 Handler */ + ARM_VSI7_Handler, /* 231: VSI 7 Handler */ +#endif +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +void Reset_Handler(void) +{ + __set_PSP((uint32_t)(&__INITIAL_SP)); + + __set_MSPLIM((uint32_t)(&__STACK_LIMIT)); + __set_PSPLIM((uint32_t)(&__STACK_LIMIT)); + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + __TZ_set_STACKSEAL_S((uint32_t *)(&__STACK_SEAL)); +#endif + + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c new file mode 100644 index 0000000..20b624e --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 new file mode 100644 index 0000000..20b624e --- /dev/null +++ b/board/Corstone-300/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1 @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2009-2023 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + * This file is derivative of CMSIS V5.9.0 system_ARMCM55.c + * Git SHA: 2b7495b8535bdcb306dac29b9ded4cfb679d7e5c + */ + +#include "SSE300MPS3.h" + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + #define XTAL (32000000UL) + #define SYSTEM_CLOCK (XTAL) + #define PERIPHERAL_CLOCK (25000000UL) + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ +extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; +uint32_t PeripheralClock = PERIPHERAL_CLOCK; + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); +#endif + +#if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ + + /* Set low-power state for PDEPU */ + /* 0b00 | ON, PDEPU is not in low-power state */ + /* 0b01 | ON, but the clock is off */ + /* 0b10 | RET(ention) */ + /* 0b11 | OFF */ + + /* Clear ELPSTATE, value is 0b11 on Cold reset */ + PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk); + + /* Favor best FP/MVE performance by default, avoid EPU switch-ON delays */ + /* PDEPU ON, Clock OFF */ + PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos; +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Enable Loop and branch info cache */ + SCB->CCR |= SCB_CCR_LOB_Msk; + __DSB(); + __ISB(); + + /* Disable cache, because of BL2->Secure change. + If cache is enabled, then code decompression can fail or cause uncertain + behaviour after switching to main. + If cache needed to be Enabled before decompression, make sure to Clean + and Invalidate it at the begining of main(..)! + + If so, use: + SCB_InvalidateICache(); // I cache cannot be cleaned + SCB_CleanInvalidateDCache(); + */ + SCB_DisableICache(); + SCB_DisableDCache(); + + SystemCoreClock = SYSTEM_CLOCK; + PeripheralClock = PERIPHERAL_CLOCK; +} diff --git a/board/Corstone-300/ethos_setup.c b/board/Corstone-300/ethos_setup.c new file mode 100644 index 0000000..455574e --- /dev/null +++ b/board/Corstone-300/ethos_setup.c @@ -0,0 +1,103 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + + #include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "ethosu_driver.h" +#include "main.h" + +#if defined(ETHOSU65) || defined(ETHOSU85) +/* Define Ethos-U NPU cache buffer size */ +#ifndef ETHOS_CACHE_BUF_SIZE +#define ETHOS_CACHE_BUF_SIZE 393216 +#endif + +/* Define Ethos-U cache buffer alignment */ +#ifndef ETHOS_CACHE_BUF_ALIGNMENT +#define ETHOS_CACHE_BUF_ALIGNMENT 32 +#endif + +/* Define Ethos-U NPU cache buffer attributes */ +#ifndef ETHOS_CACHE_BUF_ATTRIBUTES +#define ETHOS_CACHE_BUF_ATTRIBUTES __attribute__((section("ethos_cache_buf"), aligned(ETHOS_CACHE_BUF_ALIGNMENT))) +#endif +#endif + +/* Define Ethos-U NPU security mode */ +#ifndef ETHOS_SECURE_ENABLE +#define ETHOS_SECURE_ENABLE 1 +#endif + +/* Define Ethos-U NPU privilege mode */ +#ifndef ETHOS_PRIVILEGE_ENABLE +#define ETHOS_PRIVILEGE_ENABLE 1 +#endif + +/* Ethos NPU driver instance. */ +static struct ethosu_driver EthosDriver; + +#if defined(ETHOSU65) || defined(ETHOSU85) +static uint8_t ethos_cache[ETHOS_CACHE_BUF_SIZE] ETHOS_CACHE_BUF_ATTRIBUTES; +#endif + +/* + Ethos NPU interrupt handler. +*/ +void ETHOS_U55_Handler(void) { + ethosu_irq_handler(&EthosDriver); +} + +/* + Initialize the Ethos NPU driver. +*/ +void ethos_setup (void) { + void * const ethos_base_addr = (void *)ETHOS_U55_APB_BASE_S; + struct ethosu_hw_info hw_info; + int rval; + + /* Initialize Ethos-U NPU driver. */ + rval = ethosu_init(&EthosDriver, /* Ethos-U device driver */ + ethos_base_addr, /* Ethos-U base address */ + #if defined(ETHOSU65) || defined(ETHOSU85) + ethos_cache, /* Cache memory pointer */ + sizeof(ethos_cache), /* Cache memory size */ + #else + 0, /* Cache memory pointer */ + 0, /* Cache memory size */ + #endif + ETHOS_SECURE_ENABLE, /* Secure enable */ + ETHOS_PRIVILEGE_ENABLE); /* Privileged mode */ + if (rval != 0) { + printf("Failed to initialize Arm Ethos-U driver\n"); + } + else { + NVIC_EnableIRQ(ETHOS_U55_IRQn); + + ethosu_get_hw_info(&EthosDriver, &hw_info); + + printf("Ethos-U version info:\n"); + printf("\tArch: v%u.%u.%u\n", hw_info.version.arch_major_rev, + hw_info.version.arch_minor_rev, + hw_info.version.arch_patch_rev); + printf("\tMACs/cc: %u\n", (uint32_t)(1 << hw_info.cfg.macs_per_cc)); + printf("\tCmd stream: v%u\n", hw_info.cfg.cmd_stream_version); + } +} diff --git a/board/Corstone-300/fvp_config.txt b/board/Corstone-300/fvp_config.txt new file mode 100644 index 0000000..2bbc46f --- /dev/null +++ b/board/Corstone-300/fvp_config.txt @@ -0,0 +1,35 @@ +# Parameters: +# instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] +#------------------------------------------------------------------------------ +ethosu.num_macs=256 # (int , init-time) default = '0x80' : Number of 8x8 MACs performed per cycle (32, 64, 128, or 256). : [0x20:0x100] + # NOTE: must match the Vela target the model was compiled for: + # --accelerator-config ethos-u55-256 in cmsis-executorch.cbuild-mlops.yml + # (the E7's HP core NPU), otherwise the command stream is rejected + # at runtime ("npu.macs_per_cc != optimizer.macs_per_cc"). +ethosu.extra_args=--fast # (string, init-time) default = '' : To activate fast processing mode, which significantly improves the performance of the model, set this parameter to "--fast". In fast mode, NPU performance counters are not representative of counters on real hardware. + # NOTE: the FVP times nothing like the board anyway; fast mode + # makes a YOLO26n frame take seconds instead of minutes. +cpu0.INITSVTOR=0x70000000 # (int , init-time) default = '0x10000000' : Secure vector-table offset at reset +mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0x70000000 # (int, init-time) default = '0x10000000' : Reset int32_t for INITSVTOR. Should match cpu.INITSVTOR + # NOTE: the application, its vector table (__Vectors) first, is + # linked to the DDR4 at 0x70000000 (__ROM0_BASE in regions_SSE-300.h), + # but the FVP default points at the ITCM, where nothing is loaded. + # The first boot works anyway because the ELF loader sets the PC -- + # but any debugger reset reboots from INITSVTOR and fetches a garbage + # MSP/PC. Pin both to the real vector table so resets survive. +cpu0.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps + # NOTE: stdio is retargeted to semihosting (board/Corstone-300/ + # retarget_stdio.c); the FVP serves it directly on its stdout, + # and the application's exit() stops the model. +mps3_board.telnetterminal0.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal0.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal1.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal1.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal2.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal2.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.telnetterminal5.quiet=1 # (bool , init-time) default = '0' : Avoid output on stdout/stderr +mps3_board.telnetterminal5.start_telnet=0 # (bool , init-time) default = '1' : Start telnet if nothing connected +mps3_board.uart0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) +mps3_board.uart0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output +mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation +#------------------------------------------------------------------------------ diff --git a/board/Corstone-300/main.c b/board/Corstone-300/main.c new file mode 100644 index 0000000..dd8b66d --- /dev/null +++ b/board/Corstone-300/main.c @@ -0,0 +1,69 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2024-2026 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Corstone-300 FVP bring-up for the traffic counter: stdio over semihosting, + * the Ethos-U55 driver, then the application in an RTX thread, as on the + * AppKit-E7 (its threads and the Ethos-U driver's semaphores need RTX). + *---------------------------------------------------------------------------*/ + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "main.h" + +#ifdef RTE_CMSIS_RTOS2 +#include "cmsis_os2.h" + +#ifndef APP_THREAD_STACK_SIZE +#define APP_THREAD_STACK_SIZE 0x8000 +#endif +static uint64_t app_thread_stack[APP_THREAD_STACK_SIZE / 8]; +static const osThreadAttr_t app_thread_attr = { + .name = "app", + .stack_mem = app_thread_stack, + .stack_size = sizeof(app_thread_stack), + .priority = osPriorityNormal, +}; + +static void app_thread (void *argument) { + (void)argument; + app_main(); + for (;;) { + osDelay(osWaitForever); + } +} +#endif + +int main (void) { + + /* Initialize STDIO */ + stdio_init(); + + #if defined(ETHOSU_ARCH) + /* Initialize Ethos NPU */ + ethos_setup(); + #endif + +#ifdef RTE_CMSIS_RTOS2 + osKernelInitialize(); + osThreadNew(app_thread, NULL, &app_thread_attr); + osKernelStart(); + for (;;) {} +#else + return (app_main()); +#endif +} diff --git a/board/Corstone-300/main.h b/board/Corstone-300/main.h new file mode 100644 index 0000000..6e2048e --- /dev/null +++ b/board/Corstone-300/main.h @@ -0,0 +1,38 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2020-2025 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + *---------------------------------------------------------------------------*/ + +#ifndef MAIN_H__ +#define MAIN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Prototypes */ +extern int app_main (void); +extern int stdio_init (void); + +#if defined(ETHOSU_ARCH) +extern void ethos_setup (void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/board/Corstone-300/regions_SSE-300.h b/board/Corstone-300/regions_SSE-300.h new file mode 100644 index 0000000..5c5f876 --- /dev/null +++ b/board/Corstone-300/regions_SSE-300.h @@ -0,0 +1,82 @@ +// Copyright 2026 Arm Limited and/or its affiliates. +// SPDX-License-Identifier: Apache-2.0 +// +// Memory regions of the Corstone-300 FVP for the traffic counter, for the +// CMSIS-Toolbox linker script template (RTE/Device/SSE-300-MPS3/). All of +// the read-only part (code, the 2.3 MB program, the 0.5 MB test image) goes +// into __ROM0, all of the read-write part (the 1.25 MB NPU scratch, the two +// 0.5 MB input slots, the method pool, the thread stacks) into __RAM0: both +// in the secure alias of DDR4 block 1 (0x70000000, 256 MB), which the CPU and +// the NPU both reach. fvp_config.txt points the reset vector table there. +#ifndef REGIONS_SSE_300_H +#define REGIONS_SSE_300_H + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- +//------ With VS Code: Open Preview for Configuration Wizard ------------------- + +// ROM Configuration +// ======================= +// __ROM0 +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Contains Startup and Vector Table +#define __ROM0_BASE 0x70000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __ROM0_SIZE 0x01000000 +// + +// __ROM1 +#define __ROM1_BASE 0 +#define __ROM1_SIZE 0 +// + +// __ROM2 +#define __ROM2_BASE 0 +#define __ROM2_SIZE 0 +// + +// __ROM3 +#define __ROM3_BASE 0 +#define __ROM3_SIZE 0 +// + +// + +// RAM Configuration +// ======================= +// __RAM0 +// Base address <0x0-0xFFFFFFFF:8> +// Defines base address of memory region. +// Contains uninitialized RAM, Stack, and Heap +#define __RAM0_BASE 0x71000000 +// Region size [bytes] <0x0-0xFFFFFFFF:8> +// Defines size of memory region. +#define __RAM0_SIZE 0x01000000 +// + +// __RAM1 +#define __RAM1_BASE 0 +#define __RAM1_SIZE 0 +// + +// __RAM2 +#define __RAM2_BASE 0 +#define __RAM2_SIZE 0 +// + +// __RAM3 +#define __RAM3_BASE 0 +#define __RAM3_SIZE 0 +// + +// + +// Stack / Heap Configuration +// Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +// Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +#define __STACK_SIZE 0x00010000 +#define __HEAP_SIZE 0x00018000 +// + +#endif /* REGIONS_SSE_300_H */ diff --git a/board/Corstone-300/retarget_stdio.c b/board/Corstone-300/retarget_stdio.c new file mode 100644 index 0000000..1d3acf8 --- /dev/null +++ b/board/Corstone-300/retarget_stdio.c @@ -0,0 +1,101 @@ +/*--------------------------------------------------------------------------- + * Copyright 2026 Arm Limited and/or its affiliates. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: retarget_stdio.c + * Purpose: Retarget stdio to Arm semihosting + * + * CMSIS-Compiler STDOUT/STDERR/STDIN:Custom backend. The CMSIS-Compiler CORE + * component provides the toolchain-specific low-level retarget (newlib _write + * for GCC) and routes every character here. Characters go out over Arm + * semihosting (BKPT 0xAB), which the FVP serves directly on its stdout -- + * no UART model, base address, or driver involved. Requires + * cpu0.semihosting-enable=1 (see fvp_config.txt). exit() ends the simulation + * through semihosting too (_sys_exit below). + *---------------------------------------------------------------------------*/ + +/* Semihosting operation numbers (Arm semihosting specification). */ +#define SYS_WRITEC 0x03 +#define SYS_READC 0x07 +#define SYS_EXIT 0x18 + +/* SYS_EXIT reason: the application exited (the model then stops). */ +#define ADP_Stopped_ApplicationExit 0x20026 + +static int semihosting_call (int op, void *param) { + register int r0 __asm__("r0") = op; + register void *r1 __asm__("r1") = param; + __asm__ volatile ("bkpt 0xAB" : "+r"(r0) : "r"(r1) : "memory"); + return r0; +} + +/** + Initialize stdio + + \return 0 on success, or -1 on error. +*/ +int stdio_init (void) { + /* Semihosting needs no initialization. */ + return 0; +} + +/** + Put a character to the stderr + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stderr_putchar (int ch) { + char c = (char)ch; + (void)semihosting_call(SYS_WRITEC, &c); + return ch; +} + +/** + Put a character to the stdout + + \param[in] ch Character to output + \return The character written, or -1 on write error. +*/ +int stdout_putchar (int ch) { + char c = (char)ch; + (void)semihosting_call(SYS_WRITEC, &c); + return ch; +} + +/** + Get a character from the stdio + + \return The next character from the input, or -1 on read error. +*/ +int stdin_getchar (void) { + return semihosting_call(SYS_READC, 0); +} + +#if defined(__ARMCC_VERSION) +/** + Exit the program: Arm Compiler's C library calls this from exit(). The + semihosting SYS_EXIT stops the FVP; the 32-bit call carries no status. + + \param[in] return_code Exit status +*/ +__attribute__((noreturn)) void _sys_exit (int return_code) { + (void)return_code; + for (;;) { + (void)semihosting_call(SYS_EXIT, (void *)ADP_Stopped_ApplicationExit); + } +} +#endif diff --git a/cmsis-executorch.cbuild-pack.yml b/cmsis-executorch.cbuild-pack.yml new file mode 100644 index 0000000..0eb2a9b --- /dev/null +++ b/cmsis-executorch.cbuild-pack.yml @@ -0,0 +1,31 @@ +cbuild-pack: + resolved-packs: + - resolved-pack: ARM::CMSIS@6.3.0 + selected-by-pack: + - ARM::CMSIS + - ARM::CMSIS@^6.2.0 + - resolved-pack: ARM::CMSIS-Compiler@2.3.0 + selected-by-pack: + - ARM::CMSIS-Compiler + - ARM::CMSIS-Compiler@^2.1.0 + - resolved-pack: ARM::CMSIS-RTX@5.9.1 + selected-by-pack: + - ARM::CMSIS-RTX@^5.9.1 + - resolved-pack: ARM::SDS@3.1.0 + selected-by-pack: + - ARM::SDS@^3.1.0 + - resolved-pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + selected-by-pack: + - ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + - resolved-pack: ARM::ethos-u-core-driver@1.26.2 + selected-by-pack: + - ARM::ethos-u-core-driver@^1.26.2 + - resolved-pack: AlifSemiconductor::Ensemble@2.2.0 + selected-by-pack: + - AlifSemiconductor::Ensemble@^2.2.0-0 + - resolved-pack: Keil::MDK-Middleware@8.3.0 + selected-by-pack: + - Keil::MDK-Middleware@^8.3.0 + - resolved-pack: PyTorch::ExecuTorch@1.5.1 + selected-by-pack: + - PyTorch::ExecuTorch@1.5.1 diff --git a/cmsis-executorch.csolution.yml b/cmsis-executorch.csolution.yml new file mode 100644 index 0000000..18bec15 --- /dev/null +++ b/cmsis-executorch.csolution.yml @@ -0,0 +1,139 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# Traffic counter with ExecuTorch on the Ethos-U55: Ultralytics YOLO26n finds +# the vehicles in each frame, a tracker counts them as they cross a line +# (traffic/traffic.cproject.yml, documentation/traffic-counter.md). Two +# targets with the same Cortex-M55 + Ethos-U55-256 pair and the same AI layer: +# the Alif Ensemble E7 AppKit (target-type AppKit-E7), and the Corstone-300 +# FVP (target-type SSE-300-U55), which runs the detector on the test image +# without a board. Three steps build it: +# +# cbuild setup cmsis-executorch.csolution.yml --active AppKit-E7 +# python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml +# cbuild cmsis-executorch.csolution.yml --active AppKit-E7 +# +# The `mlops:` node below makes `cbuild setup` emit the *.cbuild-mlops.yml; +# create_ai_layer.py reads the NPU and Vela settings from it, exports the model +# from PyTorch in the project's venv and writes the AI layer. +solution: + created-for: CMSIS-Toolbox@2.14.1 + cdefault: + compiler: AC6 + + packs: + # Pinned exactly: the pack's C++ runtime and the Python exporter pinned in + # requirements.txt must be the same ExecuTorch version, or the .pte fails + # to load. `cbuild setup --packs` fetches it from the public index. + - pack: PyTorch::ExecuTorch@1.5.1 + - pack: ARM::CMSIS + - pack: ARM::CMSIS-Compiler + # BSP of the Corstone-300 FVP target. The layer lists it too; naming it + # here keeps the mlops: simulator target resolvable when the AppKit-E7 is + # the active target-type. + - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 + # DFP + BSP of the Alif Ensemble E7 AppKit, and the Vela configuration + # of its NPUs (ensemble_vela.ini). + - pack: AlifSemiconductor::Ensemble@^2.2.0-0 + + target-types: + # Alif Ensemble E7 AppKit (AK-E7-AIML, Gen 2): the Cortex-M55 HP core with + # its Ethos-U55-256, the 480x800 panel, an MT9M114 camera module. The + # Secure Enclave has to boot the HP core from its MRAM region: + # .alif/M55_HP_mram_cfg_e7.json, the "Install M55_HP debug stubs (AppKit-E7)" task. + - type: AppKit-E7 + board: Alif Semiconductor::AppKit-E7-AIML + device: Alif Semiconductor::AE722F80F55D5LS:M55_HP + variables: + - Board-Layer: $SolutionDir()$/board/AppKit-E7/Board-Traffic.clayer.yml + - AI-Layer: $SolutionDir()$/ai_layer/ai_layer.clayer.yml + target-set: + - set: + images: + - project-context: traffic.Release + debugger: + name: J-Link Server + # SWD at 4 MHz is the pack's setting for the Ensemble + # kits. With JTAG the generated "CMSIS Load" task blocks on + # JLinkExe's interactive JTAG-chain prompt. + protocol: swd + clock: 4000000 + start-pname: M55_HP + + # Corstone-300 (SSE-300) with a Cortex-M55 and an Ethos-U55-256, the NPU + # configuration of the E7's HP core, simulated on the Arm FVP. No camera, + # panel or SDS: the traffic counter runs the test image through the + # detector and the tracker for a few frames, prints the detections and + # ends the simulation (board/Corstone-300/Board-Traffic.clayer.yml). + - type: SSE-300-U55 + board: ARM::V2M-MPS3-SSE-300-FVP + device: ARM::SSE-300-MPS3 + variables: + - Board-Layer: $SolutionDir()$/board/Corstone-300/Board-Traffic.clayer.yml + - AI-Layer: $SolutionDir()$/ai_layer/ai_layer.clayer.yml + target-set: + - set: + images: + - project-context: traffic.Release + debugger: + name: Arm-FVP + # The model is its own GDB server (plugins/GDBServer.so, MDK FVP + # models 11.32.23+). fvp.sh resolves that plugin when VS Code was + # not started from a `vcpkg activate` shell, line-buffers the + # model's stdout so the debug adapter sees the "Listening" banner, + # and on macOS runs the model in Docker (Arm ships no macOS build). + # On Windows point this straight at FVP_Corstone_SSE-300_Ethos-U55.exe. + model: ${workspaceFolder}/.vscode/fvp.sh + config-file: board/Corstone-300/fvp_config.txt + args: "--simlimit 600" + + misc: + # CMSIS-Toolbox 2.14.1 passes -mfpu=fpv5-sp-d16 to Clang for the Cortex-M55, + # a single-precision FPU on a core with a double-precision one and MVE; + # LLVM crashes on some kernels with that combination. The later option + # wins, so name the FPU explicitly (newer toolboxes leave it to -mcpu). + - for-compiler: CLANG + C-CPP: + - -mfpu=fp-armv8-fullfp16-d16 + ASM: + - -mfpu=fp-armv8-fullfp16-d16 + + build-types: + - type: Debug + debug: on + optimize: debug + # Everything at full optimization, the packs' sources included (ExecuTorch + # runtime, Ethos-U driver, RTX, Alif drivers are -O1 in Debug). Debug + # information stays on: it costs nothing on the target. + - type: Release + debug: on + optimize: speed + + projects: + - project: ./traffic/traffic.cproject.yml + + # MLOps information: exported to cmsis-executorch.cbuild-mlops.yml by + # `cbuild setup ... --active AppKit-E7`. Retarget the NPU here and + # create_ai_layer.py picks it up on its next run. The FVP's Ethos-U55-256 + # runs the same command stream; Vela's system configuration only steers the + # scheduling for the E7's memories. + # https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information + mlops: + description: YOLO26n vehicle detector of the traffic counter for the Ethos-U55 + of the Ensemble E7's M55-HP + npu: + type: Ethos-U55 + vela: + # With the Ensemble pack in the solution, cbuild setup copies its Vela + # configuration to .cmsis/ensemble_vela.ini and emits it, together with + # --accelerator-config ethos-u55-256. RTSS_HP_SRAM_MRAM is the HP core's + # NPU in that file: the scratch in the SRAM, the weights in the MRAM. + system: RTSS_HP_SRAM_MRAM + memory: Shared_Sram + model: + clayer: $AI-Layer$ + name: TrafficVehicles + hardware: + target: AppKit-E7 # named explicitly: the released 2.14.1 detects no hardware target + simulator: + target: SSE-300-U55 diff --git a/create_ai_layer.py b/create_ai_layer.py new file mode 100644 index 0000000..99254de --- /dev/null +++ b/create_ai_layer.py @@ -0,0 +1,391 @@ +#!/usr/bin/env python3 +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +"""Create the AI layer of the CMSIS solution from its MLOps information. + + python create_ai_layer.py .cbuild-mlops.yml + +Step 2 of the three-step flow: + + cbuild setup .csolution.yml --active # writes *.cbuild-mlops.yml + python create_ai_layer.py .cbuild-mlops.yml # this script + cbuild .csolution.yml --active # compile and link + +The *.cbuild-mlops.yml is what CMSIS-Toolbox generates from the `mlops:` node +of the csolution. This script reads the NPU and Vela settings from it, exports +every method that model/model.py declares (quantize, delegate to Ethos-U, +compile with Vela) into one ExecuTorch program and writes the complete AI +layer into the directory of the clayer named under `model.clayer`: + + ai_layer.clayer.yml runtime, kernel utilities and registration, Ethos-U + backend and the operator components the exported + program actually uses + model_pte.c / .h the ExecuTorch program as a C array + model_io.h per method: input/output shapes, dtypes and the + quantization scale / zero point of each tensor + model.pte the program itself, for inspection + +The methods take and return quantized tensors (int8 or int16): the float +quantize / dequantize boundary that the Arm backend normally leaves on the CPU +is removed with ExecuTorch's quantize-IO passes, and the parameters the CPU +needs to produce and consume those tensors go into model_io.h. + +The script runs itself in the solution's .venv (see setup_venv.py) when it is +started with an interpreter that has no torch. +""" + +from __future__ import annotations + +import os +import re +import subprocess +import sys +from pathlib import Path + +HERE = Path(__file__).resolve().parent +PACK = "PyTorch::ExecuTorch" +SYMBOL = "model_pte" + + +def run_in_venv() -> None: + """Re-run under .venv when torch is not importable from this interpreter.""" + try: + import torch # noqa: F401 + except ImportError: + venv = HERE / ".venv" + python = venv / ("Scripts/python.exe" if os.name == "nt" else "bin/python") + # sys.prefix is the venv directory when running inside it (comparing + # interpreter paths does not work: venv symlinks resolve to the base). + if not python.is_file() or Path(sys.prefix).resolve() == venv.resolve(): + sys.exit( + f"torch is not installed for {sys.executable}.\n" + "Create the venv first: ./setup_venv.sh (Linux/macOS) or setup_venv.bat (Windows)" + ) + sys.exit(subprocess.run([str(python), __file__, *sys.argv[1:]]).returncode) + + +def pack_root() -> Path: + """The CMSIS pack root: $CMSIS_PACK_ROOT, else cpackget's default.""" + if env := os.environ.get("CMSIS_PACK_ROOT"): + return Path(env) + if os.name == "nt": + return Path(os.environ.get("LOCALAPPDATA", Path.home() / "AppData/Local")) / "Arm/Packs" + return Path(os.environ.get("XDG_CACHE_HOME", Path.home() / ".cache")) / "arm/packs" + + +def executorch_version(mlops_file: Path) -> str: + """The ExecuTorch pack version cbuild setup resolved, from .cbuild-pack.yml. + + The file is a lock file that keeps earlier resolutions, so an unversioned + selector can still point at an older pack; the entry selected by the + csolution's exact pin (PyTorch::ExecuTorch@) is the one in use. + """ + import yaml + + pack_file = mlops_file.with_name(mlops_file.name.replace(".cbuild-mlops.yml", ".cbuild-pack.yml")) + # After a version bump the lock file still lists the old pin as resolved + # by its own selector: the csolution's pin decides (the lock file may be a + # link into the solution directory). + for csolution in pack_file.resolve().parent.glob("*.csolution.yml"): + if pinned := re.search(rf"{re.escape(PACK)}@(\d+\.\d+\.\d+\S*)", csolution.read_text()): + return pinned.group(1) + fallback = None + for entry in yaml.safe_load(pack_file.read_text())["cbuild-pack"]["resolved-packs"]: + name, _, version = entry["resolved-pack"].partition("@") + selectors = entry.get("selected-by-pack", []) + if name != PACK or not selectors: + continue + if f"{PACK}@{version}" in selectors: + return version + fallback = fallback or version + if fallback: + return fallback + sys.exit(f"{pack_file}: {PACK} is not among the resolved packs") + + +def executorch_pack(version: str) -> Path: + """Directory of the installed ExecuTorch pack of that version.""" + vendor, _, pack = PACK.partition("::") + return pack_root() / vendor / pack / version + + +def compile_spec(mlops: dict, mlops_dir: Path): + """EthosUCompileSpec from the npu: and vela: nodes of the cbuild-mlops.yml.""" + from executorch.backends.arm.ethosu import EthosUCompileSpec + + npu = mlops.get("npu") + if not npu: + sys.exit("the solution's mlops: node names no NPU; this example needs an Ethos-U") + vela = mlops.get("vela", {}) + options = vela.get("options", "") + + def option(name: str) -> str | None: + found = re.search(rf"--{name}[= ](\S+)", options) + return found.group(1) if found else None + + target = option("accelerator-config") or f"{npu['type'].lower()}-{npu.get('macs', 256)}" + kwargs = { + "target": target, + "system_config": option("system-config"), + "memory_mode": option("memory-mode"), + } + if vela.get("ini"): + kwargs["config_ini"] = str(mlops_dir / vela["ini"]) + print(f"[ai_layer] Vela: {kwargs}") + return EthosUCompileSpec(**kwargs) + + +def quantize_method(spec, method): + """PT2E-quantize one method's module for the Ethos-U: int8, or int16 activations with int8 weights.""" + import torch + from executorch.backends.arm.quantizer import ( + EthosUQuantizer, + get_symmetric_a16w8_quantization_config, + get_symmetric_quantization_config, + ) + from torchao.quantization.pt2e.quantize_pt2e import convert_pt2e, prepare_pt2e + + graph = torch.export.export(method.module, method.example).module() + quantizer = EthosUQuantizer(spec) + if method.activation_bits == 16: + quantizer.set_global(get_symmetric_a16w8_quantization_config(is_per_channel=True)) + else: + quantizer.set_global(get_symmetric_quantization_config(is_per_channel=True)) + prepared = prepare_pt2e(graph, quantizer) + with torch.no_grad(): + for sample in method.samples: + prepared(*sample) # calibrate + return convert_pt2e(prepared) + + +def export_program(spec) -> tuple[bytes, dict]: + """Export every method of model/model.py into one .pte with quantized IO; returns the bytes and the IO description.""" + import torch + from executorch.backends.arm.ethosu import EthosUPartitioner + from executorch.exir import EdgeCompileConfig, ExecutorchBackendConfig, to_edge_transform_and_lower + from executorch.exir.passes.quantize_io_pass import quantize_input, quantize_output + + sys.path.insert(0, str(HERE / "model")) + from model import get_methods + + methods = get_methods() + programs = {m.name: torch.export.export(quantize_method(spec, m), m.example) for m in methods} + edge = to_edge_transform_and_lower( + programs, + partitioner={name: [EthosUPartitioner(spec)] for name in programs}, + compile_config=EdgeCompileConfig(_check_ir_validity=False), + ) + + # Move the float<->int boundary out of the program: the methods then take + # and return the quantized tensors the delegate works on, and the CPU side + # quantizes / dequantizes with the parameters recorded here. + io = {} + for method in methods: + program = edge.exported_program(method.name) + inputs, outputs = [], [] + for index, example in enumerate(method.example): + if not example.is_floating_point(): + # An integer input (the indices of a gather) is not quantized: + # it goes to the delegate as it is. Scale 1, zero point 0. + info = torch.iinfo(example.dtype) + inputs.append(_tensor_desc(tuple(example.shape), example.dtype, 1.0, 0, info.min, info.max)) + continue + scale, zp, qmin, qmax, dtype = quantize_input(program, index) + inputs.append(_tensor_desc(tuple(example.shape), dtype, scale, zp, qmin, qmax)) + for index in range(len(program.graph_signature.user_outputs)): + shape = _output_shape(program, index) + scale, zp, qmin, qmax, dtype = quantize_output(program, index) + outputs.append(_tensor_desc(shape, dtype, scale, zp, qmin, qmax)) + io[method.name] = {"inputs": inputs, "outputs": outputs} + + # Inputs stay the caller's buffers: without this the runtime plans memory + # for every input and memcpys the caller's tensors into it on each call + # (the 507 kB image of the traffic counter). Outputs stay planned. + from executorch.exir.passes import MemoryPlanningPass + + program = edge.to_executorch( + ExecutorchBackendConfig( + extract_delegate_segments=False, + memory_planning_pass=MemoryPlanningPass(alloc_graph_input=False), + ) + ) + return bytes(program.buffer), io + + +def _output_shape(program, index: int) -> tuple[int, ...]: + node = list(program.graph.output_node().args[0])[index] + return tuple(node.meta["val"].shape) + + +def _tensor_desc(shape, dtype, scale, zp, qmin, qmax) -> dict: + import torch + + ctype = {torch.int8: "int8_t", torch.int16: "int16_t", torch.uint8: "uint8_t", torch.int32: "int32_t"}[dtype] + return { + "shape": [int(d) for d in shape], + "dtype": str(dtype).replace("torch.", ""), + "ctype": ctype, + "scale": float(scale), + "zero_point": int(zp), + "qmin": int(qmin), + "qmax": int(qmax), + } + + +def components(pte: bytes, pack: Path) -> tuple[list[str], list[str]]: + """Runtime, kernel utils and registration, backend, plus one operator component per operator the .pte uses. + + The pack's "Extension Tensor" is not selected: its tensor_ptr_maker.cpp + needs std::random_device, which the LLVM embedded toolchain lacks; the + runner wraps its input in a TensorImpl instead. + """ + pdsc = next(pack.glob("*.pdsc")) + available = set(re.findall(r'Csub="([^"]+)"', pdsc.read_text())) + family = {"aten": "Portable", "quantized_decomposed": "Quantized", "cortex_m": "Cortex-M"} + + selected, unknown = set(), [] + for ns, op in sorted(set(re.findall(rb"(aten|quantized_decomposed|cortex_m)::(\w+)", pte))): + ns, op = ns.decode(), op.decode() + candidates = [ + f"{family[ns]} {op}", + f"{family[ns]} {re.sub(r'_(per_tensor|per_channel|byte|copy)$', '', op)}", + ] + if match := next((c for c in candidates if c in available), None): + selected.add(match) + else: + unknown.append(f"{ns}::{op}") + if unknown: + print(f"[ai_layer] warning: no component in {pack.name} for {unknown}", file=sys.stderr) + + return ["Runtime", "Kernel Utils", "Kernel Registration", "Backend EthosU"], sorted(selected) + + +def c_array(pte: bytes) -> str: + rows = [", ".join(f"0x{b:02x}" for b in pte[i : i + 16]) for i in range(0, len(pte), 16)] + return ( + "// Generated by create_ai_layer.py -- do not edit.\n" + f"__attribute__((aligned(16))) const unsigned char {SYMBOL}[] = {{\n " + + ",\n ".join(rows) + + f"\n}};\nconst unsigned long {SYMBOL}_size = sizeof({SYMBOL});\n" + ) + + +HEADER = f"""// Generated by create_ai_layer.py -- do not edit. +#pragma once +#ifdef __cplusplus +extern "C" {{ +#endif +extern const unsigned char {SYMBOL}[]; +extern const unsigned long {SYMBOL}_size; +#ifdef __cplusplus +}} +#endif +""" + + +def io_header(io: dict) -> str: + """model_io.h: one macro block per method tensor, C-preprocessor friendly.""" + lines = [ + "// Generated by create_ai_layer.py -- do not edit.", + "// Quantized IO of every method in model_pte: shapes, C types and the", + "// affine quantization q = round(x / SCALE) + ZERO_POINT the CPU applies.", + "#pragma once", + "", + ] + for name, desc in io.items(): + prefix = f"MODEL_{name.upper()}" + lines.append(f'#define {prefix}_METHOD "{name}"') + lines.append(f"#define {prefix}_NUM_INPUTS {len(desc['inputs'])}") + lines.append(f"#define {prefix}_NUM_OUTPUTS {len(desc['outputs'])}") + for kind in ("inputs", "outputs"): + for index, t in enumerate(desc[kind]): + p = f"{prefix}_{kind[:-1].upper()}{index}" + lines.append(f"#define {p}_NDIM {len(t['shape'])}") + lines.append(f"#define {p}_SHAPE {{{', '.join(str(d) for d in t['shape'])}}}") + lines.append(f"#define {p}_NUMEL {_numel(t['shape'])}") + lines.append(f"#define {p}_CTYPE {t['ctype']}") + lines.append(f"#define {p}_DTYPE_{t['dtype'].upper()} 1") + lines.append(f"#define {p}_SCALE {t['scale']!r}f") + lines.append(f"#define {p}_ZERO_POINT {t['zero_point']}") + lines.append(f"#define {p}_QMIN {t['qmin']}") + lines.append(f"#define {p}_QMAX {t['qmax']}") + lines.append("") + return "\n".join(lines) + + +def _numel(shape) -> int: + n = 1 + for d in shape: + n *= d + return n + + +def clayer(mlops: dict, runtime: list[str], operators: list[str], mlops_file: Path, version: str) -> str: + lines = [ + f"# Generated by create_ai_layer.py from {mlops_file.name} -- do not edit.", + f"# Re-run `python create_ai_layer.py {mlops_file.name}` after changing", + "# model/model.py or the csolution's mlops: node.", + "layer:", + " type: AI", + f" description: {mlops.get('description', mlops['model'].get('name', 'AI layer'))}", + "", + " packs:", + f" - pack: {PACK}@{version}", + "", + " define:", + " - ET_LOG_ENABLED: 0", + "", + " add-path:", + " - .", + "", + " components:", + *[f" - component: Machine Learning:ExecuTorch:{c}" for c in runtime], + *[f" - component: Machine Learning:ExecuTorch Operators:{c}" for c in operators], + "", + " groups:", + f" - group: {mlops['model'].get('name', 'Model')}", + " files:", + f" - file: ./{SYMBOL}.c", + f" - file: ./{SYMBOL}.h", + " - file: ./model_io.h", + "", + ] + return "\n".join(lines) + + +def main() -> None: + if len(sys.argv) != 2 or not sys.argv[1].endswith(".cbuild-mlops.yml"): + sys.exit(f"usage: {Path(__file__).name} .cbuild-mlops.yml") + run_in_venv() + + import yaml + + mlops_file = Path(sys.argv[1]).resolve() + mlops = yaml.safe_load(mlops_file.read_text())["cbuild-mlops"] + layer_file = mlops_file.parent / mlops["model"]["clayer"] + layer_dir = layer_file.parent + + pte, io = export_program(compile_spec(mlops, mlops_file.parent)) + version = executorch_version(mlops_file) + runtime, operators = components(pte, executorch_pack(version)) + + layer_dir.mkdir(parents=True, exist_ok=True) + (layer_dir / "model.pte").write_bytes(pte) + (layer_dir / f"{SYMBOL}.c").write_text(c_array(pte), newline="\n") + (layer_dir / f"{SYMBOL}.h").write_text(HEADER, newline="\n") + (layer_dir / "model_io.h").write_text(io_header(io), newline="\n") + layer_file.write_text(clayer(mlops, runtime, operators, mlops_file, version), newline="\n") + + for name, desc in io.items(): + for kind in ("inputs", "outputs"): + for index, t in enumerate(desc[kind]): + print( + f"[ai_layer] {name} {kind[:-1]}{index}: {t['dtype']}{t['shape']} " + f"scale={t['scale']:.6g} zp={t['zero_point']}" + ) + print(f"[ai_layer] {len(pte)} byte program, operators: {operators}") + print(f"[ai_layer] wrote {layer_file}") + + +if __name__ == "__main__": + main() diff --git a/documentation/mlops-flow.md b/documentation/mlops-flow.md new file mode 100644 index 0000000..aeb9449 --- /dev/null +++ b/documentation/mlops-flow.md @@ -0,0 +1,150 @@ +# The MLOps flow + +The `mlops:` node in `cmsis-executorch.csolution.yml` is the central +definition of the Ethos-U target of the traffic counter. It follows the CMSIS-Toolbox +[MLOps information](https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information) +specification. This document explains how the three build steps use and +propagate that information. + +```mermaid +flowchart TD + A["cmsis-executorch.csolution.yml
mlops: node"] -->|"1. cbuild setup --active <target>"| B["cmsis-executorch.cbuild-mlops.yml
npu, vela.options, model.clayer"] + B -->|"2. create_ai_layer.py"| C["EthosUCompileSpec
quantize, delegate, Vela"] + D["model/traffic.py
YOLO26n vehicles"] --> C + C --> E["ai_layer/model_pte.c
the program as a C array"] + C --> F["ai_layer/ai_layer.clayer.yml
component selection"] + E --> G["3. cbuild --active <target>"] + F --> G + G --> H["traffic.axf"] +``` + +## 1. `cbuild setup` turns the csolution into `*.cbuild-mlops.yml` + +The csolution is the only place where the NPU is described: + +```yaml +solution: + mlops: + description: YOLO26n vehicle detector of the traffic counter for the Ethos-U55 + of the Ensemble E7's M55-HP + npu: + type: Ethos-U55 + vela: + system: RTSS_HP_SRAM_MRAM # system-config from the Ensemble pack's Vela config + memory: Shared_Sram # memory-mode from the Vela config + model: + clayer: $AI-Layer$ + name: TrafficVehicles + hardware: + target: AppKit-E7 # [@] of the board; + # named explicitly, 2.14.1 detects none + simulator: + target: SSE-300-U55 # [@] of the FVP +``` + +`cbuild setup cmsis-executorch.csolution.yml --active AppKit-E7` +resolves it and writes `cmsis-executorch.cbuild-mlops.yml`: + +```yaml +cbuild-mlops: + generated-by: csolution version 2.15.1+p3-gf46d68bf + description: YOLO26n vehicle detector of the traffic counter for the Ethos-U55 of the Ensemble E7's M55-HP + processor: + type: Cortex-M55 + npu: + type: Ethos-U55 + macs: 256 + vela: + ini: .cmsis/ensemble_vela.ini + options: --accelerator-config ethos-u55-256 --system-config RTSS_HP_SRAM_MRAM --memory-mode Shared_Sram + model: + clayer: ai_layer/ai_layer.clayer.yml + name: TrafficVehicles + hardware: + active: AppKit-E7 + cbuild-run: out/cmsis-executorch+AppKit-E7.cbuild-run.yml + output: + - file: out/traffic/AppKit-E7/Release/traffic.axf + type: elf + simulator: + active: SSE-300-U55 + cbuild-run: out/cmsis-executorch+SSE-300-U55.cbuild-run.yml + output: + - file: out/traffic/SSE-300-U55/Release/traffic.axf + type: elf + model: ${workspaceFolder}/.vscode/fvp.sh + config-file: board/Corstone-300/fvp_config.txt +``` + +The Ensemble device family pack declares the NPUs of the device (the E7's +HP core has an Ethos-U55 with 256 MACs) and ships a Vela configuration file, +so the toolbox fills in `npu.macs`, copies the file to +`.cmsis/ensemble_vela.ini` and adds `--accelerator-config`. The FVP's +Ethos-U55-256 runs the same command stream: the system configuration only +steers how Vela schedules for the E7's SRAM and MRAM. The +`hardware:` and `simulator:` sections are what a test runner needs to load +the image on the board or to execute it on the FVP. + +This is the hand-over point to the MLOps side: everything a model-export +pipeline needs to know about the target is in this one file, and nothing in it +is specific to this example's Python code. + +`cbuild setup` writes the file even when the AI layer does not exist yet, so +the flow also works on a checkout without a generated layer. + +## 2. `create_ai_layer.py` turns `*.cbuild-mlops.yml` into the AI layer + +`python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml` stands in +for an MLOps system. It reads the file and: + +1. builds ExecuTorch's `EthosUCompileSpec` from `npu:` and `vela:` -- the + accelerator (`ethos-u55-256`), system config and memory mode come from + there, so the Python code contains no NPU configuration; +2. exports the methods `model/model.py` lists (YOLO26n of + `model/traffic.py`, the method `detect`): quantizes them, delegates the + whole graph to the Ethos-U and compiles it with Vela; +3. reads the operators the resulting program still calls on the CPU and looks + up the matching components in the `PyTorch::ExecuTorch` pack (the version + `cbuild setup` resolved, from `*.cbuild-pack.yml`); +4. writes the layer into the directory of `model.clayer`: + +| File | Content | +|------|---------| +| `ai_layer/ai_layer.clayer.yml` | runtime, kernel utilities and registration, Ethos-U backend and the operator components the program uses | +| `ai_layer/model_pte.c` / `.h` | the program as a 16-byte-aligned C array, `model_pte` / `model_pte_size` | +| `ai_layer/model.pte` | the program itself, for inspection (not committed) | + +The clayer and the C array are committed, so a checkout builds without +Python. For a fully delegated model with quantized IO the component list is +short: `Runtime`, `Kernel Utils`, `Kernel Registration` and `Backend EthosU`. +Everything else in the pack is never compiled, let alone linked. + +## 3. `cbuild` builds the application + +`cbuild cmsis-executorch.csolution.yml --active AppKit-E7` (or +`--active SSE-300-U55`) is a plain CMSIS build without any Python. The cproject knows nothing about the model: it +lists the application source and the two layers, and the AI layer contributes +both the component selection and the model data. + +Because the layer is complete before CMSIS-Toolbox resolves components, a model +change that changes the operator set is just another run of step 2 followed by +step 3. + +## Changing the model or the target + +- **Another model:** edit `model/traffic.py` (or what `model/model.py` + returns), run steps 2 and 3. +- **Another NPU configuration:** edit the `mlops:` node (and add the matching + `target-types:` entry and board layer), run steps 1 to 3. For example the + E7's high-efficiency core and its Ethos-U55 with 128 MACs: + + ```yaml + mlops: + npu: + type: Ethos-U55 + vela: + system: RTSS_HE_SRAM_MRAM # was RTSS_HP_SRAM_MRAM + memory: Shared_Sram + ``` + + The Python side needs no changes at all. diff --git a/documentation/pack-provenance.md b/documentation/pack-provenance.md new file mode 100644 index 0000000..2379f98 --- /dev/null +++ b/documentation/pack-provenance.md @@ -0,0 +1,149 @@ +# Where the ExecuTorch CMSIS pack comes from + +The `PyTorch::ExecuTorch` pack is installed into your CMSIS pack root like +any other pack; nothing of it lives in this repository. This page explains +where it comes from, how to build one yourself, and how to move to a newer +ExecuTorch version. + +## Where it comes from + +The pack is published as an asset of the matching ExecuTorch GitHub release, +which is also what its `.pdsc` declares as its download location: + +```xml +https://github.com/pytorch/executorch/releases/download/v1.5.1/ +``` + +So the normal acquisition routes work, and `cbuild setup ... --packs` takes +care of it on a fresh clone. To install it by hand: + +```bash +cpackget add PyTorch::ExecuTorch@1.5.1 +``` + +The version is pinned exactly, in `cmsis-executorch.csolution.yml` and +`cmsis-executorch.cproject.yml`: + +```yaml +packs: + - pack: PyTorch::ExecuTorch@1.5.1 +``` + +Both must agree. The pin is exact rather than a `@^1.5.1` range because the +pack's C++ runtime and the Python exporter have to be the *same* ExecuTorch +version — see [Moving to a new ExecuTorch version](#moving-to-a-new-executorch-version). + +`create_ai_layer.py` reads the installed pack's `.pdsc` out of the pack root +(`$CMSIS_PACK_ROOT`, or cpackget's default) to find out which operator +components exist. It reads the version `cbuild setup` resolved, taken from +`cmsis-executorch.cbuild-pack.yml`, so a pack root holding several +ExecuTorch versions cannot make it read the wrong one. + +## What is in the pack + +| Path | Contents | +|---|---| +| `PyTorch.ExecuTorch.pdsc` | Component declarations — one component per operator, plus runtime and backend | +| `src/` | ExecuTorch runtime, kernel and Ethos-U backend sources | +| `include/` | Public headers, **including the bundled `include/flatbuffers/`** | +| `armclang_shims/` | Small compatibility shims for Arm Compiler 6 | +| `Documentation/` | Pack README | +| `LICENSE` | Upstream BSD-3-Clause (the example code around it is Apache-2.0) | + +It is a **source** pack: nothing is prebuilt. Every operator is a selectable +component, which is what lets `create_ai_layer.py` narrow the link to +exactly the kernels a given `.pte` needs. + +## Building a pack yourself + +Worth knowing if you need a version that has no published pack yet, or want to +carry a local ExecuTorch change into the firmware. The generator lives in the +ExecuTorch tree at `backends/arm/cmsis_pack/scripts/build_pack.sh`. + +```bash +git clone https://github.com/pytorch/executorch.git +cd executorch +git checkout release/1.5 # or the tag matching your target version +git submodule update --init --recursive +``` + +> **Run the CMake cross-compile before `build_pack.sh`.** +> +> This is the one trap worth knowing about. If `build_pack.sh` runs without the +> prior cross-compile, it completes successfully but **silently omits**: +> +> - the bundled `include/flatbuffers/` headers, and +> - the flatc-generated `program_generated.h` and `scalar_type_generated.h`. +> +> The resulting pack looks complete and fails at compile time with missing-header +> errors that point nowhere useful. Those two headers are generated with: +> +> ```bash +> flatc --cpp --cpp-std c++11 --gen-mutable --scoped-enums .fbs +> ``` +> +> `flatc` ships inside the executorch wheel — after `./setup_venv.sh` it is at +> `.venv/bin/flatc`. + +Then run the generator; the pack lands in `pack-output/`: + +```bash +backends/arm/cmsis_pack/scripts/build_pack.sh +``` + +### Verifying a pack you built + +Before trusting a freshly built pack, check the parts that go missing quietly: + +```bash +PACK=pack-output/PyTorch.ExecuTorch. + +# 1. The bundled flatbuffers headers must be present. +test -d "$PACK/include/flatbuffers" || echo "MISSING: include/flatbuffers" + +# 2. The flatc-generated headers must be present. +for h in program_generated.h scalar_type_generated.h; do + find "$PACK/include" -name "$h" | grep -q . || echo "MISSING: $h" +done + +# 3. The component list should still cover the operators the model uses. +grep -c '.pack +``` + +## Moving to a new ExecuTorch version + +The pack's C++ runtime and the Python exporter must come from the *same* +ExecuTorch version — a `.pte` produced by a different version than the runtime +that loads it will fail at load time, or worse, at inference time. Four steps, +in order: + +1. **Install the new pack** — `cpackget add PyTorch::ExecuTorch@`, or + build one yourself (above) if the version is not published. +2. **Update both pins** — `PyTorch::ExecuTorch@` in the csolution and in + the cproject. +3. **Update the Python pins**: `executorch`, `torch` and `torchao` in + `requirements.txt`, following the new release's `install_requirements.py`; + `requirements-arm-tosa.txt` (the TOSA serializer and its flatbuffers pin) + only changes when the Arm backend's `requirements-arm-tosa.txt` does. +4. **Rebuild the venv, the AI layer and the project:** + + ```bash + ./setup_venv.sh --recreate + cbuild setup cmsis-executorch.csolution.yml --active AppKit-E7 --packs + python3 create_ai_layer.py cmsis-executorch.cbuild-mlops.yml + cbuild cmsis-executorch.csolution.yml --active AppKit-E7 + cbuild cmsis-executorch.csolution.yml --active SSE-300-U55 + ``` + + A changed operator set simply shows up in the regenerated + `ai_layer/ai_layer.clayer.yml`. + +Finally, update the version wherever it appears in prose: the README +(Prerequisites and the pack-version note), the csolution header comment and +this page. diff --git a/documentation/traffic-counter.md b/documentation/traffic-counter.md new file mode 100644 index 0000000..acf1976 --- /dev/null +++ b/documentation/traffic-counter.md @@ -0,0 +1,466 @@ +# Traffic counter with YOLO26n on the Ethos-U55 (AppKit-E7) + +The vehicles an Alif Ensemble E7 AppKit (AK-E7-AIML, Gen 2) sees through its +camera are detected by Ultralytics YOLO26n on the Ethos-U55-256 next to the +Cortex-M55 HP core, followed from frame to frame by a small tracker and +counted, per class and direction, as they cross a line on the picture. The +panel shows the picture, the tracks, the line and the tallies. The project is +`traffic/traffic.cproject.yml`, target-type `AppKit-E7`; the same application +and AI layer also run on the Corstone-300 FVP (target-type `SSE-300-U55`, see +[On the FVP](#on-the-fvp)). It started as a fork of the YOLO26n cat detector +for the Ensemble E8 in the Arm cmsis-executorch example. + +## The model + +[`model/traffic.py`](../model/traffic.py) cuts YOLO26n at its NMS-free +one-to-one head (the weights, anchors, letterbox and calibration images come +from `model/yolo.py`), with the classification branch ending in the five COCO +vehicle classes. Its outputs are +anchor-major, `box int8 (1, 3549, 4)` (left, top, right, bottom distance +from each anchor, in anchor strides) and `cls int8 (1, 3549, 5)` (sigmoid +score of bicycle, car, motorcycle, bus, truck): the NPU's NHWC order +flattened, where the channel-major `(1, C, N)` of Ultralytics cost 209 +per-channel copies on the Ethos-U55. + +The weights are YOLO26n without its two attention blocks, fine-tuned on the +COCO images with vehicles ([`model/yolo26n-noattn.yaml`](../model/yolo26n-noattn.yaml), +`traffic/train_vehicles.py`, see "Training" below): the whole network is one +method, `detect`, every operator on the NPU. The checkpoint is committed as +[`model/yolo26n-noattn-vehicles.pt`](../model/yolo26n-noattn-vehicles.pt) +(derived from Ultralytics' `yolo26n.pt`, under its AGPL-3.0 license). +Without it, or with `TRAFFIC_WEIGHTS` pointing at the COCO-pretrained +`yolo26n.pt`, the export keeps the attention and moves it to the CPU, as +follows. + +The two attention blocks of YOLO26n (the PSA in layer 10 and in layer 22, +13x13 tokens, 2 heads) run on the CPU. The Ethos-U55 has no matrix multiply: +Vela runs each q k^T and each attention-weighted sum as one broadcast +multiply with int32 results plus one REDUCE_SUM per row, 1358 operators, 8 +bytes of SRAM traffic per MAC, about 50 of the 80 ms of the whole network +for 1 % of its MACs (see "Performance on the board"). So the export +(`TRAFFIC_ATTENTION=cpu`, the default) is three NPU methods with the +attention cores in between, on the CPU (`traffic/attention.c`): + +| Method | Inputs | Outputs | +|--------|--------|---------| +| `stem` | `image int8 (1, 416, 416, 3)`: RGB888 as the camera path delivers it, `q = pixel ^ 0x80` | layers 0-9 and layer 10 up to the attention: `l4`, `l6` (for the neck), `y10` (C2PSA's cv1), `qkv10 (1, 13, 13, 256)` | +| attention core (CPU) | `qkv10` | `o10 (1, 13, 13, 128)` = softmax(q k^T / sqrt(32)) v per head | +| `mid` | `o10`, `qkv10`, `y10`, `l4`, `l6` | the rest of layer 10, the neck, layer 22 up to its attention: `qkv22`, `z22`, `y22`; the stride 8 and 16 heads: `box34`, `cls34` (logits) | +| attention core (CPU) | `qkv22` | `o22` | +| `head` | `o22`, `qkv22`, `z22`, `y22`, `box34`, `cls34` | `box`, `cls` as above | + +Every tensor crosses in NHWC, so no method needs a transpose. The same +tensor gets other quantization parameters as an output of one method and an +input of the next (concatenations share one range), so `detector.cpp` +requantizes it in place with a 256-entry table. The stride 32 scores are +appended in `head` so that `cls` keeps one range: a score output of the +stride 8 and 16 anchors alone got the range of what COCO128 scores there (up +to 0.19) and clipped every stronger detection. `TRAFFIC_ATTENTION=npu` +exports the whole network as one method, `detect`, instead (the attention in +the channels-last form of `TokenMajorAttention`, which saves Vela 870 +per-channel copies against Ultralytics' form); `detector.cpp` handles both. + +Vela 5.1 for the Ethos-U55-256 (`RTSS_HP_SRAM_MRAM`, `Shared_Sram`), every +operator on the NPU: without attention one method, 1.12 GMAC, 1220 KiB SRAM +scratch, a 2.28 MB program; with the attention on the CPU three methods, +1.11 GMAC, 1219 KiB scratch (stem; mid 1156 KiB, head 223 KiB), 2.27 MB. + +`traffic/eval_vehicles.py` measures the vehicle AP50 of the float and the +int8 model on a dataset in the YOLO layout; the int8 score output is +calibrated on the COCO128 images with the most vehicles. For the split +export the int8 model is the three quantized methods with the integer +attention core in between (`attention_core_int8()`, what `attention.c` +computes; on the board its output matches the host's to the last bit in all +but 1 of 21632 values). + +## Training + +`traffic/train_vehicles.py prepare` puts the COCO 2017 train images with a +vehicle (19759) and 5000 without one, with their 80-class labels, into +`tmp/train_vehicles/` (4.2 GB, the images one by one from +images.cocodataset.org); validation is the 570 COCO val2017 images with a +vehicle that are not among the first 300 (those are the test set of +`eval_vehicles.py`). `traffic/train_vehicles.py train` fine-tunes +`model/yolo26n-noattn.yaml` from `yolo26n.pt` (635 of its 720 tensors; the +two replaced blocks start from scratch) at 416 x 416 for 50 epochs with +Ultralytics' defaults (MuSGD, lr 0.01), on an M4 Max's GPU (MPS) in 9 hours, +and copies the best weights to `model/yolo26n-noattn-vehicles.pt`. +The first epochs lose accuracy (the learning rate ramps up while the new +blocks are random), the rest win it back and more: + +| Weights | Vehicle AP50 float | int8 | +|---------|--------------------|------| +| COCO-pretrained YOLO26n (attention on the CPU) | 0.476 | 0.464 | +| without attention, fine-tuned, epoch 9 of 50 | 0.395 | 0.374 | +| without attention, fine-tuned, 50 epochs | 0.510 | 0.501 | + +(300 COCO val2017 images with vehicles, 1168 of them, `eval_vehicles.py`.) +The fine-tune on vehicles at the application's input size is worth more +than the attention blocks were. + +## Build and run + +```bash +./setup_venv.sh && .venv/bin/python -m pip install ultralytics # once +.venv/bin/python traffic/make_test_image.py # the test image, traffic/test_image.c (not committed) +cbuild setup cmsis-executorch.csolution.yml --active AppKit-E7 --packs # writes cmsis-executorch.cbuild-mlops.yml +.venv/bin/python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml # only after changing model/traffic.py +cbuild cmsis-executorch.csolution.yml --active AppKit-E7 --packs +``` + +The AI layer `ai_layer/` is committed, so the export is only needed after a +change to the model. The `mlops:` node of the csolution gives it the +Ethos-U55-256 and the Vela system configuration `RTSS_HP_SRAM_MRAM` of the +Ensemble pack's `ensemble_vela.ini` (the HP core's NPU: scratch in the SRAM, +command stream and weights in the MRAM); see [mlops-flow.md](mlops-flow.md). + +The Secure Enclave has to boot the HP core from its MRAM region: the "Alif: +Install M55_HP debug stubs (AppKit-E7)" task (SW4 on SEUART; the boot table +is `.alif/M55_HP_mram_cfg_e7.json` with the E7's own device configuration +`.alif/app-device-config-e7.json`, silicon revision B4), or +`tools/setools_mram.py --part E7` to program the image itself through the +SE. Then load and debug `AppKit-E7` from the CMSIS view (launch +configuration "M55_HP JLink (launch)"). + +The console is a log buffer in the DTCM, `console_log`, that the debugger +reads (`python tools/console_log.py +out/traffic/AppKit-E7/Release/traffic.axf.map`). The global `traffic_status` +holds the tallies (`counts`), the frame counters, the times of each step in +microseconds, the camera gain and white balance, the live tracks and the +latest detections; writing 1 to `traffic_reset_counts` zeroes the tallies. + +## On the FVP + +The target-type `SSE-300-U55` is the Corstone-300 with a Cortex-M55 and an +Ethos-U55-256, simulated by `FVP_Corstone_SSE-300_Ethos-U55`: the NPU +configuration of the E7's HP core, so the AI layer is the same and the +command stream the same. The FVP has no camera, panel, joystick or SDS link; +its board layer ([`board/Corstone-300/`](../board/Corstone-300/)) leaves out +their `APP_HAS_*` defines, so `app_traffic.cpp` takes the test image, and sets +`TRAFFIC_FRAMES` (3): the test image goes through the detector and the tracker +that many times, every frame's detections go to the model's stdout over +semihosting, and `exit()` ends the simulation: + +```text +Traffic counter: YOLO26n on the Ethos-U55, input 416x416 RGB888, core 32 MHz, line at 208 vertical +frame 0: 2 vehicles, detect 1203 us (NPU 163 us) + TRUCK 0.65 x1 161 y1 233 x2 293 y2 314 + TRUCK 0.50 x1 335 y1 201 x2 415 y2 363 +... +Test_result: PASS +``` + +The detections are the board's on the same image (truck 0.65 and truck +0.50, see Performance on the board): the same int8 command stream on the same +input. The times are not: the FVP's NPU runs in fast mode (`ethosu.extra_args=--fast` in +`board/Corstone-300/fvp_config.txt`) and the model times nothing like the +hardware; three frames take about 5 s of wall time. Code and data live in +the DDR4 (`board/Corstone-300/regions_SSE-300.h`): the program, the test +image, the NPU scratch and the input slots exceed the SSE-300's SRAMs. + +```bash +cbuild cmsis-executorch.csolution.yml --active SSE-300-U55 --packs +FVP_Corstone_SSE-300_Ethos-U55 -f board/Corstone-300/fvp_config.txt -a out/traffic/SSE-300-U55/Release/traffic.axf +``` + +In VS Code, **Run** and **Debug** in the CMSIS view do the same with +`.vscode/fvp.sh` as the model, which on macOS runs the Linux FVP in Docker +(the image is built on first use, `.vscode/fvp.Dockerfile`). The FVP needs an +Arm user-based license (the Keil MDK Community license is enough). + +## The pipeline + +| Step | Where | +|------|-------| +| The kit's MT9M114 module, 640x480 RGB565 from the sensor's own ISP over MIPI CSI-2 (1 lane) into the CPI, which writes one frame buffer; at each VSYNC the application hands it the other of two (`camera.c`; the E7 has no ISP and its CPI no streaming mode) | CPI | +| The frame scaled to 416x416 interleaved RGB888 (an ARX3A0's raw Bayer frame demosaiced first, the colours of each 2x2 cell, no interpolation), turned if the module is mounted turned, gray-world white balance; the MT9M114 runs its own auto exposure, for an ARX3A0 the mean brightness drives the sensor gain (`camera_auto_exposure`) | camera thread (`image.c`) | +| RGB888 to int8 in the backend's input copy, `stem`, `mid` and `head` on the NPU, the two attention cores and the requantization between them on the CPU (`attention.c`), the best class per anchor and the decode | vision thread (`detector.cpp`) | +| Detections matched to the tracks by overlap with a constant-velocity prediction; a track is confirmed after 3 detections and counted once when its centre crosses the line (`tracker.c`) | vision thread | +| The picture into the back frame buffer | vision thread | +| The line, the boxes in the class colours (the track labels kept inside the picture: the margins beside it are never redrawn), the tallies, the score maps, cache clean, present | display thread, while the NPU runs the next frame | + +The counting line is vertical in the middle of the picture +(`TRAFFIC_LINE_VERTICAL: 1`, set for the Amsterdam crossing of the YouTube +recordings, whose traffic runs left and right below the middle: over the whole +video a vertical line in the middle counts 261 crossings, a horizontal one +29); without the define it is horizontal. `TRAFFIC_LINE_POS` (input pixels) +and `TRAFFIC_LINE_VERTICAL` in the `define:` block of +`traffic/traffic.cproject.yml` move and turn it, the joystick at run time. +Direction 0 ("DOWN", or "RIGHT" for a vertical line) is a crossing towards +larger coordinates. + +Camera settings to confirm on the board (`traffic/camera.h`): `CAMERA_BAYER` +(the Bayer order of the ARX3A0's frame, GRBG assumed: swapped red and blue or +a green cast mean another order) and `CAMERA_QUARTER_TURNS` (the module's +mounting). The pack's own AppKit-E7 layer names the MT9M114 sensor; with that +module the layer's sensor component and `RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 3` +(640x480 RGB565) select the RGB565 path of `camera.c`. + +## Recording and playback (SDS) + +Two streams: `CameraIn` (each 416x416 RGB888 model input) and `Detections` +(a `detections_t` per frame, a class per box), metadata in +`recordings/traffic/*.sds.yml`. + +```bash +.venv/bin/python traffic/sds_session.py record 20 # 20 s from the camera +.venv/bin/python traffic/sds_session.py play # CameraIn..sds into the detector instead of the camera +.venv/bin/python traffic/images_to_sds.py make recordings/traffic/playback img1.jpg img2.jpg ... +.venv/bin/python traffic/sds_session.py play --workdir recordings/traffic/playback +.venv/bin/python traffic/images_to_sds.py check recordings/traffic/playback # board vs host float model +``` + +Playback keeps the recorded pace: every record carries its time in ms (the +kernel tick when recorded from the camera; `images_to_sds.py make --fps N` +stamps images 1000/N ms apart, default 10 fps), and `rec_play_read_input` +holds a record until it is as far after the previous one as their times are +apart. A late record goes at once and the schedule moves with it, so a stall +in the USB transfer does not make the following frames race. Without it +playback ran as fast as the loop, 2.65x too fast for a 10 fps stream at 26.5 +fps. Measured over the User USB (2026-09-29): 100 records at 10 fps took +10.0 s from open to close (9.9 s of video); 300 records at 30 fps took 11.6 +s, 25.8 fps: the loop cannot keep up with 30, so such a stream plays at +0.86x and never waits. `recordings/traffic/youtube_full_fill` is the traffic +video (25 fps, 9 min) resampled to 30 fps by ffmpeg, which repeats every +sixth frame: 16303 records, 8.5 GB; `recordings/traffic/youtube_60s` is its +first minute (1800 records, 935 MB), which plays in 67 s (26.8 fps; with the +vertical line `count_playback.py` counts 26 over the board's detections: +22 bicycles, 2 cars, 2 motorcycles). +`images_to_sds.py` at 10 fps (eval) makes +300 images a 30 s playback. The tracker counts per frame, not per second: +the pace changes what the panel shows, not the counts. + +On the AppKit-E7 the joystick moves the line (`traffic/joystick.c`, +`APP_HAS_JOYSTICK`): left and right move a vertical line, up and down a +horizontal one, faster once held for a second, and the centre button turns it +by 90 degrees; the direction labels follow. The switches sit on the +low-power GPIO block (P15_0..4, pulled up by the pin table); a read of that +block costs milliseconds, so a thread at the lowest priority polls it every +40 ms while the vision thread waits for the NPU (from the vision thread the +five reads took 17 ms a frame and the panel flickered), and the vision thread +applies the requested line between two tracker updates; moving the line +counts nothing by itself. + +`traffic/count_playback.py [--sweep]` reruns tracker.c's logic on the +PC over the board's detections of a playback (the count the board showed) and +over the float model's detections of the same inputs (the reference), by +class and direction, and reports where the tracks moved; `--sweep` tries +horizontal and vertical lines at several positions. On the YouTube clip +(vehicles along a road across the picture just below the middle) the +horizontal line at 208 counts 9 on the board and 12 on the host, a vertical +line at 208 counts 45 and 64: the line has to cut the traffic's path +(`TRAFFIC_LINE_POS`, `TRAFFIC_LINE_VERTICAL` in the layer). + +The firmware's SDSIO client connects only while it starts: start the server +(`sds_session.py`, which waits for the client's first flags exchange), then +reset the board. `traffic/eval_vehicles.py --board ` scores the board's detections of a playback of the dataset's images +against the host's, all cut as `detector.cpp` cuts them (score above 0.30, at +most 16 boxes). For the 300 test images (`recordings/traffic/eval300`, +2026-09-29, the fine-tuned model without attention) the board matches the +host's int8 model: AP50 of the cut detections 0.362 (host int8 0.362, float +0.366), precision 0.809 (0.808), recall 0.396 (0.397), NPU 31.1 ms per image. + +The same four steps are VS Code tasks (Terminal > Run Task): "SDS: video to +CameraIn stream" (ffmpeg frames at a chosen rate, letterboxed or with +`--fill`, the sides cut so the picture fills the input), "SDS: play recording +to the board (USB)", "SDS: record from the camera (USB)" and "SDS: check +playback against the host model"; and the panel video below, "SDS: play +recording and record the panel (USB)" and "SDS: panel stream to MP4". One +SDSIO server owns the USB device at a time: a second playback started while +one runs resets the link, and the board's half-open streams then crash the +next server; let a run finish or stop it with Ctrl+C. + +### A video of the panel + +With SDSIO-Server's user flag 0 set when the streams open (key A, or +`sds_session.py --panel`) the firmware opens a third stream, `Panel`: every +frame as the panel showed it, the CDC200's whole 480x800 frame buffer. The +display thread writes it after the frame is on the panel and before the +vision thread may draw into that buffer again, so no frame is lost and a slow +link holds the loop back instead. A record must fit the stream buffer and no +memory holds a 1.15 MB one, so a frame goes as 20 records of 40 rows with the +frame's timeslot, through a 230 kB buffer in SRAM1 (four records); a lock +keeps the vision thread from closing the stream in the middle of a frame, +and at the end of a playback it waits for the last frame's records. +`recordings/traffic/Panel.sds.yml` describes a record; the bytes are the +frame buffer's, B, G, R per pixel and turned by 180 degrees. + +```bash +.venv/bin/python traffic/sds_session.py play --panel --timeout 3600 --workdir recordings/traffic/ +.venv/bin/python traffic/panel_to_video.py recordings/traffic/ -o panel.mp4 +.venv/bin/python traffic/panel_to_video.py recordings/traffic/ --still 150 -o frame.png +``` + +`panel_to_video.py` joins the records of each frame, turns it upright and +has ffmpeg write H.264 at the pace of the timeslots: in a playback those are +the clip's (30 fps for the traffic video), so the video shows the traffic at +its real speed, every frame the board drew, whatever rate the board managed +while it streamed; `--fps` sets another. A frame cut short (stopped with S +while it was written) is dropped. SDS-Convert's `video` mode cannot do this: +it reads the whole file into memory and takes one record per frame. + +The cost is the USB: 1.15 MB up per frame next to the 519 kB CameraIn record +down. On the whole traffic video (`youtube_full_fill`, 16303 frames, +2026-10-01) the loop ran at 17.1 fps instead of 25.8, 58 ms a frame of which +24 ms the vision thread waited for the display thread's panel write; the +NPU's 31 ms did not change. The playback took 16 minutes, about 29 MB/s over +the User USB, and every frame arrived: 16303 panel frames (18.8 GB) for +16303 detections. The "FPS" on the recorded panel is that slower rate. + +During a playback the camera thread pauses: the model inputs share the two +slots in SRAM1 (see below). It also starts no snapshots then: while it kept +the CPI going unread, playbacks of the traffic video stopped after 580 and +1420 frames in `osRtxErrorNotify` (stack overflow of `sdsControl`), a +snapshot had written about 1 kB of picture past the end of the last camera +buffer, over the bottom of that thread's stack right behind it (3 CPI error +events counted by then). + +The link is the board's User USB (`SDS:IO:USB&MDK USB`, a custom-class +device "SDSIO-Client", VID 0xC251 PID 0x8007, high speed): the 40-frame +YouTube clip (20.7 MB) plays in about 8 s, where the J-Link RTT link +(`--transport rtt`, `tools/sdsio_rtt_bridge.py`) needed 5 s per frame. +Two things the USB device needs on the E7: the application powers the USB +PHY through the Secure Enclave (`usb_power_init` in `main.c`), and every +buffer the USB controller reads or writes in the DTCM must lie in the +linker's non-secure region `NS_REGION_0` (the TGU rejects the controller +elsewhere, and a control or bulk transfer then hangs silently): the EP0 +buffer (`USBD0_BUF_MEM_LOCATE`), the SDS client's bulk buffer, the SDS +data block, and the RTX dynamic memory that holds the SDS thread's stack, +because the SDS client sends its command headers straight from the stack. + +## Memory + +| Memory | Holds | +|--------|-------| +| MRAM, from 0x80200000 | code and the test image in the HP core's region, then the 2.46 MB program (`ER_MODEL`, running on into the MRAM user region at 0x80400000). It stops 64 kB below the top of the MRAM, where the Secure Enclave's application package lives (`board/AppKit-E7/linker_ac6_traffic.sct.src`); 3.0 of the 3.4 MB are used | +| SRAM0, 4 MB | the ExecuTorch method pool, the two 640x480 RGB565 camera frames (614 kB each), the two 480x800 RGB888 panel buffers (1.15 MB each), the thread stacks; the first 4 kB stay free for the Cortex-A32 stub; 92 % used (with the attention on the CPU also the outputs of `stem`, 519 kB, reused by `head`'s, with a 16 kB method pool: 99 %) | +| SRAM1, 2.5 MB at 0x08000000 | the `Panel` stream buffer (230 kB), two model input slots (519 kB each) and Vela's scratch (1.25 MB, `APP_TEMP_POOL_SECTION`; the NPU runs 81 ms from here as from SRAM0); 98 % used; `UNINIT`, powered through the Secure Enclave by the application; the CPI and the CDC200 cannot reach it, so the camera frames and the panel buffers are in SRAM0. SRAM8 (2 MB at 0x63200000) is no alternative for a panel buffer: with it the display DMA hangs the interconnect at boot, the debug port with it, and the image in MRAM then has to be replaced with the reset button pressed while the J-Link connects | +| DTCM, 1 MB | the console log, the SDS input buffer, the C library, the tracker (with the attention on the CPU also the outputs of `mid`, 139 kB, the two attention outputs and the attention core's buffers: 92 % instead of 72 %); the non-secure region at its end holds the USB DMA buffers and RTX's dynamic memory | + +The E7's SRAM0 and SRAM1 are not contiguous, so the scatter file places +them separately; the input slots went from three to two to fit. + +## Camera on the AppKit-E7 + +Four things stood between the pack's AppKit-E7 BSP and a live picture +(2026-09-25, all found on the board with the debugger): + +- **The camera clock pin.** The BSP's pin table selects `LPCAM_XVCLK_B` on + P0_3, the clock of the HE core's low-power CPI, which nothing enables. The + sensor drivers run the HP CPI's pixel clock (`CAMERA_PIXCLK_CTRL`, 400 MHz / + 20), which reaches the pin only as `CAM_XVCLK_A`: without it the sensor never + answers on I2C1. `board/AppKit-E7/RTE/BSP/.../pins.h` selects `CAM_XVCLK_A`, + as the pack's own AppKit-E7 layer does. +- **The sensor.** The kit's module is an MT9M114 (I2C address 0x5D over MIPI), + not an ARX3A0: the layer names the MT9M114 component, + `RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 3` (640x480 RGB565). Its ISP + tracks the exposure only once asked (`CPI_CAMERA_SENSOR_AE` in `camera.c`). +- **SRAM1 is the CPU's alone.** The CPI's writes to SRAM1 come back with AXI + decode errors (`CAM_AXI_ERR_STAT` 0xff03), and the CDC200 cannot read it + either (the panel goes dark). Neither the E8's nor the E7's device + configuration in the boot table changes that. So the camera frames live in + SRAM0 (`.bss.ai_pool`); to keep both panel buffers there too, Vela's scratch + moved to SRAM1 next to the model input slots (see Memory). +- **One snapshot per frame.** In video mode the pack's driver refuses a new + frame address while the CPI is busy (`ARM_DRIVER_ERROR_BUSY`), and the E7's + CPI, which has no stream mode, then writes frame after frame past the + buffer, over the thread stacks and the pools: a bus fault in the camera + thread, and within seconds the Secure Enclave and the debug port are gone. + `camera.c` takes one snapshot at a time (`CaptureFrame`, the STOP event) and + starts the next one into the other buffer from the camera thread, about 25 + snapshots a second. + +The panel's MADCTL value is a layer setting (`TRAFFIC_LCD_MADCTL`), written +before the video stream starts. On this ILI9806E in video mode only bit 0 +does anything, a mirror along the long axis (the pack's panel driver sets +0x01, the layer 0x00); bits 7 and 6 are ignored. The panel hangs upside down, so +`IMAGE_PANEL_TURN_180` (the layer) makes `image.c` draw everything, the picture +and every rectangle behind boxes, line, score maps and text, at the opposite +x and y: no extra pass over the frame buffer (turning it in place afterwards +cost 60 ms a frame and starved the NPU). + +The panel buffers are the CDC200's RGB888 (`RTE_CDC200_PIXEL_FORMAT 1`): the +HWRM names the layer formats by bit position in a little-endian word +(`CDC_Ln_PIX_FORMAT`: ARGB8888, RGB888, RGB565 with red in the top bits), so +RGB888 is R in bits 23:16 and B in 7:0, in memory B, G, R. The model input +is R, G, B, which the MT9M114's RGB565 (R in bits 15:11) gives directly and +the model needs, so `image.c` swaps R and B when it copies the picture into +the panel buffer and when it fills a rectangle. With R, G, B in the panel +buffer red and blue trade places on the panel. + +With the camera the loop runs at 25 fps (18.7 fps with the attention on the +CPU). The camera thread converts a +frame only when the vision thread has taken the last one (the camera +delivers about twice the frames the detector takes), and converts below the +vision thread's priority, so the one conversion per frame (7 ms, 15 ms before +the per-pixel division left `image_rgb565_to_input`) goes into the vision +thread's waits for the NPU and not into the detector's CPU work. Right after a +`load_and_debug` (a core-only reset) the first inference can fail with err 35, +the NPU still busy with the previous job; the loop recovers on its own. + +## Performance on the board + +2026-09-28/29, test image, no camera: + +| Model and export | NPU | CPU attention | Requant | Detect | Frame | Camera loop | Test image (host int8) | +|------------------|-----|---------------|---------|--------|-------|-------------|------------------------| +| YOLO26n, `detect`, everything on the NPU (before) | 80.4 ms | - | - | 82.2 ms | 85.6 ms, 11.7 fps | 11.1 fps | truck 0.69, truck 0.61 | +| YOLO26n, `detect`, channels-last attention, anchor-major outputs | 79.7 ms | - | - | | | | truck 0.69, truck 0.61 | +| YOLO26n, `stem` + `mid` + `head`, attention on the CPU | 31.1 ms (16.4 + 13.0 + 1.6) | 10.0 ms | 1.7 ms | 47.3 ms | 50.7 ms, 19.7 fps | 18.7 fps | truck 0.69, truck 0.61 (0.69, 0.61) | +| without attention, fine-tuned, `detect` | 31.0 ms | - | - | 32.7 ms | 36.0 ms, 27.6 fps | 25.0 fps | truck 0.65, truck 0.50 (0.65, 0.50, and a motorcycle at 0.35) | + +With the attention on the CPU the NPU writes 12.5 MB per frame instead of 65 +MB; the rest of its `detect` is the backend's copies in and out of the three +NPU jobs (about 4.5 ms). The vehicle AP50 on 300 COCO val2017 images with +vehicles (1168 of them) of YOLO26n: float 0.476; int8 0.457 before, 0.461 +with the channels-last attention, 0.464 with the attention on the CPU; a +smaller input costs accuracy (int8 0.420 at 384, 0.403 at 352, 0.386 at +320). Without attention and fine-tuned: float 0.510, int8 0.501. + +What the attention costs on the NPU was found by running the command stream +from a copy in SRAM0 with an NPU_OP_STOP (and QSIZE right after it) at the +first attention operator: the backbone before it takes 16.5 of the 80.4 ms, +22.0 of the 102 MB read and 6.3 of the 65 MB written. + +Before (2026-09-25), AppKit-E7, HP core and Ethos-U55-256 at 400 MHz, the +test image, no camera. The NPU time is the command stream from start to interrupt, +the rest of the frame is the CPU (the input copy, the decode, the tracker, the +picture); the display thread runs while the NPU works. + +| Input | Vela | NPU | Frame | Detections on the test image | +|-------|------|-----|-------|------------------------------| +| 416 | `RTSS_HP_SRAM_MRAM`, `Shared_Sram` | 81.0 ms | 83.4 ms, 12.0 fps | 2 (float model on the host: 0.71, 0.56, 0.35, 0.27) | +| 416 | `RTSS_HP_DTCM_SRAM`, `Dtcm_Cache`, 640 kB cache in the DTCM | 84.0 ms | 86.4 ms, 11.6 fps | 2 | +| 320 | `RTSS_HP_SRAM_MRAM`, `Shared_Sram` | 40.6 ms | 42.2 ms, 23.7 fps | 0: the int8 model's best score is 0.28, below the 0.30 threshold (host: 0.47, 0.35, 0.28) | + +The U55 is bound by its one AXI port, not by the MACs and not by the MRAM. +Its PMU over one 416 inference (32.4 M cycles, counters programmed from the +debugger after the driver's soft reset, `detector.cpp`'s inference hooks): + +| Counter | Cycles or beats | Share | +|---------|-----------------|-------| +| `MAC_ACTIVE` | 7.6 M | 23 % | +| `MAC_STALLED_BY_IB` (waiting for input data) | 10.7 M | 33 % | +| `AXI0_RD_TRAN_REQ_STALLED` | 11.9 M | 37 % | +| `MAC_STALLED_BY_WD` (weights from the MRAM) | 1.1 M | 3 % | +| `AXI0_RD_DATA_BEAT_RECEIVED` | 12.8 M beats in 3.1 M transactions (4 beats each) | 102 MB read | +| `AXI0_WR_DATA_BEAT_WRITTEN` | 8.1 M beats | 65 MB written | + +The same counters with the scratch cache in the DTCM are unchanged (the DTCM +is no faster for the NPU than SRAM0 on this part, whatever `ensemble_vela.ini` +assumes), so memory placement does not help; only less traffic does. A 320 +input halves the NPU time but costs detections: the model would need the +score threshold and the int8 calibration revisited at that size +(`YOLO_IMGSZ=320` for `create_ai_layer.py` and `make_test_image.py`). Most of +the traffic was the attention (above). + +## Status + +Runs on the AppKit-E7 (AK-E7-AIML, Gen 2, MT9M114 module; 2026-09-28, AC6, +`out/traffic/AppKit-E7/Release/traffic.axf`): YOLO26n without attention, +fine-tuned on vehicles, the camera loop at 25 fps (11.5 fps with the +COCO-pretrained YOLO26n whole on the NPU, 18.7 fps with its attention on the +CPU), the NPU at 31 ms per 416x416 frame, the joystick line, and SDS +recording and playback over the User USB. The tracker's counting is checked +on the host against the float model (`traffic/count_playback.py`). diff --git a/model/model.py b/model/model.py new file mode 100644 index 0000000..879ecbe --- /dev/null +++ b/model/model.py @@ -0,0 +1,40 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +"""The methods create_ai_layer.py exports into the ExecuTorch program. + +create_ai_layer.py calls get_methods() and turns every MethodSpec into one +method of the .pte: it exports the module, quantizes it with the samples as +calibration data (the first sample is also the example input), delegates it +to the Ethos-U and compiles it with Vela. The model of this repository is +the traffic counter's YOLO26n vehicle detector (traffic.py). +""" + +from __future__ import annotations + +from dataclasses import dataclass, field + +import torch +from torch import nn + + +@dataclass +class MethodSpec: + """One ExecuTorch method: the module, its calibration/example inputs and the activation width.""" + + name: str + module: nn.Module + samples: list[tuple[torch.Tensor, ...]] = field(default_factory=list) + activation_bits: int = 8 # 8 or 16 (int16 activations, int8 weights) + + @property + def example(self) -> tuple[torch.Tensor, ...]: + return self.samples[0] + + +def get_methods() -> list[MethodSpec]: + torch.manual_seed(0) + # YOLO26n with the vehicle classes, for the Ethos-U55: the single method + # `detect`, or stem, mid and head around the attention on the CPU. + from traffic import get_traffic_methods + + return get_traffic_methods() diff --git a/model/traffic.py b/model/traffic.py new file mode 100644 index 0000000..4d0d5cc --- /dev/null +++ b/model/traffic.py @@ -0,0 +1,435 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +"""Vehicle detection with Ultralytics YOLO26n on the Ethos-U55, for the traffic counter. + +YOLO26n cut at its NMS-free one-to-one head (model/yolo.py): the network up +to the raw head outputs on the NPU, the threshold and the box decode on the +CPU, with the classification branch ending in the vehicle classes of COCO: + + image int8 (1, S, S, 3) RGB in [0, 1], interleaved + -> box int8 (1, N, 4) left, top, right, bottom distances + from each anchor, in anchor strides + -> cls int8 (1, N, C) sigmoid score per class, C = len(CLASSES) + +With the fine-tuned weights (YOLO26n without its attention blocks, see +WEIGHTS below) that is the single method `detect`. With the COCO-pretrained +yolo26n.pt and its two attention blocks it is, by default +(TRAFFIC_ATTENTION=cpu), three NPU methods, stem, mid and head, with the +attention cores on the CPU in between (see Split below); +TRAFFIC_ATTENTION=npu exports that as the single method `detect` too. + +The N anchors are the cells of the stride 8, 16 and 32 maps, row by row, +stride 8 first. The CPU (traffic/detector.cpp) takes the best class of each +anchor, thresholds it and turns the distances into boxes; traffic/tracker.c +follows the boxes from frame to frame and counts them across a line. + +The Ethos-U55 (the E7's NPU) has no TRANSPOSE: the NHWC to NCHW permute of +the input is handled by the Arm backend's layout passes, and whatever it +cannot fold stays on the CPU, so the export reports what runs where. What the layout passes cannot fold, Vela turns into +one copy per channel. So the outputs are anchor-major, (1, N, 4) and (1, N, C), +which is the NPU's NHWC order flattened (channel-major outputs cost 209 such +copies), and the two attention blocks take q, k and v as column slices of the +(1, N, C) token view (TokenMajorAttention) instead of the (1, heads, dims, N) +view Ultralytics uses (about 870 copies). +""" + +from __future__ import annotations + +import copy +import os +from pathlib import Path + +import numpy as np +import torch +from torch import nn + +from model import MethodSpec +from yolo import ( # noqa: F401 (re-exported for the scripts in traffic/) + LETTERBOX_FILL, + STRIDES, + anchors, + coco128_images, + letterbox, + num_anchors, + to_input, +) +import yolo +from ultralytics.nn.modules.block import PSABlock + +# COCO index and name of each output channel, in order. +CLASSES = ((1, "bicycle"), (2, "car"), (3, "motorcycle"), (5, "bus"), (7, "truck")) +CLASS_INDICES = [c for c, _ in CLASSES] +CLASS_NAMES = [n for _, n in CLASSES] +IMAGE_SIZE = int(os.environ.get("YOLO_IMGSZ", "416")) # square input, a multiple of 32 +CALIBRATION_IMAGES = 64 + +CACHE = Path(__file__).resolve().parent / ".cache" + + +class TokenMajorAttention(nn.Module): + """The attention of a YOLO26 PSABlock, the same arithmetic on the channels-last token view. + + Ultralytics views the qkv map as (B, heads, 2 * key_dim + head_dim, N) and + splits q, k, v along the dims axis: on the NPU's NHWC tensors that view is + a transpose. Here q, k and v of each head are column slices of the + (B, N, channels) view of the NHWC map, which is free.""" + + def __init__(self, attn: nn.Module) -> None: + super().__init__() + self.qkv, self.proj, self.pe = attn.qkv, attn.proj, attn.pe + self.heads, self.key_dim, self.head_dim, self.scale = attn.num_heads, attn.key_dim, attn.head_dim, attn.scale + + def forward(self, x: torch.Tensor) -> torch.Tensor: + B, C, H, W = x.shape + kd = self.key_dim + tokens = self.qkv(x).permute(0, 2, 3, 1).reshape(B, H * W, self.heads, 2 * kd + self.head_dim) + out, values = [], [] + for h in range(self.heads): + q = tokens[:, :, h, :kd] * self.scale + k = tokens[:, :, h, kd : 2 * kd] + v = tokens[:, :, h, 2 * kd :] + out.append((q @ k.transpose(1, 2)).softmax(-1) @ v) + values.append(v) + o = torch.cat(out, -1).reshape(B, H, W, C).permute(0, 3, 1, 2) + v = torch.cat(values, -1).reshape(B, H, W, C).permute(0, 3, 1, 2) + return self.proj(o + self.pe(v)) + + +class YoloVehicles(nn.Module): + """YOLO26n up to the raw one-to-one head outputs, the vehicle classes only; see the module docstring.""" + + def __init__(self, detection_model: nn.Module, classes: list[int] | None = None) -> None: + super().__init__() + classes = classes or CLASS_INDICES + self.layers = detection_model.model[:-1] + self.save = set(detection_model.save) + head = detection_model.model[-1] + self.from_ = list(head.f) + self.box_head = head.one2one_cv2 + cls_head = copy.deepcopy(head.one2one_cv3) + for branch in cls_head: + full = branch[-1] + few = nn.Conv2d(full.in_channels, len(classes), kernel_size=1, bias=True) + few.weight.data = full.weight.data[classes].clone() + few.bias.data = full.bias.data[classes].clone() + branch[-1] = few + self.cls_head = cls_head + for block in self.layers.modules(): + if isinstance(block, PSABlock): + block.attn = TokenMajorAttention(block.attn) + + def forward(self, image: torch.Tensor) -> tuple[torch.Tensor, torch.Tensor]: + x = image.permute(0, 3, 1, 2) # NHWC -> NCHW + saved: list[torch.Tensor | None] = [] + for m in self.layers: + if m.f != -1: + x = saved[m.f] if isinstance(m.f, int) else [x if j == -1 else saved[j] for j in m.f] + x = m(x) + saved.append(x if m.i in self.save else None) + feats = [saved[j] for j in self.from_] + # Anchor-major: each map's NHWC order flattened, (1, N, 4) and (1, N, C). + box = torch.cat([b(f).permute(0, 2, 3, 1).flatten(1, 2) for b, f in zip(self.box_head, feats)], dim=1) + cls = torch.cat([c(f).permute(0, 2, 3, 1).flatten(1, 2) for c, f in zip(self.cls_head, feats)], dim=1) + return box, torch.sigmoid(cls) + + +def decode(box: np.ndarray, score: np.ndarray, threshold: float, size: int | None = None) -> np.ndarray: + """Head outputs of one image, (N, 4) and (N, C), to detections (K, 6): x1, y1, x2, y2 in input pixels, score, class. + + What traffic/detector.cpp does on the board: the best class per anchor, then the threshold.""" + size = size or IMAGE_SIZE + centre, stride = anchors(size) + best = score.argmax(1) + conf = score[np.arange(score.shape[0]), best] + keep = np.nonzero(conf > threshold)[0] + ltrb = box[keep] + c = centre[keep] + xyxy = np.concatenate([c - ltrb[:, :2], c + ltrb[:, 2:]], 1) * stride[keep, None] + return np.concatenate([xyxy, conf[keep, None], best[keep, None].astype(np.float32)], 1) + + +# --------------------------------------------------------------------------- +# The attention on the CPU. The Ethos-U55 has no matrix multiply: Vela runs +# each of the two per-block products (q k^T and the attention-weighted sum of +# v) as one broadcast multiply with int32 results plus one REDUCE_SUM per +# row, 8 bytes of SRAM traffic per MAC, about 50 of the 80 ms of the whole +# network for 1 % of its MACs. With TRAFFIC_ATTENTION=cpu (the default) the +# network is cut around the two attention cores into three NPU methods, +# +# stem(image) -> l4, l6, y10, qkv10 +# mid(o10, qkv10, y10, l4, l6) -> qkv22, z22, y22, box34, cls34 +# head(o22, qkv22, z22, y22, box34, cls34) -> box, cls +# +# and the CPU (traffic/attention.c) turns qkv into o = softmax(q k^T s) v per +# head in between. Every tensor crosses in NHWC (the NPU's order, no +# transposes). mid already runs the stride 8 and 16 heads (box34, and cls34 +# as logits); head appends the stride 32 anchors and takes the sigmoid, so +# box and cls are `detect`'s outputs, one int8 range each: a score output of +# the stride 8 + 16 anchors alone got the range of what COCO128 scores there +# (up to 0.19) and clipped every stronger detection. +# The same tensor gets different quantization parameters as an output of one +# method and an input of the next (concatenations share one range), so the +# CPU requantizes on the way. TRAFFIC_ATTENTION=npu exports the single +# `detect` method instead. +# --------------------------------------------------------------------------- +ATTENTION = os.environ.get("TRAFFIC_ATTENTION", "cpu") +# The weights: TRAFFIC_WEIGHTS, else YOLO26n without its attention blocks +# fine-tuned on the COCO images with vehicles (model/yolo26n-noattn.yaml trained +# by traffic/train_vehicles.py, committed as model/yolo26n-noattn-vehicles.pt), +# else the COCO-pretrained yolo26n.pt. A network without PSA blocks is always +# the single method `detect`: there is no attention to take off the NPU. +TRAINED = Path(__file__).resolve().parent / "yolo26n-noattn-vehicles.pt" +WEIGHTS = os.environ.get("TRAFFIC_WEIGHTS") or (str(TRAINED) if TRAINED.is_file() else None) + + +def load_detection_model(weights: str | Path | None = None) -> nn.Module: + """yolo.load_detection_model() of `weights`, TRAFFIC_WEIGHTS, the fine-tuned model or yolo26n.pt.""" + weights = weights or WEIGHTS + print(f"[traffic] weights: {weights or yolo.CACHE / yolo.WEIGHTS}") + return yolo.load_detection_model(weights) + + +def _nhwc(x: torch.Tensor) -> torch.Tensor: + return x.permute(0, 2, 3, 1) + + +def _nchw(x: torch.Tensor) -> torch.Tensor: + return x.permute(0, 3, 1, 2) + + +def _anchor_major(x: torch.Tensor) -> torch.Tensor: + return x.permute(0, 2, 3, 1).flatten(1, 2) + + +def attention_core(qkv: torch.Tensor, attn: TokenMajorAttention) -> torch.Tensor: + """The CPU part in float: NHWC qkv (B, H, W, heads * (2 kd + hd)) -> o (B, H, W, heads * hd).""" + B, H, W, _ = qkv.shape + kd, hd = attn.key_dim, attn.head_dim + t = qkv.reshape(B, H * W, attn.heads, 2 * kd + hd) + out = [ + ((t[:, :, h, :kd] * attn.scale) @ t[:, :, h, kd : 2 * kd].transpose(1, 2)).softmax(-1) @ t[:, :, h, 2 * kd :] + for h in range(attn.heads) + ] + return torch.cat(out, -1).reshape(B, H, W, attn.heads * hd) + + +def _round(x: np.ndarray) -> np.ndarray: + return np.sign(x) * np.floor(np.abs(x) + 0.5) # half away from zero, like vcvtaq / lroundf + + +def attention_core_int8( + qkv: np.ndarray, qkv_qp: tuple[float, int], out_qp: tuple[float, int], attn: TokenMajorAttention +) -> np.ndarray: + """What traffic/attention.c computes, for the host evaluation: int8 (H, W, heads * (2 kd + hd)) -> int8 (H, W, heads * hd). + + Per head and query row i: exact int32 dot products d_ij of the zero-point + corrected q and k, e_ij = exp((d_ij - max_j d_ij) s_q s_k scale), p_ij = + round(255 e_ij) as uint8 (relative to the row's largest weight), then + o_ic = sum_j p_ij (v_jc - zp) / sum_j p_ij, requantized to the scale the + next NPU method expects.""" + (s_in, zp), (s_out, zp_out) = qkv_qp, out_qp + H, W, _ = qkv.shape + kd, hd = attn.key_dim, attn.head_dim + t = qkv.reshape(H * W, attn.heads, 2 * kd + hd).astype(np.int64) + out = np.empty((H * W, attn.heads * hd), np.int8) + c = np.float32(s_in * s_in * attn.scale) + for h in range(attn.heads): + q, k, v = t[:, h, :kd] - zp, t[:, h, kd : 2 * kd] - zp, t[:, h, 2 * kd :] + d = q @ k.T + e = np.exp(((d - d.max(1, keepdims=True)).astype(np.float32) * c)) + p = np.floor(e * 255 + 0.5).astype(np.int64) + sp = p.sum(1, keepdims=True) + acc = p @ (v + 128) - (128 + zp) * sp + o = acc.astype(np.float32) * (np.float32(s_in / s_out) / sp.astype(np.float32)) + out[:, h * hd : (h + 1) * hd] = np.clip(_round(o) + zp_out, -128, 127) + return out.reshape(H, W, attn.heads * hd) + + +def _finish_psa(block: nn.Module, x: torch.Tensor, o: torch.Tensor, qkv: torch.Tensor) -> torch.Tensor: + """The rest of a PSABlock once the CPU has the attention core o: pe(v), proj, both residuals, the FFN.""" + attn = block.attn + B, H, W, _ = o.shape + kd = attn.key_dim + v = qkv.reshape(B, H * W, attn.heads, 2 * kd + attn.head_dim)[..., 2 * kd :].reshape(B, H, W, -1) + x = x + attn.proj(_nchw(o) + attn.pe(_nchw(v))) + return x + block.ffn(x) + + +class Stem(nn.Module): + """Layers 0-9 and layer 10 (C2PSA) up to its attention's qkv: image -> l4, l6, y10 (cv1 of layer 10), qkv10.""" + + def __init__(self, net: YoloVehicles) -> None: + super().__init__() + self.net = net + + def forward(self, image: torch.Tensor) -> tuple[torch.Tensor, ...]: + layers = self.net.layers + x = image.permute(0, 3, 1, 2) + for i in range(10): + x = layers[i](x) + if i == 4: + l4 = x + elif i == 6: + l6 = x + c2psa = layers[10] + y = c2psa.cv1(x) + qkv = c2psa.m[0].attn.qkv(y[:, c2psa.c :]) + return _nhwc(l4), _nhwc(l6), _nhwc(y), _nhwc(qkv) + + +class Mid(nn.Module): + """The rest of layer 10, the neck (11-21), layer 22 (C3k2 with PSA) up to its qkv, and the stride 8 and 16 heads.""" + + def __init__(self, net: YoloVehicles) -> None: + super().__init__() + self.net = net + + def forward(self, o10, qkv10, y10, l4, l6) -> tuple[torch.Tensor, ...]: + net = self.net + c2psa = net.layers[10] + y = _nchw(y10) + b = _finish_psa(c2psa.m[0], y[:, c2psa.c :], o10, qkv10) + x = c2psa.cv2(torch.cat((y[:, : c2psa.c], b), 1)) + saved = {4: _nchw(l4), 6: _nchw(l6), 10: x} + for m in net.layers[11:22]: + if m.f != -1: + x = saved[m.f] if isinstance(m.f, int) else [x if j == -1 else saved[j] for j in m.f] + x = m(x) + if m.i in net.save: + saved[m.i] = x + c3k2 = net.layers[22] + y22 = c3k2.cv1(x) + z = c3k2.m[0][0](y22[:, c3k2.c :]) + qkv22 = c3k2.m[0][1].attn.qkv(z) + feats = [saved[j] for j in net.from_[:2]] + box = torch.cat([_anchor_major(b(f)) for b, f in zip(net.box_head[:2], feats)], dim=1) + cls = torch.cat([_anchor_major(c(f)) for c, f in zip(net.cls_head[:2], feats)], dim=1) + return _nhwc(qkv22), _nhwc(z), _nhwc(y22), box, cls + + +class Head(nn.Module): + """The rest of layer 22 and the stride 32 head, appended to mid's stride 8 and 16 anchors.""" + + def __init__(self, net: YoloVehicles) -> None: + super().__init__() + self.net = net + + def forward(self, o22, qkv22, z22, y22, box34, cls34) -> tuple[torch.Tensor, torch.Tensor]: + net = self.net + c3k2 = net.layers[22] + y = _nchw(y22) + y2 = _finish_psa(c3k2.m[0][1], _nchw(z22), o22, qkv22) + x = c3k2.cv2(torch.cat((y[:, : c3k2.c], y[:, c3k2.c :], y2), 1)) + box = torch.cat((box34, _anchor_major(net.box_head[2](x))), 1) + return box, torch.sigmoid(torch.cat((cls34, _anchor_major(net.cls_head[2](x))), 1)) + + +class Split: + """stem -> attention core -> mid -> attention core -> head, as the board runs it; float, or quantized.""" + + def __init__(self, net: YoloVehicles) -> None: + self.stem, self.mid, self.head = Stem(net).eval(), Mid(net).eval(), Head(net).eval() + self.attn10 = net.layers[10].m[0].attn + self.attn22 = net.layers[22].m[0][1].attn + self.quantized = None + + def stages(self, image: torch.Tensor) -> list[tuple[torch.Tensor, ...]]: + """The float inputs of stem, mid and head for one image (the calibration samples).""" + with torch.no_grad(): + l4, l6, y10, qkv10 = self.stem(image) + mid_in = (attention_core(qkv10, self.attn10), qkv10, y10, l4, l6) + qkv22, z22, y22, box34, cls34 = self.mid(*mid_in) + return [(image,), mid_in, (attention_core(qkv22, self.attn22), qkv22, z22, y22, box34, cls34)] + + def __call__(self, image: torch.Tensor) -> tuple[torch.Tensor, torch.Tensor]: + if self.quantized is not None: + return self._int8(image) + with torch.no_grad(): + return self.head(*self.stages(image)[2]) + + def quantize(self, quantize_method) -> "Split": + """The same pipeline with the PT2E-quantized methods and the integer core (attention_core_int8).""" + q = Split.__new__(Split) + q.attn10, q.attn22 = self.attn10, self.attn22 + q.quantized = {m.name: (quantize_method(m), m) for m in self.methods()} + q.qparams = {name: io_qparams(gm) for name, (gm, _) in q.quantized.items()} + return q + + def _int8(self, image: torch.Tensor) -> tuple[torch.Tensor, torch.Tensor]: + stem, mid, head = (self.quantized[n][0] for n in ("stem", "mid", "head")) + qp = self.qparams + + def core(qkv, qkv_qp, out_qp, attn): + s, z = qkv_qp + qkv_q = torch.clamp(torch.round(qkv / s) + z, -128, 127)[0].numpy().astype(np.int8) + o = attention_core_int8(qkv_q, qkv_qp, out_qp, attn) + return torch.from_numpy((o.astype(np.float32) - out_qp[1]) * out_qp[0])[None] + + with torch.no_grad(): + l4, l6, y10, qkv10 = stem(image) + o10 = core(qkv10, qp["stem"][1][3], qp["mid"][0][0], self.attn10) + qkv22, z22, y22, box34, cls34 = mid(o10, qkv10, y10, l4, l6) + o22 = core(qkv22, qp["mid"][1][0], qp["head"][0][0], self.attn22) + return head(o22, qkv22, z22, y22, box34, cls34) + + def methods(self) -> list[MethodSpec]: + samples = [self.stages(image) for (image,) in _samples()] + return [ + MethodSpec("stem", self.stem, [s[0] for s in samples]), + MethodSpec("mid", self.mid, [s[1] for s in samples]), + MethodSpec("head", self.head, [s[2] for s in samples]), + ] + + +def io_qparams(gm: torch.fx.GraphModule) -> tuple[list[tuple[float, int]], list[tuple[float, int]]]: + """(scale, zero point) of each input and output of a PT2E-quantized module.""" + ins, outs = [], [] + for n in gm.graph.nodes: + if n.op == "placeholder": + q = next(u for u in n.users if "quantize_per_tensor" in str(u.target)) + ins.append((float(q.args[1]), int(q.args[2]))) + elif n.op == "output": + outs = [(float(d.args[1]), int(d.args[2])) for d in n.args[0]] + return ins, outs + + +def _samples() -> list[tuple[torch.Tensor]]: + """Letterboxed COCO128 images, those with vehicles first (they pin the score output's range).""" + import cv2 + + images = coco128_images() + labels = CACHE / "coco128" / "labels" / "train2017" + wanted = {str(c) for c in CLASS_INDICES} + + def vehicles(p: Path) -> int: + f = labels / (p.stem + ".txt") + return sum(line.split()[0] in wanted for line in f.read_text().splitlines()) if f.is_file() else 0 + + ordered = sorted(images, key=lambda p: -vehicles(p))[:CALIBRATION_IMAGES] + return [(to_input(letterbox(cv2.imread(str(p)), IMAGE_SIZE)[0]),) for p in ordered] + + +def _has_attention(net: YoloVehicles) -> bool: + return any(isinstance(m, TokenMajorAttention) for m in net.modules()) + + +def get_traffic_methods() -> list[MethodSpec]: + yolo.IMAGE_SIZE = IMAGE_SIZE + net = YoloVehicles(load_detection_model()).eval() + if ATTENTION == "npu" or not _has_attention(net): + return [MethodSpec("detect", net, _samples())] + return Split(net).methods() + + +def runners(quantize_method) -> tuple: + """The float and the int8 detector as the board runs it, image -> (box (1, N, 4), score (1, N, C)). + + `quantize_method(spec)` is create_ai_layer.quantize_method bound to the + compile spec; the int8 one is its fake quantization on the host (plus the + integer attention core with TRAFFIC_ATTENTION=cpu).""" + yolo.IMAGE_SIZE = IMAGE_SIZE + net = YoloVehicles(load_detection_model()).eval() + if ATTENTION == "npu" or not _has_attention(net): + return net, quantize_method(MethodSpec("detect", net, _samples())) + split = Split(net) + return split, split.quantize(quantize_method) diff --git a/model/yolo.py b/model/yolo.py new file mode 100644 index 0000000..af8601c --- /dev/null +++ b/model/yolo.py @@ -0,0 +1,101 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +"""Ultralytics YOLO26n: what the traffic counter's model (traffic.py) and its scripts share. + +YOLO26 is NMS-free: its one-to-one head gives at most one box per object, so +what is left after the network is a threshold, no non-maximum suppression. +traffic.py takes YOLO26n, keeps the one-to-one head and cuts the network +where the NPU stops being useful. This module has the parts around it: the +weights (load_detection_model), the anchors of the three feature maps (the +N = (S/8)^2 + (S/16)^2 + (S/32)^2 cells, row by row, stride 8 first), the +letterbox the application uses too, and the COCO128 images (train2017, +downloaded on first use into model/.cache/) that calibrate the quantization. +""" + +from __future__ import annotations + +import copy +import os +import urllib.request +import zipfile +from pathlib import Path + +import numpy as np +import torch +from torch import nn + +IMAGE_SIZE = int(os.environ.get("YOLO_IMGSZ", "416")) # square input, a multiple of 32 +STRIDES = (8, 16, 32) +LETTERBOX_FILL = 114 # the Ultralytics pad colour, also what the application pads with + +CACHE = Path(__file__).resolve().parent / ".cache" +WEIGHTS = "yolo26n.pt" +COCO128_URL = "https://github.com/ultralytics/assets/releases/download/v0.0.0/coco128.zip" + + +def num_anchors(size: int | None = None) -> int: + size = size or IMAGE_SIZE + return sum((size // s) ** 2 for s in STRIDES) + + +def load_detection_model(weights: str | Path | None = None) -> nn.Module: + """The COCO-pretrained YOLO26n (or `weights`), BatchNorm folded, one-to-one head only (Ultralytics downloads the weights).""" + from ultralytics import YOLO + + CACHE.mkdir(exist_ok=True) + model = YOLO(str(weights or CACHE / WEIGHTS)).model + model = copy.deepcopy(model).float().eval() + model.model[-1].end2end = True # fuse() then drops the one-to-many branch and keeps one2one_* + return model.fuse(verbose=False) + + +def anchors(size: int | None = None) -> tuple[np.ndarray, np.ndarray]: + """Anchor centres (N, 2) in grid units and strides (N,), in the order of the head outputs.""" + size = size or IMAGE_SIZE + centres, strides = [], [] + for s in STRIDES: + n = size // s + ys, xs = np.meshgrid(np.arange(n) + 0.5, np.arange(n) + 0.5, indexing="ij") + centres.append(np.stack([xs.ravel(), ys.ravel()], 1)) + strides.append(np.full(n * n, s, dtype=np.float32)) + return np.concatenate(centres).astype(np.float32), np.concatenate(strides) + + +def letterbox(bgr: np.ndarray, size: int | None = None) -> tuple[np.ndarray, float, tuple[int, int]]: + """Resize the longer side to `size`, pad to a square with the Ultralytics grey; RGB uint8, the scale and the (x, y) pad.""" + import cv2 + + size = size or IMAGE_SIZE + + h, w = bgr.shape[:2] + r = size / max(h, w) + nw, nh = round(w * r), round(h * r) + resized = cv2.resize(bgr, (nw, nh), interpolation=cv2.INTER_AREA if r < 1 else cv2.INTER_LINEAR) + out = np.full((size, size, 3), LETTERBOX_FILL, dtype=np.uint8) + px, py = (size - nw) // 2, (size - nh) // 2 + out[py : py + nh, px : px + nw] = resized[:, :, ::-1] + return out, r, (px, py) + + +def to_input(rgb: np.ndarray) -> torch.Tensor: + return torch.from_numpy(rgb).float().div(255.0).unsqueeze(0) # (1, S, S, 3) + + +def coco128_images() -> list[Path]: + root = CACHE / "coco128" + if not root.is_dir(): + CACHE.mkdir(exist_ok=True) + archive = CACHE / "coco128.zip" + print(f"[yolo] downloading {COCO128_URL}") + # The python.org interpreters on macOS come without CA certificates: use certifi's (a requests dependency). + import ssl + + import certifi + + context = ssl.create_default_context(cafile=certifi.where()) + with urllib.request.urlopen(COCO128_URL, context=context) as response: + archive.write_bytes(response.read()) + with zipfile.ZipFile(archive) as z: + z.extractall(CACHE) + archive.unlink() + return sorted((root / "images" / "train2017").glob("*.jpg")) diff --git a/model/yolo26n-noattn-vehicles.pt b/model/yolo26n-noattn-vehicles.pt new file mode 100644 index 0000000000000000000000000000000000000000..fd86c94f7938782cdd0ae78605a92ee16e6b4e74 GIT binary patch literal 5515721 zcmb512YeJ&_x=NlKtx3BqKG}QKzhMK70>|UV8MbRgun(u!k$b()KvtR1uNKl@4bt? z_paD`?_%%e|2+4(Gl{#rpCA9%_jB&|p4pwd=ghg!9VWB0<7!r0Juk0Yx4fMHt(CWa z-sFbXaKMzhu&)2C8BHUGu9J6Q_W$N}P9^gSCSV_VcwIxX(}aG&lA@A|orAq&=oJ6-C(VaEzQZ*T(7EsS^wgS;^gYC*VI_w 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